BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: CM8A34012

-- ***************************************************************
--      Company: Integrated Device Technology, Inc. 
--
--      Part : CM8A34012
--
--      Title: BSDL file of CM8A34012
--      Generated by : AS
--
--      Release status: formal issue
--      Security level: client use
--      BSDL Version 2001
--      Revision History:
--              Mar 19, 2018:   initial release
--              Jun 13, 2018:   ID[4:0] == [nc,nc,nc,nc,nc] == variant31 == 0x64F
--
-- Generated by boundaryScanGenerate 2015.2-p1      Mon Jun 29 23:40:43 GMT 2015 on 09/10/16 18:53:05
-- BSDL Version 2001

entity CM8A34012 is 
    generic (PHYSICAL_PIN_MAP : string := "QFN_72");

    port (
        -- Port List
        OSCI                 : linkage  bit;
        OSCO                 : linkage  bit;
        XO_DPLL              : linkage  bit;
        nMR1                  : in       bit;
        SCL_M                : inout    bit;
        SDA_M                : inout    bit;
        SCLK                 : inout    bit;
        SDIO                 : inout    bit;
        SDI_A1               : inout    bit;
        CS_A0                : inout    bit;
        nTEST                : in       bit;
        CLK0                 : linkage  bit;
        CLK1                 : linkage  bit;
        CLK2                 : linkage  bit;
        CLK3                 : linkage  bit;
        CLK4                 : linkage  bit;
        CLK5                 : linkage  bit;
        CLK6                 : linkage  bit;
        nCLK0                : linkage  bit;
        nCLK1                : linkage  bit;
        nCLK2                : linkage  bit;
        nCLK3                : linkage  bit;
        nCLK4                : linkage  bit;
        nCLK5                : linkage  bit;
        nCLK6                : linkage  bit;
        Q0                   : linkage  bit;
        Q1                   : linkage  bit;
        Q2                   : linkage  bit;
        Q3                   : linkage  bit;
        Q4                   : linkage  bit;
        Q5                   : linkage  bit;
        Q6                   : linkage  bit;
        Q7                   : linkage  bit;
        nQ0                  : linkage  bit;
        nQ1                  : linkage  bit;
        nQ2                  : linkage  bit;
        nQ3                  : linkage  bit;
        nQ4                  : linkage  bit;
        nQ5                  : linkage  bit;
        nQ6                  : linkage  bit;
        nQ7                  : linkage  bit;
        GPIO_DC0             : in       bit;
        GPIO_DC1             : in       bit;
        GPIO_DC2             : in       bit;
        GPIO_DC3             : out      bit;
        GPIO_DC4             : in       bit;
        GPIO_DC5             : inout    bit;
        GPIO_DC8             : inout    bit;
        GPIO_DC9             : inout    bit;
        FILTER_PAD          : linkage  bit;
        VDDA_BANDGAP         : linkage  bit;
        VDD_DIGITAL_IN_ANALOG_BOTTOM         : linkage  bit;
        VDDA_FBDIV           : linkage  bit;
        VDDA_LC              : linkage  bit;
--        VDDA_PDCP            : linkage  bit;
        VDD_CLK0             : linkage  bit;
        VDD_CLK1             : linkage  bit;
        VDDD                 : linkage  bit;
        VSSD                 : linkage  bit;
        VDD_FOD_Q0_Q1        : linkage  bit;
--        VDD_FOD_Q2_Q3        : linkage  bit;
        VDD_FOD_Q4_Q5        : linkage  bit;
--        VDD_FOD_Q6_Q7        : linkage  bit;
        VDDO_Q0            : linkage  bit;
        VDDO_Q1            : linkage  bit;
        VDDO_Q2            : linkage  bit;
        VDDO_Q3            : linkage  bit;
        VDDO_Q4            : linkage  bit;
        VDDO_Q5            : linkage  bit;
        VDDO_Q6            : linkage  bit;
        VDDO_Q7            : linkage  bit;
        VDDA_XTAL            : linkage  bit;
        VREG_XTAL            : linkage  bit);

    use STD_1149_1_2001.all;
    use LVS_BSCAN_CELLS.all;

    attribute COMPONENT_CONFORMANCE of CM8A34012: entity is "STD_1149_1_2001";

    --Pin mappings

    attribute PIN_MAP of CM8A34012: entity is PHYSICAL_PIN_MAP;

    constant QFN_72: PIN_MAP_STRING := 
    "OSCI                 : 67    , " &
    "OSCO                 : 66    , " &
    "XO_DPLL              : 72    , " &
    "nMR1                  : 70    , " &
    "SCL_M                : 18    , " &
    "SDA_M                : 17    , " &
    "SCLK                 : 20    , " &
    "SDIO                 : 21    , " &
    "SDI_A1               : 22    , " &
    "CS_A0                : 23    , " &
    "nTEST                : 27   , " &
    "CLK0                 : 1   , " &
    "CLK1                 : 3   , " &
    "CLK2                 : 5   , " &
    "CLK3                 : 7   , " &
    "CLK4                 : 11   , " &
    "CLK5                 : 13   , " &
    "CLK6                 : 15   , " &
    "nCLK0                : 2   , " &
    "nCLK1                : 4   , " &
    "nCLK2                : 6   , " &
    "nCLK3                : 8   , " &
    "nCLK4                : 12   , " &
    "nCLK5                : 14   , " &
    "nCLK6                : 16   , " &
    "Q0                   : 60   , " &
    "Q1                   : 56   , " &
    "Q2                   : 53   , " &
    "Q3                   : 49   , " &
    "Q4                   : 43   , " &
    "Q5                   : 39   , " &
    "Q6                   : 36   , " &
    "Q7                   : 32   , " &
    "nQ0                  : 59   , " &
    "nQ1                  : 57   , " &
    "nQ2                  : 52   , " &
    "nQ3                  : 48   , " &
    "nQ4                  : 44   , " &
    "nQ5                  : 40   , " &
    "nQ6                  : 35   , " &
    "nQ7                  : 33   , " &
    "GPIO_DC0             : 64   , " &
    "GPIO_DC1             : 47   , " &
    "GPIO_DC2             : 45   , " &
    "GPIO_DC3             : 28   , " &
    "GPIO_DC4             : 58   , " &
    "GPIO_DC5             : 51  , " &
    "GPIO_DC8             : 41   , " &
    "GPIO_DC9             : 34   , " &
    "FILTER_PAD          : 24   , " &
    "VDDA_BANDGAP         : 26   , " &
    "VDD_DIGITAL_IN_ANALOG_BOTTOM         : 29   , " &
    "VDDA_FBDIV           : 69   , " &
    "VDDA_LC              : 25   , " &
--    "VDDA_PDCP            : 68   , " &
    "VDD_CLK0             : 71   , " &
    "VDD_CLK1             : 19   , " &
    "VDDD                 : 9   , " &
    "VSSD                 : 10   , " &
    "VDD_FOD_Q0_Q1        : 62   , " &
--    "VDD_FOD_Q2_Q3        : 62   , " &
    "VDD_FOD_Q4_Q5        : 30   , " &
--    "VDD_FOD_Q6_Q7        : 30   , " &
    "VDDO_Q0              : 61   , " &
    "VDDO_Q1              : 55   , " &
    "VDDO_Q2              : 54   , " &
    "VDDO_Q3              : 50   , " &
    "VDDO_Q4              : 42   , " &
    "VDDO_Q5              : 38   , " &
    "VDDO_Q6              : 37   , " &
    "VDDO_Q7              : 31   , " &
    "VDDA_XTAL            : 68  , " &
    "VREG_XTAL            : 65   " ;

   attribute TAP_SCAN_RESET of GPIO_DC4                     : signal is true;
   attribute TAP_SCAN_IN    of GPIO_DC2                     : signal is true;
   attribute TAP_SCAN_MODE  of GPIO_DC1                     : signal is true;
   attribute TAP_SCAN_OUT   of GPIO_DC3                     : signal is true;
   attribute TAP_SCAN_CLOCK of GPIO_DC0                     : signal is (1.0000000000000000000e+07, BOTH);


    attribute COMPLIANCE_PATTERNS of CM8A34012 : entity is 
        "(nTEST) (0)";
   attribute INSTRUCTION_LENGTH of CM8A34012: entity is 18;
 
   attribute INSTRUCTION_OPCODE of CM8A34012: entity is
      "IDCODE       (111111111111111110)," &
      "BYPASS       (111111111111111111)," &
      "EXTEST       (111111111111101000)," &
      "SAMPLE       (111111111111111000)," &
      "PRELOAD      (111111111111111000)," &
      "HIGHZ        (111111111111001111)," &
      "CLAMP        (111111111111101111) " ;
 
   attribute INSTRUCTION_CAPTURE of CM8A34012: entity is "xxxxxxxxxxxxxxxx01";
 
   attribute IDCODE_REGISTER of CM8A34012: entity is
      "0000"             & -- version
      "0000011001001110" & -- part number
      "00000110011"      & -- manufacturer's identity
      "1";                   -- required by 1149.1
 
   attribute REGISTER_ACCESS of CM8A34012: entity is
      "DEVICE_ID    ( IDCODE ), " &
      "BOUNDARY     ( SAMPLE, PRELOAD, EXTEST )," &
      "BYPASS       ( HIGHZ, CLAMP, BYPASS ) " ;


    --Boundary scan definition
    attribute BOUNDARY_LENGTH of CM8A34012: entity is 43;

    attribute BOUNDARY_REGISTER of CM8A34012: entity is 
    -- num  cell         port               function       safe     [ccell disval  rslt]
    "  42   (BC_4       , nMR1              , observe_only , X   )                          ,"&
    "  41   (BC_2       , *                , control      , 1   )                          ,"&
    "  40   (LV_BC_7    , SCL_M            , bidir        , X    ,   41     , 1     , Z   ),"&
    "  39   (BC_2       , *                , control      , 1   )                          ,"&
    "  38   (LV_BC_7    , SDA_M            , bidir        , X    ,   39     , 1     , Z   ),"&
    "  37   (BC_2       , *                , control      , 1   )                          ,"&
    "  36   (LV_BC_7    , SCLK             , bidir        , X    ,   37     , 1     , Z   ),"&
    "  35   (BC_2       , *                , control      , 1   )                          ,"&
    "  34   (LV_BC_7    , SDIO             , bidir        , X    ,   35     , 1     , Z   ),"&
    "  33   (BC_2       , *                , control      , 1   )                          ,"&
    "  32   (LV_BC_7    , SDI_A1           , bidir        , X    ,   33     , 1     , Z   ),"&
    "  31   (BC_2       , *                , control      , 1   )                          ,"&
    "  30   (LV_BC_7    , CS_A0            , bidir        , X    ,   31     , 1     , Z   ),"&
    "  29   (BC_0       , *                , internal      , 0   )                          ,"&
    "  28   (BC_0    , *         , internal        , 0    ),"&
    "  27   (BC_0       , *                , internal      , 0   )                          ,"&
    "  26   (BC_0    , *         , internal        , 0  ),"&
    "  25   (BC_0       , *                , internal      , 0   )                          ,"&
    "  24   (BC_0    , *       , internal        , 0  ),"&
    "  23   (BC_0       , *                , internal      , 0   )                          ,"&
    "  22   (BC_0    , *        , internal        , 0  ),"&
    "  21   (BC_2       , *                , control      , 1   )                          ,"&
    "  20   (LV_BC_7    , GPIO_DC5         , bidir        , X    ,   21     , 1     , Z   ),"&
    "  19   (BC_0       , *                , internal      , 0   )                          ,"&
    "  18   (BC_0    , *         , internal        , 0 ),"&
    "  17   (BC_0       , *                , internal      , 0   )                          ,"&
    "  16   (BC_0    , *         , internal        , 0 ),"&
    "  15   (BC_2       , *                , control      , 1   )                          ,"&
    "  14   (LV_BC_7    , GPIO_DC8         , bidir        , X    ,   15     , 1     , Z   ),"&
    "  13   (BC_2       , *                , control      , 1   )                          ,"&
    "  12   (LV_BC_7    , GPIO_DC9         , bidir        , X    ,   13     , 1     , Z   ),"&
    "  11   (BC_0       , *                , internal      , 0   )                          ,"&
    "  10   (BC_0    , *        , internal        , 0 ),"&
    "  9    (BC_0       , *                , internal      , 0   )                          ,"&
    "  8    (BC_0    , *        , internal        , 0 ),"&
    "  7    (BC_0       , *                , internal      , 0   )                          ,"&
    "  6    (BC_0    , *        , internal        , 0 ),"&
    "  5    (BC_0       , *                , internal      , 0   )                          ,"&
    "  4    (BC_0    , *        , internal        , 0 ),"&
    "  3    (BC_0       , *                , internal      , 0   )                          ,"&
    "  2    (BC_0    , *        , internal        , 0 ),"&
    "  1    (BC_0       , *                , internal      , 0   )                          ,"&
    "  0    (BC_0    , *        , internal        , 0 ) ";

end CM8A34012;
-- VHDL package to be uploaded
--package LVS_BSCAN_CELLS is
--    use STD_1149_1_2001.all;
--        constant LV_BC_7: CELL_INFO;
--
--end LVS_BSCAN_CELLS;
--package body LVS_BSCAN_CELLS is
--    use STD_1149_1_2001.all;
--        constant LV_BC_7: CELL_INFO := 
--           ((BIDIR_IN, EXTEST,  PI),  (BIDIR_OUT, EXTEST,  PO),
--           (BIDIR_IN, SAMPLE,  PI),  (BIDIR_OUT, SAMPLE,  PI),
--           (BIDIR_IN, INTEST,  X),  (BIDIR_OUT, INTEST,  PI));
--
--end LVS_BSCAN_CELLS;
--