----------------------------------------------------------------------
-- AM437x Boundary Scan --
----------------------------------------------------------------------
-- Supported Devices: AM437x Revision 1.2 --
-- Derived from parent device BSDL file --
----------------------------------------------------------------------
-- Created by : Texas Instruments Incorporated --
-- Documentation : AM437x Technical Reference Manual --
-- BSDL Revision : 1.2 Corrected W16, added missing rsv pins, --
-- version number corrected for latest silicon.--
-- Corrected bc_1 paramters for WARMRSTn. --
-- 1.1 Corrected syntax errors --
-- 1.0 originally created --
-- --
-- BSDL Status : Released --
-- Date Created : 30/Sept/2015 --
-- --
----------------------------------------------------------------------
-------------------------------------------------------------------------------
-- --
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-- ------------------------------------------------------------------------- --
entity AM437x is
generic(PHYSICAL_PIN_MAP : string := "ZDN");
port(
gpmc_ad0 : inout bit;
gpmc_ad1 : inout bit;
gpmc_ad2 : inout bit;
gpmc_ad3 : inout bit;
gpmc_ad4 : inout bit;
gpmc_ad5 : inout bit;
gpmc_ad6 : inout bit;
gpmc_ad7 : inout bit;
gpmc_ad8 : inout bit;
gpmc_ad9 : inout bit;
gpmc_ad10 : inout bit;
gpmc_ad11 : inout bit;
gpmc_ad12 : inout bit;
gpmc_ad13 : inout bit;
gpmc_ad14 : inout bit;
gpmc_ad15 : inout bit;
gpmc_a0 : inout bit;
gpmc_a1 : inout bit;
gpmc_a2 : inout bit;
gpmc_a3 : inout bit;
gpmc_a4 : inout bit;
gpmc_a5 : inout bit;
gpmc_a6 : inout bit;
gpmc_a7 : inout bit;
gpmc_a8 : inout bit;
gpmc_a9 : inout bit;
gpmc_a10 : inout bit;
gpmc_a11 : inout bit;
gpmc_wait0 : inout bit;
gpmc_wpn : inout bit;
gpmc_be1n : inout bit;
gpmc_csn0 : inout bit;
gpmc_csn1 : inout bit;
gpmc_csn2 : inout bit;
gpmc_csn3 : inout bit;
gpmc_clk : inout bit;
gpmc_advn_ale : inout bit;
gpmc_oen_ren : inout bit;
gpmc_wen : inout bit;
gpmc_be0n_cle : inout bit;
dss_data0 : inout bit;
dss_data1 : inout bit;
dss_data2 : inout bit;
dss_data3 : inout bit;
dss_data4 : inout bit;
dss_data5 : inout bit;
dss_data6 : inout bit;
dss_data7 : inout bit;
dss_data8 : inout bit;
dss_data9 : inout bit;
dss_data10 : inout bit;
dss_data11 : inout bit;
dss_data12 : inout bit;
dss_data13 : inout bit;
dss_data14 : inout bit;
dss_data15 : inout bit;
dss_vsync : inout bit;
dss_hsync : inout bit;
dss_pclk : inout bit;
dss_ac_bias_en : inout bit;
mmc0_dat3 : inout bit;
mmc0_dat2 : inout bit;
mmc0_dat1 : inout bit;
mmc0_dat0 : inout bit;
mmc0_clk : inout bit;
mmc0_cmd : inout bit;
mii1_col : inout bit;
mii1_crs : inout bit;
mii1_rx_er : inout bit;
mii1_tx_en : inout bit;
mii1_rx_dv : inout bit;
mii1_txd3 : inout bit;
mii1_txd2 : inout bit;
mii1_txd1 : inout bit;
mii1_txd0 : inout bit;
mii1_tx_clk : inout bit;
mii1_rx_clk : inout bit;
mii1_rxd3 : inout bit;
mii1_rxd2 : inout bit;
mii1_rxd1 : inout bit;
mii1_rxd0 : inout bit;
rmii1_ref_clk : inout bit;
mdio_data : inout bit;
mdio_clk : inout bit;
spi0_sclk : inout bit;
spi0_d0 : inout bit;
spi0_d1 : inout bit;
spi0_cs0 : inout bit;
spi0_cs1 : inout bit;
eCAP0_in_PWM0_out : inout bit;
uart0_ctsn : inout bit;
uart0_rtsn : inout bit;
uart0_rxd : inout bit;
uart0_txd : inout bit;
uart1_ctsn : inout bit;
uart1_rtsn : inout bit;
uart1_rxd : inout bit;
uart1_txd : inout bit;
I2C0_SDA : inout bit;
I2C0_SCL : inout bit;
mcasp0_aclkx : inout bit;
mcasp0_fsx : inout bit;
mcasp0_axr0 : inout bit;
mcasp0_ahclkr : inout bit;
mcasp0_aclkr : inout bit;
mcasp0_fsr : inout bit;
mcasp0_axr1 : inout bit;
mcasp0_ahclkx : inout bit;
cam0_hd : inout bit;
cam0_vd : inout bit;
cam0_field : inout bit;
cam0_wen : inout bit;
cam0_pclk : inout bit;
cam0_data8 : inout bit;
cam0_data9 : inout bit;
cam1_data9 : inout bit;
cam1_data8 : inout bit;
cam1_hd : inout bit;
cam1_vd : inout bit;
cam1_pclk : inout bit;
cam1_field : inout bit;
cam1_wen : inout bit;
cam1_data0 : inout bit;
cam1_data1 : inout bit;
cam1_data2 : inout bit;
cam1_data3 : inout bit;
cam1_data4 : inout bit;
cam1_data5 : inout bit;
cam1_data6 : inout bit;
cam1_data7 : inout bit;
cam0_data0 : inout bit;
cam0_data1 : inout bit;
cam0_data2 : inout bit;
cam0_data3 : inout bit;
cam0_data4 : inout bit;
cam0_data5 : inout bit;
cam0_data6 : inout bit;
cam0_data7 : inout bit;
uart3_rxd : inout bit;
uart3_txd : inout bit;
uart3_ctsn : inout bit;
uart3_rtsn : inout bit;
gpio5_8 : inout bit;
gpio5_9 : inout bit;
gpio5_10 : inout bit;
gpio5_11 : inout bit;
gpio5_12 : inout bit;
gpio5_13 : inout bit;
spi4_sclk : inout bit;
spi4_d0 : inout bit;
spi4_d1 : inout bit;
spi4_cs0 : inout bit;
spi2_sclk : inout bit;
spi2_d0 : inout bit;
spi2_d1 : inout bit;
spi2_cs0 : inout bit;
reserved : linkage bit_vector (27 downto 0);
reserved1 : in bit;
-- --
-- reserved1 named VSS in data manual to ensure it is always low --
-- --
xdma_event_intr0 : inout bit;
xdma_event_intr1 : inout bit;
clkreq : inout bit;
WARMRSTn : inout bit;
PWRONRSTn : in bit;
EXTINTn : in bit;
XTALIN : linkage bit;
XTALOUT : linkage bit;
TMS : in bit;
TDI : in bit;
TDO : out bit;
TCK : in bit;
nTRST : in bit;
EMU0 : inout bit;
EMU1 : inout bit;
RTC_XTALIN : linkage bit;
RTC_XTALOUT : linkage bit;
RTC_PWRONRSTn : in bit;
RTC_WAKEUP : in bit;
RTC_PMIC_EN : linkage bit;
RTC_KALDO_ENn : linkage bit;
USB0_DM : linkage bit;
USB0_DP : linkage bit;
USB0_CE : linkage bit;
USB0_ID : linkage bit;
USB0_VBUS : linkage bit;
USB0_DRVVBUS : inout bit;
USB1_DM : linkage bit;
USB1_DP : linkage bit;
USB1_CE : linkage bit;
USB1_ID : linkage bit;
USB1_VBUS : linkage bit;
USB1_DRVVBUS : inout bit;
ddr_resetn : out bit;
ddr_csn0 : inout bit;
ddr_csn1 : inout bit;
ddr_cke0 : inout bit;
ddr_cke1 : inout bit;
ddr_ck : inout bit;
ddr_nck : inout bit;
ddr_casn : inout bit;
ddr_rasn : inout bit;
ddr_wen : inout bit;
ddr_ba0 : inout bit;
ddr_ba1 : inout bit;
ddr_ba2 : inout bit;
ddr_a0 : inout bit;
ddr_a1 : inout bit;
ddr_a2 : inout bit;
ddr_a3 : inout bit;
ddr_a4 : inout bit;
ddr_a5 : inout bit;
ddr_a6 : inout bit;
ddr_a7 : inout bit;
ddr_a8 : inout bit;
ddr_a9 : inout bit;
ddr_a10 : inout bit;
ddr_a11 : inout bit;
ddr_a12 : inout bit;
ddr_a13 : inout bit;
ddr_a14 : inout bit;
ddr_a15 : inout bit;
ddr_odt0 : inout bit;
ddr_odt1 : inout bit;
ddr_d0 : inout bit;
ddr_d1 : inout bit;
ddr_d2 : inout bit;
ddr_d3 : inout bit;
ddr_d4 : inout bit;
ddr_d5 : inout bit;
ddr_d6 : inout bit;
ddr_d7 : inout bit;
ddr_d8 : inout bit;
ddr_d9 : inout bit;
ddr_d10 : inout bit;
ddr_d11 : inout bit;
ddr_d12 : inout bit;
ddr_d13 : inout bit;
ddr_d14 : inout bit;
ddr_d15 : inout bit;
ddr_d16 : inout bit;
ddr_d17 : inout bit;
ddr_d18 : inout bit;
ddr_d19 : inout bit;
ddr_d20 : inout bit;
ddr_d21 : inout bit;
ddr_d22 : inout bit;
ddr_d23 : inout bit;
ddr_d24 : inout bit;
ddr_d25 : inout bit;
ddr_d26 : inout bit;
ddr_d27 : inout bit;
ddr_d28 : inout bit;
ddr_d29 : inout bit;
ddr_d30 : inout bit;
ddr_d31 : inout bit;
ddr_dqm0 : inout bit;
ddr_dqm1 : inout bit;
ddr_dqm2 : inout bit;
ddr_dqm3 : inout bit;
ddr_dqs0 : inout bit;
ddr_dqsn0 : inout bit;
ddr_dqs1 : inout bit;
ddr_dqsn1 : inout bit;
ddr_dqs2 : inout bit;
ddr_dqsn2 : inout bit;
ddr_dqs3 : inout bit;
ddr_dqsn3 : inout bit;
DDR_VREF : linkage bit;
ddr_vtp : linkage bit;
ADC0_AIN7 : linkage bit;
ADC0_AIN6 : linkage bit;
ADC0_AIN5 : linkage bit;
ADC0_AIN4 : linkage bit;
ADC0_AIN3 : linkage bit;
ADC0_AIN2 : linkage bit;
ADC0_AIN1 : linkage bit;
ADC0_AIN0 : linkage bit;
ADC0_VREFP : linkage bit;
ADC0_VREFN : linkage bit;
ADC1_AIN5 : linkage bit;
ADC1_AIN4 : linkage bit;
ADC1_AIN3 : linkage bit;
ADC1_AIN2 : linkage bit;
ADC1_AIN1 : linkage bit;
ADC1_AIN0 : linkage bit;
ADC1_VREFP : linkage bit;
ADC1_VREFN : linkage bit;
ADC1_AIN6 : linkage bit;
ADC1_AIN7 : linkage bit;
CAP_VDDS1P8V_IOLDO : linkage bit;
VDDS3P3V_IOLDO : linkage bit;
VDDA_ADC1 : linkage bit;
VDDA_ADC0 : linkage bit;
VDDSHV10 : linkage bit_vector (1 downto 0);
VDDSHV7 : linkage bit;
VDDSHV8 : linkage bit_vector (1 downto 0);
VDDSHV9 : linkage bit_vector (1 downto 0);
VDDSHV11 : linkage bit_vector (1 downto 0);
VDDS_CLKOUT : linkage bit;
CAP_VBB_MPU : linkage bit;
CAP_VDD_RTC : linkage bit;
CAP_VDD_SRAM_CORE : linkage bit;
CAP_VDD_SRAM_MPU : linkage bit;
VDD_CORE : linkage bit_vector (24 downto 0);
VDD_MPU : linkage bit_vector (11 downto 0);
vdd_mpu_mon : linkage bit;
VDDA1P8V_USB0 : linkage bit;
VDDA1P8V_USB1 : linkage bit;
VDDA3P3V_USB0 : linkage bit;
VDDA3P3V_USB1 : linkage bit;
VDDS : linkage bit_vector (7 downto 0);
VDDS_DDR : linkage bit_vector (12 downto 0);
VDDS_OSC : linkage bit;
VDDS_PLL_CORE_LCD : linkage bit;
VDDS_PLL_DDR : linkage bit;
VDDS_PLL_MPU : linkage bit;
VDDS_RTC : linkage bit;
VDDS_SRAM_CORE_BG : linkage bit;
VDDS_SRAM_MPU_BB : linkage bit;
VDDSHV1 : linkage bit_vector (1 downto 0);
VDDSHV2 : linkage bit_vector (2 downto 0);
VDDSHV3 : linkage bit_vector (6 downto 0);
VDDSHV5 : linkage bit;
VDDSHV6 : linkage bit_vector (2 downto 0);
VSS : linkage bit_vector (67 downto 0);
VSS_OSC : linkage bit;
VSS_RTC : linkage bit;
VSSA_ADC : linkage bit;
VSSA_USB : linkage bit
);
use STD_1149_1_2001.all; -- Get standard attributes and definitions
attribute COMPONENT_CONFORMANCE of AM437x : entity is
"STD_1149_1_2001";
attribute PIN_MAP of AM437x : entity is PHYSICAL_PIN_MAP;
constant ZDN : PIN_MAP_STRING :=
"ADC1_AIN6 : AE16 ," &
"ADC1_AIN7 : AD16 ," &
"CAP_VDDS1P8V_IOLDO: D6 ," &
"VDDS3P3V_IOLDO : F8 ," &
"VDDA_ADC1 : Y16 ," &
"VDDA_ADC0 : AB12 ," &
"VDDSHV10 : (G10, H10) ," &
"VDDSHV7 : F16 ," &
"VDDSHV8 : (G13, G14) ," &
"VDDSHV9 : (G11, H11) ," &
"VDDSHV11 : (H8, H9) ," &
"VDDS_CLKOUT : E23 ," &
"gpmc_ad0 : B5 ," &
"gpmc_ad1 : A5 ," &
"gpmc_ad2 : B6 ," &
"gpmc_ad3 : A6 ," &
"gpmc_ad4 : B7 ," &
"gpmc_ad5 : A7 ," &
"gpmc_ad6 : C8 ," &
"gpmc_ad7 : B8 ," &
"gpmc_ad8 : B10 ," &
"gpmc_ad9 : A10 ," &
"gpmc_ad10 : F11 ," &
"gpmc_ad11 : D11 ," &
"gpmc_ad12 : E11 ," &
"gpmc_ad13 : C11 ," &
"gpmc_ad14 : B11 ," &
"gpmc_ad15 : A11 ," &
"gpmc_a0 : C3 ," &
"gpmc_a1 : C5 ," &
"gpmc_a2 : C6 ," &
"gpmc_a3 : A4 ," &
"gpmc_a4 : D7 ," &
"gpmc_a5 : E7 ," &
"gpmc_a6 : E8 ," &
"gpmc_a7 : F6 ," &
"gpmc_a8 : F7 ," &
"gpmc_a9 : B4 ," &
"gpmc_a10 : G8 ," &
"gpmc_a11 : D8 ," &
"gpmc_wait0 : A2 ," &
"gpmc_wpn : B3 ," &
"gpmc_be1n : A3 ," &
"gpmc_csn0 : A8 ," &
"gpmc_csn1 : B9 ," &
"gpmc_csn2 : F10 ," &
"gpmc_csn3 : B12 ," &
"gpmc_clk : A12 ," &
"gpmc_advn_ale : A9 ," &
"gpmc_oen_ren : E10 ," &
"gpmc_wen : D10 ," &
"gpmc_be0n_cle : C10 ," &
"dss_data0 : B22 ," &
"dss_data1 : A21 ," &
"dss_data2 : B21 ," &
"dss_data3 : C21 ," &
"dss_data4 : A20 ," &
"dss_data5 : B20 ," &
"dss_data6 : C20 ," &
"dss_data7 : E19 ," &
"dss_data8 : A19 ," &
"dss_data9 : B19 ," &
"dss_data10 : A18 ," &
"dss_data11 : B18 ," &
"dss_data12 : C19 ," &
"dss_data13 : D19 ," &
"dss_data14 : C17 ," &
"dss_data15 : D17 ," &
"dss_vsync : B23 ," &
"dss_hsync : A23 ," &
"dss_pclk : A22 ," &
"dss_ac_bias_en : A24 ," &
"mmc0_dat3 : B1 ," &
"mmc0_dat2 : B2 ," &
"mmc0_dat1 : C2 ," &
"mmc0_dat0 : C1 ," &
"mmc0_clk : D1 ," &
"mmc0_cmd : D2 ," &
"mii1_col : D16 ," &
"mii1_crs : B14 ," &
"mii1_rx_er : B13 ," &
"mii1_tx_en : A13 ," &
"mii1_rx_dv : A15 ," &
"mii1_txd3 : C16 ," &
"mii1_txd2 : C13 ," &
"mii1_txd1 : A14 ," &
"mii1_txd0 : B15 ," &
"mii1_tx_clk : D14 ," &
"mii1_rx_clk : D13 ," &
"mii1_rxd3 : C14 ," &
"mii1_rxd2 : E16 ," &
"mii1_rxd1 : B16 ," &
"mii1_rxd0 : F17 ," &
"rmii1_ref_clk : A16 ," &
"mdio_data : A17 ," &
"mdio_clk : B17 ," &
"spi0_sclk : P23 ," &
"spi0_d0 : T22 ," &
"spi0_d1 : T21 ," &
"spi0_cs0 : T20 ," &
"spi0_cs1 : R25 ," &
"eCAP0_in_PWM0_out : G24 ," &
"uart0_ctsn : L25 ," &
"uart0_rtsn : J25 ," &
"uart0_rxd : K25 ," &
"uart0_txd : J24 ," &
"uart1_ctsn : K22 ," &
"uart1_rtsn : L22 ," &
"uart1_rxd : K21 ," &
"uart1_txd : L21 ," &
"I2C0_SDA : AB24 ," &
"I2C0_SCL : Y22 ," &
"mcasp0_aclkx : N24 ," &
"mcasp0_fsx : N22 ," &
"mcasp0_axr0 : H23 ," &
"mcasp0_ahclkr : M24 ," &
"mcasp0_aclkr : L23 ," &
"mcasp0_fsr : K23 ," &
"mcasp0_axr1 : M25 ," &
"mcasp0_ahclkx : L24 ," &
"cam0_hd : AE17 ," &
"cam0_vd : AD18 ," &
"cam0_field : AC18 ," &
"cam0_wen : AD17 ," &
"cam0_pclk : AC20 ," &
"cam0_data8 : AB19 ," &
"cam0_data9 : AA19 ," &
"cam1_data9 : AC24 ," &
"cam1_data8 : AD24 ," &
"cam1_hd : AD25 ," &
"cam1_vd : AC23 ," &
"cam1_pclk : AE21 ," &
"cam1_field : AC25 ," &
"cam1_wen : AB25 ," &
"cam1_data0 : AB20 ," &
"cam1_data1 : AC21 ," &
"cam1_data2 : AD21 ," &
"cam1_data3 : AE22 ," &
"cam1_data4 : AD22 ," &
"cam1_data5 : AE23 ," &
"cam1_data6 : AD23 ," &
"cam1_data7 : AE24 ," &
"cam0_data0 : AE18 ," &
"cam0_data1 : AB18 ," &
"cam0_data2 : Y18 ," &
"cam0_data3 : AA18 ," &
"cam0_data4 : AE19 ," &
"cam0_data5 : AD19 ," &
"cam0_data6 : AE20 ," &
"cam0_data7 : AD20 ," &
"uart3_rxd : H25 ," &
"uart3_txd : H24 ," &
"uart3_ctsn : H22 ," &
"uart3_rtsn : K24 ," &
"gpio5_8 : D25 ," &
"gpio5_9 : F24 ," &
"gpio5_10 : G20 ," &
"gpio5_11 : F23 ," &
"gpio5_12 : E25 ," &
"gpio5_13 : E24 ," &
"spi4_sclk : P25 ," &
"spi4_d0 : R24 ," &
"spi4_d1 : P24 ," &
"spi4_cs0 : N25 ," &
"spi2_sclk : N20 ," &
"spi2_d0 : P22 ," &
"spi2_d1 : P20 ," &
"spi2_cs0 : T23 ," &
"reserved : (AA10, AA7, AA9, AB10, AB6, AB7, AB9, AC10, AC12, AC5, AC6, AC7, AC9, AD1, AD10, AD11, AD2, AD7, AE11, AE12, AE9, H19, H21, P21, W10, Y10, Y6, Y7) ," &
"reserved1 : AE10 ," &
-- --
-- reserved1 named VSS in data manual to ensure it is always low --
-- --
"xdma_event_intr0 : D24 ," &
"xdma_event_intr1 : C24 ," &
"clkreq : H20 ," &
"WARMRSTn : G22 ," &
"PWRONRSTn : Y23 ," &
"EXTINTn : G25 ," &
"XTALIN : C25 ," &
"XTALOUT : B25 ," &
"TMS : Y24 ," &
"TDI : Y20 ," &
"TDO : AA24 ," &
"TCK : AA25 ," &
"nTRST : Y25 ," &
"EMU0 : N23 ," &
"EMU1 : T24 ," &
"RTC_XTALIN : AE5 ," &
"RTC_XTALOUT : AE4 ," &
"RTC_PWRONRSTn : AE6 ," &
"RTC_WAKEUP : AE3 ," &
"RTC_PMIC_EN : AD6 ," &
"RTC_KALDO_ENn : AE2 ," &
"USB0_DM : W24 ," &
"USB0_DP : W25 ," &
"USB0_CE : W22 ," &
"USB0_ID : U24 ," &
"USB0_VBUS : U23 ," &
"USB0_DRVVBUS : G21 ," &
"USB1_DM : V25 ," &
"USB1_DP : V24 ," &
"USB1_CE : U22 ," &
"USB1_ID : U25 ," &
"USB1_VBUS : T25 ," &
"USB1_DRVVBUS : F25 ," &
"ddr_resetn : T1 ," &
"ddr_csn0 : M5 ," &
"ddr_csn1 : M4 ," &
"ddr_cke0 : M3 ," &
"ddr_cke1 : N6 ," &
"ddr_ck : M2 ," &
"ddr_nck : M1 ," &
"ddr_casn : N3 ," &
"ddr_rasn : N2 ," &
"ddr_wen : N4 ," &
"ddr_ba0 : K1 ," &
"ddr_ba1 : K2 ," &
"ddr_ba2 : K3 ," &
"ddr_a0 : N1 ," &
"ddr_a1 : L1 ," &
"ddr_a2 : L2 ," &
"ddr_a3 : P2 ," &
"ddr_a4 : P1 ," &
"ddr_a5 : R5 ," &
"ddr_a6 : R4 ," &
"ddr_a7 : R3 ," &
"ddr_a8 : R2 ," &
"ddr_a9 : R1 ," &
"ddr_a10 : M6 ," &
"ddr_a11 : T5 ," &
"ddr_a12 : T4 ," &
"ddr_a13 : N5 ," &
"ddr_a14 : T3 ," &
"ddr_a15 : T2 ," &
"ddr_odt0 : U1 ," &
"ddr_odt1 : U2 ," &
"ddr_d0 : E3 ," &
"ddr_d1 : E2 ," &
"ddr_d2 : E1 ," &
"ddr_d3 : F3 ," &
"ddr_d4 : G4 ," &
"ddr_d5 : G3 ," &
"ddr_d6 : G2 ," &
"ddr_d7 : G1 ," &
"ddr_d8 : H1 ," &
"ddr_d9 : J6 ," &
"ddr_d10 : J5 ," &
"ddr_d11 : J4 ," &
"ddr_d12 : J3 ," &
"ddr_d13 : K6 ," &
"ddr_d14 : K5 ," &
"ddr_d15 : K4 ," &
"ddr_d16 : V5 ," &
"ddr_d17 : V4 ," &
"ddr_d18 : V3 ," &
"ddr_d19 : V2 ," &
"ddr_d20 : V1 ," &
"ddr_d21 : W4 ," &
"ddr_d22 : W5 ," &
"ddr_d23 : W6 ," &
"ddr_d24 : Y2 ," &
"ddr_d25 : Y3 ," &
"ddr_d26 : Y4 ," &
"ddr_d27 : AA3 ," &
"ddr_d28 : AB2 ," &
"ddr_d29 : AB1 ," &
"ddr_d30 : AC1 ," &
"ddr_d31 : AC2 ," &
"ddr_dqm0 : F4 ," &
"ddr_dqm1 : H2 ," &
"ddr_dqm2 : V6 ," &
"ddr_dqm3 : Y1 ," &
"ddr_dqs0 : F2 ," &
"ddr_dqsn0 : F1 ," &
"ddr_dqs1 : J2 ," &
"ddr_dqsn1 : J1 ," &
"ddr_dqs2 : W1 ," &
"ddr_dqsn2 : W2 ," &
"ddr_dqs3 : AA1 ," &
"ddr_dqsn3 : AA2 ," &
"DDR_VREF : T6 ," &
"ddr_vtp : AC3 ," &
"ADC0_AIN7 : AE13 ," &
"ADC0_AIN6 : AD13 ," &
"ADC0_AIN5 : AC13 ," &
"ADC0_AIN4 : AB13 ," &
"ADC0_AIN3 : AA13 ," &
"ADC0_AIN2 : Y13 ," &
"ADC0_AIN1 : Y12 ," &
"ADC0_AIN0 : AA12 ," &
"ADC0_VREFP : AD14 ," &
"ADC0_VREFN : AE14 ," &
"ADC1_AIN5 : Y15 ," &
"ADC1_AIN4 : AA15 ," &
"ADC1_AIN3 : AB15 ," &
"ADC1_AIN2 : AA16 ," &
"ADC1_AIN1 : AB16 ," &
"ADC1_AIN0 : AC16 ," &
"ADC1_VREFP : AE15 ," &
"ADC1_VREFN : AD15 ," &
"CAP_VBB_MPU : F19 ," &
"CAP_VDD_RTC : AD3 ," &
"CAP_VDD_SRAM_CORE : E13 ," &
"CAP_VDD_SRAM_MPU : E14 ," &
"VDD_CORE : (J10, J11, L12, L14, M12, M14, M9, N16, N17, N9, P16, P17, R11, R14, R9, T11, T14, T18, T19, T9, U15, V15, W12, W13, AD9) ," &
"VDD_MPU : (H13, H14, H16, J13, J14, J16, K19, K20, L19, L20, M17, M18) ," &
"vdd_mpu_mon : D20 ," &
"VDDA1P8V_USB0 : W21 ," &
"VDDA1P8V_USB1 : U21 ," &
"VDDA3P3V_USB0 : W20 ," &
"VDDA3P3V_USB1 : U20 ," &
"VDDS : (F20, G6, H12, P19, W15, Y19, AD12, AD8) ," &
"VDDS_DDR : (K7, K8, M7, M8, N7, N8, R6, R7, R8, T7, T8, V7, V8) ," &
"VDDS_OSC : C23 ," &
"VDDS_PLL_CORE_LCD : N21 ," &
"VDDS_PLL_DDR : G5 ," &
"VDDS_PLL_MPU : E17 ," &
"VDDS_RTC : AD5 ," &
"VDDS_SRAM_CORE_BG : F13 ," &
"VDDS_SRAM_MPU_BB : F14 ," &
"VDDSHV1 : (J7, J8) ," &
"VDDSHV2 : (V16, V17, W16) ," &
"VDDSHV3 : (J18, K17, K18, N18, N19, P18, W18) ," &
"VDDSHV5 : F22 ," &
"VDDSHV6 : (G16, G17, H17) ," &
"VSS : (A1, A25, AA23, AE1, AE25, H15, H18, J12, J15, J17, J9, K11, K12, K14, K15, K9, L11, L15, L17, L18, L8, L9, M10, M11, M13, M15, M16, N10, N11, N12, N13, N14, N15, P10, P11, P12, P13, P14, P15, P8, P9, R12, R15, R17, R18, T12, T15, T17, U10, U11, U12, U13, U14, U16, U17, U18, U19, U8, U9, V10, V11, V12, V13, V14, V18, V9, AE7, AE8) ," &
"VSS_OSC : B24 ," &
"VSS_RTC : AD4 ," &
"VSSA_ADC : AC15 ," &
"VSSA_USB : W23 ";
attribute PORT_GROUPING of AM437x : entity is
"Differential_Voltage ( (ddr_dqs0,ddr_dqsn0)," &
"(ddr_dqs1,ddr_dqsn1)," &
"(ddr_dqs2,ddr_dqsn2)," &
"(ddr_dqs3,ddr_dqsn3))";
-- *********************************************************
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of nTRST : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (20.00e6, BOTH);
attribute COMPLIANCE_PATTERNS of AM437x: entity is
"( PWRONRSTn, reserved1) (10)";
-- --
-- reserved1 named VSS in data manual to ensure it is always low --
-- --
attribute INSTRUCTION_LENGTH of AM437x: entity is 6;
attribute INSTRUCTION_OPCODE of AM437x: entity is
"EXTEST (011000), " &
"IDCODE (000100), " &
"BYPASS (111111), " &
"SAMPLE (011011), " &
"PRELOAD (011100), " &
"PRIVATE (000000, " &
" 000001, " &
" 000010, " &
" 000011, " &
" 000101, " &
" 000110, " &
" 000111, " &
" 001000, " &
" 001001, " &
" 001010, " &
" 001011, " &
" 001100, " &
" 001101, " &
" 001110, " &
" 001111, " &
" 010000, " &
" 010001, " &
" 010010, " &
" 010011, " &
" 010100, " &
" 010101, " &
" 010110, " &
" 010111, " &
" 011001, " &
" 011010, " &
" 011101, " &
" 011110, " &
" 011111, " &
" 100000, " &
" 100001, " &
" 100010, " &
" 100011, " &
" 100100, " &
" 100101, " &
" 100110, " &
" 100111, " &
" 101000, " &
" 101001, " &
" 101010, " &
" 101011, " &
" 101100, " &
" 101101, " &
" 101110, " &
" 101111, " &
" 110000, " &
" 110001, " &
" 110010, " &
" 110011, " &
" 110100, " &
" 110101, " &
" 110110, " &
" 110111, " &
" 111000, " &
" 111001, " &
" 111010, " &
" 111011, " &
" 111100, " &
" 111101, " &
" 111110) " ;
attribute INSTRUCTION_CAPTURE of AM437x: entity is "XXXX01";
attribute INSTRUCTION_PRIVATE of AM437x: entity is "PRIVATE";
------------------------------------------------------------
-- Version number must be modified to match the version --
-- of the AM437x used. Bits 31-28 of the CTRL_DEVICE_ID --
-- register should be substituted for the version number --
-- in IDCODE_REGISTER attribute below. --
------------------------------------------------------------
attribute IDCODE_REGISTER of AM437x: entity is
-- "0000" & -- Version number 1.0
-- "0001" & -- Version number 1.1
"0010" & -- Version number 1.2
"1011100110001100" & -- Part number -- pin package ID
"00000010111" & -- Manufacturer ID -- Texas Instruments
"1"; -- Required by IEEE Std.
attribute REGISTER_ACCESS of AM437x: entity is
"BOUNDARY (EXTEST, SAMPLE, PRELOAD)," &
"BYPASS (BYPASS) " ;
attribute BOUNDARY_LENGTH of AM437x: entity is 737;
attribute BOUNDARY_REGISTER of AM437x: entity is
"0 ( bc_1, gpmc_a11, output3, X, 1, 1, pull0)," &
"1 ( bc_1, *, control, 1 )," &
"2 ( bc_1, gpmc_a11, input, X )," &
"3 ( bc_1, gpmc_wait0, output3, X, 4, 1, pull1)," &
"4 ( bc_1, *, control, 1 )," &
"5 ( bc_1, gpmc_wait0, input, X )," &
"6 ( bc_1, gpmc_wpn, output3, X, 7, 1, pull1)," &
"7 ( bc_1, *, control, 1 )," &
"8 ( bc_1, gpmc_wpn, input, X )," &
"9 ( bc_1, gpmc_be1n, output3, X, 10, 1, pull1)," &
"10 ( bc_1, *, control, 1 )," &
"11 ( bc_1, gpmc_be1n, input, X )," &
"12 ( bc_1, gpmc_ad0, output3, X, 13, 1, pull0)," &
"13 ( bc_1, *, control, 1 )," &
"14 ( bc_1, gpmc_ad0, input, X )," &
"15 ( bc_1, gpmc_ad1, output3, X, 16, 1, pull0)," &
"16 ( bc_1, *, control, 1 )," &
"17 ( bc_1, gpmc_ad1, input, X )," &
"18 ( bc_1, gpmc_ad2, output3, X, 19, 1, pull0)," &
"19 ( bc_1, *, control, 1 )," &
"20 ( bc_1, gpmc_ad2, input, X )," &
"21 ( bc_1, gpmc_ad3, output3, X, 22, 1, pull0)," &
"22 ( bc_1, *, control, 1 )," &
"23 ( bc_1, gpmc_ad3, input, X )," &
"24 ( bc_1, gpmc_ad4, output3, X, 25, 1, pull0)," &
"25 ( bc_1, *, control, 1 )," &
"26 ( bc_1, gpmc_ad4, input, X )," &
"27 ( bc_1, gpmc_ad5, output3, X, 28, 1, pull0)," &
"28 ( bc_1, *, control, 1 )," &
"29 ( bc_1, gpmc_ad5, input, X )," &
"30 ( bc_1, gpmc_ad6, output3, X, 31, 1, pull0)," &
"31 ( bc_1, *, control, 1 )," &
"32 ( bc_1, gpmc_ad6, input, X )," &
"33 ( bc_1, gpmc_ad7, output3, X, 34, 1, pull0)," &
"34 ( bc_1, *, control, 1 )," &
"35 ( bc_1, gpmc_ad7, input, X )," &
"36 ( bc_1, gpmc_csn0, output3, X, 37, 1, pull1)," &
"37 ( bc_1, *, control, 1 )," &
"38 ( bc_1, gpmc_csn0, input, X )," &
"39 ( bc_1, gpmc_csn1, output3, X, 40, 1, pull1)," &
"40 ( bc_1, *, control, 1 )," &
"41 ( bc_1, gpmc_csn1, input, X )," &
"42 ( bc_1, gpmc_csn2, output3, X, 43, 1, pull1)," &
"43 ( bc_1, *, control, 1 )," &
"44 ( bc_1, gpmc_csn2, input, X )," &
"45 ( bc_1, gpmc_advn_ale, output3, X, 46, 1, pull1)," &
"46 ( bc_1, *, control, 1 )," &
"47 ( bc_1, gpmc_advn_ale, input, X )," &
"48 ( bc_1, gpmc_oen_ren, output3, X, 49, 1, pull1)," &
"49 ( bc_1, *, control, 1 )," &
"50 ( bc_1, gpmc_oen_ren, input, X )," &
"51 ( bc_1, gpmc_wen, output3, X, 52, 1, pull1)," &
"52 ( bc_1, *, control, 1 )," &
"53 ( bc_1, gpmc_wen, input, X )," &
"54 ( bc_1, gpmc_be0n_cle, output3, X, 55, 1, pull1)," &
"55 ( bc_1, *, control, 1 )," &
"56 ( bc_1, gpmc_be0n_cle, input, X )," &
"57 ( bc_1, gpmc_ad8, output3, X, 58, 1, pull0)," &
"58 ( bc_1, *, control, 1 )," &
"59 ( bc_1, gpmc_ad8, input, X )," &
"60 ( bc_1, gpmc_ad9, output3, X, 61, 1, pull0)," &
"61 ( bc_1, *, control, 1 )," &
"62 ( bc_1, gpmc_ad9, input, X )," &
"63 ( bc_1, gpmc_ad10, output3, X, 64, 1, pull0)," &
"64 ( bc_1, *, control, 1 )," &
"65 ( bc_1, gpmc_ad10, input, X )," &
"66 ( bc_1, gpmc_ad11, output3, X, 67, 1, pull0)," &
"67 ( bc_1, *, control, 1 )," &
"68 ( bc_1, gpmc_ad11, input, X )," &
"69 ( bc_1, gpmc_ad12, output3, X, 70, 1, pull0)," &
"70 ( bc_1, *, control, 1 )," &
"71 ( bc_1, gpmc_ad12, input, X )," &
"72 ( bc_1, gpmc_ad13, output3, X, 73, 1, pull0)," &
"73 ( bc_1, *, control, 1 )," &
"74 ( bc_1, gpmc_ad13, input, X )," &
"75 ( bc_1, gpmc_ad14, output3, X, 76, 1, pull0)," &
"76 ( bc_1, *, control, 1 )," &
"77 ( bc_1, gpmc_ad14, input, X )," &
"78 ( bc_1, gpmc_ad15, output3, X, 79, 1, pull0)," &
"79 ( bc_1, *, control, 1 )," &
"80 ( bc_1, gpmc_ad15, input, X )," &
"81 ( bc_1, gpmc_csn3, output3, X, 82, 1, pull1)," &
"82 ( bc_1, *, control, 1 )," &
"83 ( bc_1, gpmc_csn3, input, X )," &
"84 ( bc_1, gpmc_clk, output3, X, 85, 1, pull0)," &
"85 ( bc_1, *, control, 1 )," &
"86 ( bc_1, gpmc_clk, input, X )," &
"87 ( bc_1, mii1_col, output3, X, 88, 1, pull0)," &
"88 ( bc_1, *, control, 1 )," &
"89 ( bc_1, mii1_col, input, X )," &
"90 ( bc_1, mii1_crs, output3, X, 91, 1, pull0)," &
"91 ( bc_1, *, control, 1 )," &
"92 ( bc_1, mii1_crs, input, X )," &
"93 ( bc_1, mii1_rx_er, output3, X, 94, 1, pull0)," &
"94 ( bc_1, *, control, 1 )," &
"95 ( bc_1, mii1_rx_er, input, X )," &
"96 ( bc_1, mii1_tx_en, output3, X, 97, 1, pull0)," &
"97 ( bc_1, *, control, 1 )," &
"98 ( bc_1, mii1_tx_en, input, X )," &
"99 ( bc_1, mii1_rx_dv, output3, X, 100, 1, pull0)," &
"100 ( bc_1, *, control, 1 )," &
"101 ( bc_1, mii1_rx_dv, input, X )," &
"102 ( bc_1, mii1_txd3, output3, X, 103, 1, pull0)," &
"103 ( bc_1, *, control, 1 )," &
"104 ( bc_1, mii1_txd3, input, X )," &
"105 ( bc_1, mii1_txd2, output3, X, 106, 1, pull0)," &
"106 ( bc_1, *, control, 1 )," &
"107 ( bc_1, mii1_txd2, input, X )," &
"108 ( bc_1, mii1_txd1, output3, X, 109, 1, pull0)," &
"109 ( bc_1, *, control, 1 )," &
"110 ( bc_1, mii1_txd1, input, X )," &
"111 ( bc_1, mii1_txd0, output3, X, 112, 1, pull0)," &
"112 ( bc_1, *, control, 1 )," &
"113 ( bc_1, mii1_txd0, input, X )," &
"114 ( bc_1, mii1_tx_clk, output3, X, 115, 1, pull0)," &
"115 ( bc_1, *, control, 1 )," &
"116 ( bc_1, mii1_tx_clk, input, X )," &
"117 ( bc_1, mii1_rx_clk, output3, X, 118, 1, pull0)," &
"118 ( bc_1, *, control, 1 )," &
"119 ( bc_1, mii1_rx_clk, input, X )," &
"120 ( bc_1, mii1_rxd3, output3, X, 121, 1, pull0)," &
"121 ( bc_1, *, control, 1 )," &
"122 ( bc_1, mii1_rxd3, input, X )," &
"123 ( bc_1, mii1_rxd2, output3, X, 124, 1, pull0)," &
"124 ( bc_1, *, control, 1 )," &
"125 ( bc_1, mii1_rxd2, input, X )," &
"126 ( bc_1, mii1_rxd1, output3, X, 127, 1, pull0)," &
"127 ( bc_1, *, control, 1 )," &
"128 ( bc_1, mii1_rxd1, input, X )," &
"129 ( bc_1, mii1_rxd0, output3, X, 130, 1, pull0)," &
"130 ( bc_1, *, control, 1 )," &
"131 ( bc_1, mii1_rxd0, input, X )," &
"132 ( bc_1, rmii1_ref_clk, output3, X, 133, 1, pull0)," &
"133 ( bc_1, *, control, 1 )," &
"134 ( bc_1, rmii1_ref_clk, input, X )," &
"135 ( bc_1, mdio_clk, output3, X, 136, 1, pull1)," &
"136 ( bc_1, *, control, 1 )," &
"137 ( bc_1, mdio_clk, input, X )," &
"138 ( bc_1, mdio_data, output3, X, 139, 1, pull1)," &
"139 ( bc_1, *, control, 1 )," &
"140 ( bc_1, mdio_data, input, X )," &
"141 ( bc_1, dss_data15, output3, X, 142, 1, Z)," &
"142 ( bc_1, *, control, 1 )," &
"143 ( bc_1, dss_data15, input, X )," &
"144 ( bc_1, dss_data14, output3, X, 145, 1, Z)," &
"145 ( bc_1, *, control, 1 )," &
"146 ( bc_1, dss_data14, input, X )," &
"147 ( bc_1, dss_data13, output3, X, 148, 1, Z)," &
"148 ( bc_1, *, control, 1 )," &
"149 ( bc_1, dss_data13, input, X )," &
"150 ( bc_1, dss_data12, output3, X, 151, 1, Z)," &
"151 ( bc_1, *, control, 1 )," &
"152 ( bc_1, dss_data12, input, X )," &
"153 ( bc_1, dss_data11, output3, X, 154, 1, Z)," &
"154 ( bc_1, *, control, 1 )," &
"155 ( bc_1, dss_data11, input, X )," &
"156 ( bc_1, dss_data10, output3, X, 157, 1, Z)," &
"157 ( bc_1, *, control, 1 )," &
"158 ( bc_1, dss_data10, input, X )," &
"159 ( bc_1, dss_data9, output3, X, 160, 1, Z)," &
"160 ( bc_1, *, control, 1 )," &
"161 ( bc_1, dss_data9, input, X )," &
"162 ( bc_1, dss_data8, output3, X, 163, 1, Z)," &
"163 ( bc_1, *, control, 1 )," &
"164 ( bc_1, dss_data8, input, X )," &
"165 ( bc_1, dss_data7, output3, X, 166, 1, Z)," &
"166 ( bc_1, *, control, 1 )," &
"167 ( bc_1, dss_data7, input, X )," &
"168 ( bc_1, dss_data6, output3, X, 169, 1, Z)," &
"169 ( bc_1, *, control, 1 )," &
"170 ( bc_1, dss_data6, input, X )," &
"171 ( bc_1, dss_data5, output3, X, 172, 1, Z)," &
"172 ( bc_1, *, control, 1 )," &
"173 ( bc_1, dss_data5, input, X )," &
"174 ( bc_1, dss_data4, output3, X, 175, 1, Z)," &
"175 ( bc_1, *, control, 1 )," &
"176 ( bc_1, dss_data4, input, X )," &
"177 ( bc_1, dss_data3, output3, X, 178, 1, Z)," &
"178 ( bc_1, *, control, 1 )," &
"179 ( bc_1, dss_data3, input, X )," &
"180 ( bc_1, dss_data2, output3, X, 181, 1, Z)," &
"181 ( bc_1, *, control, 1 )," &
"182 ( bc_1, dss_data2, input, X )," &
"183 ( bc_1, dss_data1, output3, X, 184, 1, Z)," &
"184 ( bc_1, *, control, 1 )," &
"185 ( bc_1, dss_data1, input, X )," &
"186 ( bc_1, dss_data0, output3, X, 187, 1, Z)," &
"187 ( bc_1, *, control, 1 )," &
"188 ( bc_1, dss_data0, input, X )," &
"189 ( bc_1, dss_pclk, output3, X, 190, 1, pull0)," &
"190 ( bc_1, *, control, 1 )," &
"191 ( bc_1, dss_pclk, input, X )," &
"192 ( bc_1, dss_vsync, output3, X, 193, 1, Z)," &
"193 ( bc_1, *, control, 1 )," &
"194 ( bc_1, dss_vsync, input, X )," &
"195 ( bc_1, dss_hsync, output3, X, 196, 1, Z)," &
"196 ( bc_1, *, control, 1 )," &
"197 ( bc_1, dss_hsync, input, X )," &
"198 ( bc_1, dss_ac_bias_en, output3, X, 199, 1, Z)," &
"199 ( bc_1, *, control, 1 )," &
"200 ( bc_1, dss_ac_bias_en, input, X )," &
"201 ( bc_1, xdma_event_intr1, output3, X, 202, 1, pull0)," &
"202 ( bc_1, *, control, 1 )," &
"203 ( bc_1, xdma_event_intr1, input, X )," &
"204 ( bc_1, xdma_event_intr0, output3, X, 205, 1, pull0)," &
"205 ( bc_1, *, control, 1 )," &
"206 ( bc_1, xdma_event_intr0, input, X )," &
"207 ( bc_1, USB1_DRVVBUS, output3, X, 208, 1, pull0)," &
"208 ( bc_1, *, control, 1 )," &
"209 ( bc_1, USB1_DRVVBUS, input, X )," &
"210 ( bc_1, USB0_DRVVBUS, output3, X, 211, 1, pull0)," &
"211 ( bc_1, *, control, 1 )," &
"212 ( bc_1, USB0_DRVVBUS, input, X )," &
"213 ( bc_1, WARMRSTn, output2, 1, 213, 1, WEAK1)," &
"214 ( bc_1, *, internal, X )," &
"215 ( bc_1, WARMRSTn, input, X )," &
"216 ( bc_1, eCAP0_in_PWM0_out, output3, X, 217, 1, pull0)," &
"217 ( bc_1, *, control, 1 )," &
"218 ( bc_1, eCAP0_in_PWM0_out, input, X )," &
"219 ( bc_1, EXTINTn, input, X )," &
"220 ( bc_1, clkreq, output3, X, 221, 1, pull1)," &
"221 ( bc_1, *, control, 1 )," &
"222 ( bc_1, clkreq, input, X )," &
"223 ( bc_1, uart3_ctsn, output3, X, 224, 1, pull1)," &
"224 ( bc_1, *, control, 1 )," &
"225 ( bc_1, uart3_ctsn, input, X )," &
"226 ( bc_1, spi2_cs0, output3, X, 227, 1, pull1)," &
"227 ( bc_1, *, control, 1 )," &
"228 ( bc_1, spi2_cs0, input, X )," &
"229 ( bc_1, spi2_d1, output3, X, 230, 1, pull1)," &
"230 ( bc_1, *, control, 1 )," &
"231 ( bc_1, spi2_d1, input, X )," &
"232 ( bc_1, spi2_d0, output3, X, 233, 1, pull0)," &
"233 ( bc_1, *, control, 1 )," &
"234 ( bc_1, spi2_d0, input, X )," &
"235 ( bc_1, spi2_sclk, output3, X, 236, 1, pull0)," &
"236 ( bc_1, *, control, 1 )," &
"237 ( bc_1, spi2_sclk, input, X )," &
"238 ( bc_1, spi4_cs0, output3, X, 239, 1, pull1)," &
"239 ( bc_1, *, control, 1 )," &
"240 ( bc_1, spi4_cs0, input, X )," &
"241 ( bc_1, spi4_d1, output3, X, 242, 1, pull0)," &
"242 ( bc_1, *, control, 1 )," &
"243 ( bc_1, spi4_d1, input, X )," &
"244 ( bc_1, spi4_d0, output3, X, 245, 1, pull0)," &
"245 ( bc_1, *, control, 1 )," &
"246 ( bc_1, spi4_d0, input, X )," &
"247 ( bc_1, spi4_sclk, output3, X, 248, 1, pull0)," &
"248 ( bc_1, *, control, 1 )," &
"249 ( bc_1, spi4_sclk, input, X )," &
"250 ( bc_1, gpio5_13, output3, X, 251, 1, pull0)," &
"251 ( bc_1, *, control, 1 )," &
"252 ( bc_1, gpio5_13, input, X )," &
"253 ( bc_1, gpio5_12, output3, X, 254, 1, pull0)," &
"254 ( bc_1, *, control, 1 )," &
"255 ( bc_1, gpio5_12, input, X )," &
"256 ( bc_1, gpio5_11, output3, X, 257, 1, pull0)," &
"257 ( bc_1, *, control, 1 )," &
"258 ( bc_1, gpio5_11, input, X )," &
"259 ( bc_1, gpio5_10, output3, X, 260, 1, pull0)," &
"260 ( bc_1, *, control, 1 )," &
"261 ( bc_1, gpio5_10, input, X )," &
"262 ( bc_1, gpio5_9, output3, X, 263, 1, pull0)," &
"263 ( bc_1, *, control, 1 )," &
"264 ( bc_1, gpio5_9, input, X )," &
"265 ( bc_1, gpio5_8, output3, X, 266, 1, pull0)," &
"266 ( bc_1, *, control, 1 )," &
"267 ( bc_1, gpio5_8, input, X )," &
"268 ( bc_1, uart3_rtsn, output3, X, 269, 1, pull1)," &
"269 ( bc_1, *, control, 1 )," &
"270 ( bc_1, uart3_rtsn, input, X )," &
"271 ( bc_1, uart3_txd, output3, X, 272, 1, pull1)," &
"272 ( bc_1, *, control, 1 )," &
"273 ( bc_1, uart3_txd, input, X )," &
"274 ( bc_1, uart3_rxd, output3, X, 275, 1, pull1)," &
"275 ( bc_1, *, control, 1 )," &
"276 ( bc_1, uart3_rxd, input, X )," &
"277 ( bc_1, uart1_txd, output3, X, 278, 1, pull1)," &
"278 ( bc_1, *, control, 1 )," &
"279 ( bc_1, uart1_txd, input, X )," &
"280 ( bc_1, uart1_rxd, output3, X, 281, 1, pull1)," &
"281 ( bc_1, *, control, 1 )," &
"282 ( bc_1, uart1_rxd, input, X )," &
"283 ( bc_1, uart1_rtsn, output3, X, 284, 1, pull1)," &
"284 ( bc_1, *, control, 1 )," &
"285 ( bc_1, uart1_rtsn, input, X )," &
"286 ( bc_1, uart1_ctsn, output3, X, 287, 1, pull1)," &
"287 ( bc_1, *, control, 1 )," &
"288 ( bc_1, uart1_ctsn, input, X )," &
"289 ( bc_1, uart0_txd, output3, X, 290, 1, pull1)," &
"290 ( bc_1, *, control, 1 )," &
"291 ( bc_1, uart0_txd, input, X )," &
"292 ( bc_1, uart0_rxd, output3, X, 293, 1, pull1)," &
"293 ( bc_1, *, control, 1 )," &
"294 ( bc_1, uart0_rxd, input, X )," &
"295 ( bc_1, uart0_rtsn, output3, X, 296, 1, pull1)," &
"296 ( bc_1, *, control, 1 )," &
"297 ( bc_1, uart0_rtsn, input, X )," &
"298 ( bc_1, uart0_ctsn, output3, X, 299, 1, pull1)," &
"299 ( bc_1, *, control, 1 )," &
"300 ( bc_1, uart0_ctsn, input, X )," &
"301 ( bc_1, mcasp0_axr0, output3, X, 302, 1, pull0)," &
"302 ( bc_1, *, control, 1 )," &
"303 ( bc_1, mcasp0_axr0, input, X )," &
"304 ( bc_1, mcasp0_ahclkr, output3, X, 305, 1, pull0)," &
"305 ( bc_1, *, control, 1 )," &
"306 ( bc_1, mcasp0_ahclkr, input, X )," &
"307 ( bc_1, mcasp0_aclkr, output3, X, 308, 1, pull0)," &
"308 ( bc_1, *, control, 1 )," &
"309 ( bc_1, mcasp0_aclkr, input, X )," &
"310 ( bc_1, mcasp0_fsr, output3, X, 311, 1, pull0)," &
"311 ( bc_1, *, control, 1 )," &
"312 ( bc_1, mcasp0_fsr, input, X )," &
"313 ( bc_1, mcasp0_axr1, output3, X, 314, 1, pull0)," &
"314 ( bc_1, *, control, 1 )," &
"315 ( bc_1, mcasp0_axr1, input, X )," &
"316 ( bc_1, mcasp0_ahclkx, output3, X, 317, 1, pull0)," &
"317 ( bc_1, *, control, 1 )," &
"318 ( bc_1, mcasp0_ahclkx, input, X )," &
"319 ( bc_1, mcasp0_aclkx, output3, X, 320, 1, pull0)," &
"320 ( bc_1, *, control, 1 )," &
"321 ( bc_1, mcasp0_aclkx, input, X )," &
"322 ( bc_1, mcasp0_fsx, output3, X, 323, 1, pull0)," &
"323 ( bc_1, *, control, 1 )," &
"324 ( bc_1, mcasp0_fsx, input, X )," &
"325 ( bc_1, EMU0, output3, X, 326, 1, pull1)," &
"326 ( bc_1, *, control, 1 )," &
"327 ( bc_1, EMU0, input, X )," &
"328 ( bc_1, EMU1, output3, X, 329, 1, pull1)," &
"329 ( bc_1, *, control, 1 )," &
"330 ( bc_1, EMU1, input, X )," &
"331 ( bc_1, spi0_sclk, output3, X, 332, 1, pull1)," &
"332 ( bc_1, *, control, 1 )," &
"333 ( bc_1, spi0_sclk, input, X )," &
"334 ( bc_1, spi0_d0, output3, X, 335, 1, pull1)," &
"335 ( bc_1, *, control, 1 )," &
"336 ( bc_1, spi0_d0, input, X )," &
"337 ( bc_1, spi0_d1, output3, X, 338, 1, pull1)," &
"338 ( bc_1, *, control, 1 )," &
"339 ( bc_1, spi0_d1, input, X )," &
"340 ( bc_1, spi0_cs0, output3, X, 341, 1, pull1)," &
"341 ( bc_1, *, control, 1 )," &
"342 ( bc_1, spi0_cs0, input, X )," &
"343 ( bc_1, spi0_cs1, output3, X, 344, 1, pull1)," &
"344 ( bc_1, *, control, 1 )," &
"345 ( bc_1, spi0_cs1, input, X )," &
"346 ( bc_1, *, internal, X )," &
"347 ( bc_1, *, internal, X )," &
"348 ( bc_1, *, internal, X )," &
"349 ( bc_1, *, internal, 1 )," & -- porz
"350 ( bc_1, I2C0_SDA, output3, X, 351, 1, pull1)," &
"351 ( bc_1, *, control, 1 )," &
"352 ( bc_1, I2C0_SDA, input, X )," &
"353 ( bc_1, I2C0_SCL, output3, X, 354, 1, pull1)," &
"354 ( bc_1, *, control, 1 )," &
"355 ( bc_1, I2C0_SCL, input, X )," &
"356 ( bc_1, cam1_wen, output3, X, 357, 1, pull0)," &
"357 ( bc_1, *, control, 1 )," &
"358 ( bc_1, cam1_wen, input, X )," &
"359 ( bc_1, cam1_field, output3, X, 360, 1, pull0)," &
"360 ( bc_1, *, control, 1 )," &
"361 ( bc_1, cam1_field, input, X )," &
"362 ( bc_1, cam1_hd, output3, X, 363, 1, pull0)," &
"363 ( bc_1, *, control, 1 )," &
"364 ( bc_1, cam1_hd, input, X )," &
"365 ( bc_1, cam1_vd, output3, X, 366, 1, pull0)," &
"366 ( bc_1, *, control, 1 )," &
"367 ( bc_1, cam1_vd, input, X )," &
"368 ( bc_1, cam1_data9, output3, X, 369, 1, pull0)," &
"369 ( bc_1, *, control, 1 )," &
"370 ( bc_1, cam1_data9, input, X )," &
"371 ( bc_1, cam1_data8, output3, X, 372, 1, pull0)," &
"372 ( bc_1, *, control, 1 )," &
"373 ( bc_1, cam1_data8, input, X )," &
"374 ( bc_1, cam1_data7, output3, X, 375, 1, pull0)," &
"375 ( bc_1, *, control, 1 )," &
"376 ( bc_1, cam1_data7, input, X )," &
"377 ( bc_1, cam1_data6, output3, X, 378, 1, pull0)," &
"378 ( bc_1, *, control, 1 )," &
"379 ( bc_1, cam1_data6, input, X )," &
"380 ( bc_1, cam1_data5, output3, X, 381, 1, pull1)," &
"381 ( bc_1, *, control, 1 )," &
"382 ( bc_1, cam1_data5, input, X )," &
"383 ( bc_1, cam1_data4, output3, X, 384, 1, pull0)," &
"384 ( bc_1, *, control, 1 )," &
"385 ( bc_1, cam1_data4, input, X )," &
"386 ( bc_1, cam1_data3, output3, X, 387, 1, pull0)," &
"387 ( bc_1, *, control, 1 )," &
"388 ( bc_1, cam1_data3, input, X )," &
"389 ( bc_1, cam1_data2, output3, X, 390, 1, pull0)," &
"390 ( bc_1, *, control, 1 )," &
"391 ( bc_1, cam1_data2, input, X )," &
"392 ( bc_1, cam1_data1, output3, X, 393, 1, pull1)," &
"393 ( bc_1, *, control, 1 )," &
"394 ( bc_1, cam1_data1, input, X )," &
"395 ( bc_1, cam1_data0, output3, X, 396, 1, pull0)," &
"396 ( bc_1, *, control, 1 )," &
"397 ( bc_1, cam1_data0, input, X )," &
"398 ( bc_1, cam1_pclk, output3, X, 399, 1, pull0)," &
"399 ( bc_1, *, control, 1 )," &
"400 ( bc_1, cam1_pclk, input, X )," &
"401 ( bc_1, cam0_pclk, output3, X, 402, 1, pull0)," &
"402 ( bc_1, *, control, 1 )," &
"403 ( bc_1, cam0_pclk, input, X )," &
"404 ( bc_1, cam0_data9, output3, X, 405, 1, pull0)," &
"405 ( bc_1, *, control, 1 )," &
"406 ( bc_1, cam0_data9, input, X )," &
"407 ( bc_1, cam0_data8, output3, X, 408, 1, pull0)," &
"408 ( bc_1, *, control, 1 )," &
"409 ( bc_1, cam0_data8, input, X )," &
"410 ( bc_1, cam0_data7, output3, X, 411, 1, pull0)," &
"411 ( bc_1, *, control, 1 )," &
"412 ( bc_1, cam0_data7, input, X )," &
"413 ( bc_1, cam0_data6, output3, X, 414, 1, pull0)," &
"414 ( bc_1, *, control, 1 )," &
"415 ( bc_1, cam0_data6, input, X )," &
"416 ( bc_1, cam0_data5, output3, X, 417, 1, pull0)," &
"417 ( bc_1, *, control, 1 )," &
"418 ( bc_1, cam0_data5, input, X )," &
"419 ( bc_1, cam0_data4, output3, X, 420, 1, pull0)," &
"420 ( bc_1, *, control, 1 )," &
"421 ( bc_1, cam0_data4, input, X )," &
"422 ( bc_1, cam0_data3, output3, X, 423, 1, pull0)," &
"423 ( bc_1, *, control, 1 )," &
"424 ( bc_1, cam0_data3, input, X )," &
"425 ( bc_1, cam0_data2, output3, X, 426, 1, pull0)," &
"426 ( bc_1, *, control, 1 )," &
"427 ( bc_1, cam0_data2, input, X )," &
"428 ( bc_1, cam0_data1, output3, X, 429, 1, pull0)," &
"429 ( bc_1, *, control, 1 )," &
"430 ( bc_1, cam0_data1, input, X )," &
"431 ( bc_1, cam0_data0, output3, X, 432, 1, pull0)," &
"432 ( bc_1, *, control, 1 )," &
"433 ( bc_1, cam0_data0, input, X )," &
"434 ( bc_1, cam0_vd, output3, X, 435, 1, pull0)," &
"435 ( bc_1, *, control, 1 )," &
"436 ( bc_1, cam0_vd, input, X )," &
"437 ( bc_1, cam0_field, output3, X, 438, 1, pull0)," &
"438 ( bc_1, *, control, 1 )," &
"439 ( bc_1, cam0_field, input, X )," &
"440 ( bc_1, cam0_wen, output3, X, 441, 1, pull0)," &
"441 ( bc_1, *, control, 1 )," &
"442 ( bc_1, cam0_wen, input, X )," &
"443 ( bc_1, cam0_hd, output3, X, 444, 1, pull0)," &
"444 ( bc_1, *, control, 1 )," &
"445 ( bc_1, cam0_hd, input, X )," &
"446 ( bc_1, *, internal, 1 )," &
"447 ( bc_1, *, internal, X )," &
"448 ( bc_1, *, internal, X )," &
"449 ( bc_1, *, internal, X )," &
"450 ( bc_1, *, internal, X )," &
"451 ( bc_1, *, internal, X )," &
"452 ( bc_1, *, internal, X )," &
"453 ( bc_1, *, internal, X )," &
"454 ( bc_1, *, internal, X )," &
"455 ( bc_1, *, internal, X )," &
"456 ( bc_1, *, internal, X )," &
"457 ( bc_1, *, internal, X )," &
"458 ( bc_1, *, internal, X )," &
"459 ( bc_1, *, internal, X )," &
"460 ( bc_1, *, internal, X )," &
"461 ( bc_1, *, internal, X )," &
"462 ( bc_1, *, internal, X )," &
"463 ( bc_1, *, internal, X )," &
"464 ( bc_1, *, internal, X )," &
"465 ( bc_1, *, internal, X )," &
"466 ( bc_1, *, internal, X )," &
"467 ( bc_1, *, internal, X )," &
"468 ( bc_1, *, internal, X )," &
"469 ( bc_1, *, internal, X )," &
"470 ( bc_1, *, internal, X )," &
"471 ( bc_1, *, internal, X )," &
"472 ( bc_1, *, internal, X )," &
"473 ( bc_1, *, internal, X )," &
"474 ( bc_1, *, internal, X )," &
"475 ( bc_1, *, internal, X )," &
"476 ( bc_1, *, internal, X )," &
"477 ( bc_1, *, internal, X )," &
"478 ( bc_1, *, internal, X )," &
"479 ( bc_1, *, internal, X )," &
"480 ( bc_1, *, internal, X )," &
"481 ( bc_1, *, internal, X )," &
"482 ( bc_1, *, internal, X )," &
"483 ( bc_1, *, internal, X )," &
"484 ( bc_1, *, internal, X )," &
"485 ( bc_1, *, internal, X )," &
"486 ( bc_1, *, internal, X )," &
"487 ( bc_1, *, internal, X )," &
"488 ( bc_1, *, internal, X )," &
"489 ( bc_1, *, internal, X )," &
"490 ( bc_1, *, internal, X )," &
"491 ( bc_1, *, internal, X )," &
"492 ( bc_1, *, internal, X )," &
"493 ( bc_1, *, internal, X )," &
"494 ( bc_1, *, internal, X )," &
"495 ( bc_1, *, internal, X )," &
"496 ( bc_1, *, internal, X )," &
"497 ( bc_1, *, internal, X )," &
"498 ( bc_1, *, internal, X )," &
"499 ( bc_1, *, internal, X )," &
"500 ( bc_1, RTC_WAKEUP, input, X )," &
"501 ( bc_1, RTC_PWRONRSTn, input, X )," &
"502 ( bc_1, ddr_d31, output3, X, 503, 1, pull0)," &
"503 ( bc_1, *, control, 1 )," &
"504 ( bc_1, ddr_d31, input, X )," &
"505 ( bc_1, ddr_d30, output3, X, 506, 1, pull0)," &
"506 ( bc_1, *, control, 1 )," &
"507 ( bc_1, ddr_d30, input, X )," &
"508 ( bc_1, ddr_d29, output3, X, 509, 1, pull0)," &
"509 ( bc_1, *, control, 1 )," &
"510 ( bc_1, ddr_d29, input, X )," &
"511 ( bc_1, ddr_d28, output3, X, 512, 1, pull0)," &
"512 ( bc_1, *, control, 1 )," &
"513 ( bc_1, ddr_d28, input, X )," &
"514 ( bc_1, ddr_dqs3, output3, X, 515, 1, pull0)," &
"515 ( bc_1, *, control, 1 )," &
"516 ( bc_1, ddr_dqs3, input, X )," &
"517 ( bc_1, ddr_d27, output3, X, 518, 1, pull0)," &
"518 ( bc_1, *, control, 1 )," &
"519 ( bc_1, ddr_d27, input, X )," &
"520 ( bc_1, ddr_d26, output3, X, 521, 1, pull0)," &
"521 ( bc_1, *, control, 1 )," &
"522 ( bc_1, ddr_d26, input, X )," &
"523 ( bc_1, ddr_d25, output3, X, 524, 1, pull0)," &
"524 ( bc_1, *, control, 1 )," &
"525 ( bc_1, ddr_d25, input, X )," &
"526 ( bc_1, ddr_d24, output3, X, 527, 1, pull0)," &
"527 ( bc_1, *, control, 1 )," &
"528 ( bc_1, ddr_d24, input, X )," &
"529 ( bc_1, ddr_dqm3, output3, X, 530, 1, pull1)," &
"530 ( bc_1, *, control, 1 )," &
"531 ( bc_1, ddr_dqm3, input, X )," &
"532 ( bc_1, ddr_d23, output3, X, 533, 1, pull0)," &
"533 ( bc_1, *, control, 1 )," &
"534 ( bc_1, ddr_d23, input, X )," &
"535 ( bc_1, ddr_d22, output3, X, 536, 1, pull0)," &
"536 ( bc_1, *, control, 1 )," &
"537 ( bc_1, ddr_d22, input, X )," &
"538 ( bc_1, ddr_d21, output3, X, 539, 1, pull0)," &
"539 ( bc_1, *, control, 1 )," &
"540 ( bc_1, ddr_d21, input, X )," &
"541 ( bc_1, ddr_d20, output3, X, 542, 1, pull0)," &
"542 ( bc_1, *, control, 1 )," &
"543 ( bc_1, ddr_d20, input, X )," &
"544 ( bc_1, ddr_dqs2, output3, X, 545, 1, pull0)," &
"545 ( bc_1, *, control, 1 )," &
"546 ( bc_1, ddr_dqs2, input, X )," &
"547 ( bc_1, ddr_d19, output3, X, 548, 1, pull0)," &
"548 ( bc_1, *, control, 1 )," &
"549 ( bc_1, ddr_d19, input, X )," &
"550 ( bc_1, ddr_d18, output3, X, 551, 1, pull0)," &
"551 ( bc_1, *, control, 1 )," &
"552 ( bc_1, ddr_d18, input, X )," &
"553 ( bc_1, ddr_d17, output3, X, 554, 1, pull0)," &
"554 ( bc_1, *, control, 1 )," &
"555 ( bc_1, ddr_d17, input, X )," &
"556 ( bc_1, ddr_d16, output3, X, 557, 1, pull0)," &
"557 ( bc_1, *, control, 1 )," &
"558 ( bc_1, ddr_d16, input, X )," &
"559 ( bc_1, ddr_dqm2, output3, X, 560, 1, pull1)," &
"560 ( bc_1, *, control, 1 )," &
"561 ( bc_1, ddr_dqm2, input, X )," &
"562 ( bc_1, ddr_csn1, output3, X, 592, 1, pull1)," &
"563 ( bc_1, ddr_csn1, input, X )," &
"564 ( bc_1, ddr_odt1, output3, X, 585, 1, pull0)," &
"565 ( bc_1, ddr_odt1, input, X )," &
"566 ( bc_1, ddr_a1, output3, X, 592, 1, pull1)," &
"567 ( bc_1, ddr_a1, input, X )," &
"568 ( bc_1, ddr_csn0, output3, X, 592, 1, pull1)," &
"569 ( bc_1, ddr_csn0, input, X )," &
"570 ( bc_1, ddr_a13, output3, X, 592, 1, pull1)," &
"571 ( bc_1, ddr_a13, input, X )," &
"572 ( bc_1, ddr_a14, output3, X, 585, 1, pull1)," &
"573 ( bc_1, ddr_a14, input, X )," &
"574 ( bc_1, ddr_odt0, output3, X, 585, 1, pull0)," &
"575 ( bc_1, ddr_odt0, input, X )," &
"576 ( bc_1, ddr_resetn, output3, X, 585, 1, pull1)," &
"577 ( bc_1, *, internal, X )," &
"578 ( bc_1, ddr_cke1, output3, X, 592, 1, pull0)," &
"579 ( bc_1, ddr_cke1, input, X )," &
"580 ( bc_1, ddr_rasn, output3, X, 592, 1, pull1)," &
"581 ( bc_1, ddr_rasn, input, X )," &
"582 ( bc_1, ddr_casn, output3, X, 592, 1, pull1)," &
"583 ( bc_1, ddr_casn, input, X )," &
"584 ( bc_1, ddr_a11, output3, X, 585, 1, pull1)," &
"585 ( bc_1, *, control, 1 )," &
"586 ( bc_1, ddr_a11, input, X )," &
"587 ( bc_1, ddr_a0, output3, X, 585, 1, pull1)," &
"588 ( bc_1, ddr_a0, input, X )," &
"589 ( bc_1, ddr_a10, output3, X, 592, 1, pull1)," &
"590 ( bc_1, ddr_a10, input, X )," &
"591 ( bc_1, ddr_ba1, output3, X, 592, 1, pull1)," &
"592 ( bc_1, *, control, 1 )," &
"593 ( bc_1, ddr_ba1, input, X )," &
"594 ( bc_1, ddr_a7, output3, X, 585, 1, pull1)," &
"595 ( bc_1, ddr_a7, input, X )," &
"596 ( bc_1, ddr_a12, output3, X, 585, 1, pull1)," &
"597 ( bc_1, ddr_a12, input, X )," &
"598 ( bc_1, ddr_a2, output3, X, 592, 1, pull1)," &
"599 ( bc_1, ddr_a2, input, X )," &
"600 ( bc_1, ddr_a15, output3, X, 585, 1, pull1)," &
"601 ( bc_1, ddr_a15, input, X )," &
"602 ( bc_1, ddr_cke0, output3, X, 592, 1, pull0)," &
"603 ( bc_1, ddr_cke0, input, X )," &
"604 ( bc_1, ddr_nck, output3, X, 592, 1, pull1)," &
"605 ( bc_1, ddr_nck, input, X )," &
"606 ( bc_1, ddr_ck, output3, X, 592, 1, pull0)," &
"607 ( bc_1, ddr_ck, input, X )," &
"608 ( bc_1, ddr_a8, output3, X, 585, 1, pull1)," &
"609 ( bc_1, ddr_a8, input, X )," &
"610 ( bc_1, ddr_a6, output3, X, 585, 1, pull1)," &
"611 ( bc_1, ddr_a6, input, X )," &
"612 ( bc_1, ddr_a9, output3, X, 585, 1, pull1)," &
"613 ( bc_1, ddr_a9, input, X )," &
"614 ( bc_1, ddr_a4, output3, X, 585, 1, pull1)," &
"615 ( bc_1, ddr_a4, input, X )," &
"616 ( bc_1, ddr_a3, output3, X, 585, 1, pull1)," &
"617 ( bc_1, ddr_a3, input, X )," &
"618 ( bc_1, ddr_ba0, output3, X, 592, 1, pull1)," &
"619 ( bc_1, ddr_ba0, input, X )," &
"620 ( bc_1, ddr_a5, output3, X, 585, 1, pull1)," &
"621 ( bc_1, ddr_a5, input, X )," &
"622 ( bc_1, ddr_wen, output3, X, 592, 1, pull1)," &
"623 ( bc_1, ddr_wen, input, X )," &
"624 ( bc_1, ddr_ba2, output3, X, 592, 1, pull1)," &
"625 ( bc_1, ddr_ba2, input, X )," &
"626 ( bc_1, ddr_d15, output3, X, 627, 1, pull0)," &
"627 ( bc_1, *, control, 1 )," &
"628 ( bc_1, ddr_d15, input, X )," &
"629 ( bc_1, ddr_d14, output3, X, 630, 1, pull0)," &
"630 ( bc_1, *, control, 1 )," &
"631 ( bc_1, ddr_d14, input, X )," &
"632 ( bc_1, ddr_d13, output3, X, 633, 1, pull0)," &
"633 ( bc_1, *, control, 1 )," &
"634 ( bc_1, ddr_d13, input, X )," &
"635 ( bc_1, ddr_d12, output3, X, 636, 1, pull0)," &
"636 ( bc_1, *, control, 1 )," &
"637 ( bc_1, ddr_d12, input, X )," &
"638 ( bc_1, ddr_dqs1, output3, X, 639, 1, pull0)," &
"639 ( bc_1, *, control, 1 )," &
"640 ( bc_1, ddr_dqs1, input, X )," &
"641 ( bc_1, ddr_d11, output3, X, 642, 1, pull0)," &
"642 ( bc_1, *, control, 1 )," &
"643 ( bc_1, ddr_d11, input, X )," &
"644 ( bc_1, ddr_d10, output3, X, 645, 1, pull0)," &
"645 ( bc_1, *, control, 1 )," &
"646 ( bc_1, ddr_d10, input, X )," &
"647 ( bc_1, ddr_d9, output3, X, 648, 1, pull0)," &
"648 ( bc_1, *, control, 1 )," &
"649 ( bc_1, ddr_d9, input, X )," &
"650 ( bc_1, ddr_d8, output3, X, 651, 1, pull0)," &
"651 ( bc_1, *, control, 1 )," &
"652 ( bc_1, ddr_d8, input, X )," &
"653 ( bc_1, ddr_dqm1, output3, X, 654, 1, pull1)," &
"654 ( bc_1, *, control, 1 )," &
"655 ( bc_1, ddr_dqm1, input, X )," &
"656 ( bc_1, ddr_d7, output3, X, 657, 1, pull0)," &
"657 ( bc_1, *, control, 1 )," &
"658 ( bc_1, ddr_d7, input, X )," &
"659 ( bc_1, ddr_d6, output3, X, 660, 1, pull0)," &
"660 ( bc_1, *, control, 1 )," &
"661 ( bc_1, ddr_d6, input, X )," &
"662 ( bc_1, ddr_d5, output3, X, 663, 1, pull0)," &
"663 ( bc_1, *, control, 1 )," &
"664 ( bc_1, ddr_d5, input, X )," &
"665 ( bc_1, ddr_d4, output3, X, 666, 1, pull0)," &
"666 ( bc_1, *, control, 1 )," &
"667 ( bc_1, ddr_d4, input, X )," &
"668 ( bc_1, ddr_dqs0, output3, X, 669, 1, pull0)," &
"669 ( bc_1, *, control, 1 )," &
"670 ( bc_1, ddr_dqs0, input, X )," &
"671 ( bc_1, ddr_d3, output3, X, 672, 1, pull0)," &
"672 ( bc_1, *, control, 1 )," &
"673 ( bc_1, ddr_d3, input, X )," &
"674 ( bc_1, ddr_d2, output3, X, 675, 1, pull0)," &
"675 ( bc_1, *, control, 1 )," &
"676 ( bc_1, ddr_d2, input, X )," &
"677 ( bc_1, ddr_d1, output3, X, 678, 1, pull0)," &
"678 ( bc_1, *, control, 1 )," &
"679 ( bc_1, ddr_d1, input, X )," &
"680 ( bc_1, ddr_d0, output3, X, 681, 1, pull0)," &
"681 ( bc_1, *, control, 1 )," &
"682 ( bc_1, ddr_d0, input, X )," &
"683 ( bc_1, ddr_dqm0, output3, X, 684, 1, pull1)," &
"684 ( bc_1, *, control, 1 )," &
"685 ( bc_1, ddr_dqm0, input, X )," &
"686 ( bc_1, mmc0_cmd, output3, X, 687, 1, Z)," &
"687 ( bc_1, *, control, 1 )," &
"688 ( bc_1, mmc0_cmd, input, X )," &
"689 ( bc_1, mmc0_clk, output3, X, 690, 1, Z)," &
"690 ( bc_1, *, control, 1 )," &
"691 ( bc_1, mmc0_clk, input, X )," &
"692 ( bc_1, mmc0_dat0, output3, X, 693, 1, Z)," &
"693 ( bc_1, *, control, 1 )," &
"694 ( bc_1, mmc0_dat0, input, X )," &
"695 ( bc_1, mmc0_dat1, output3, X, 696, 1, Z)," &
"696 ( bc_1, *, control, 1 )," &
"697 ( bc_1, mmc0_dat1, input, X )," &
"698 ( bc_1, mmc0_dat3, output3, X, 699, 1, Z)," &
"699 ( bc_1, *, control, 1 )," &
"700 ( bc_1, mmc0_dat3, input, X )," &
"701 ( bc_1, mmc0_dat2, output3, X, 702, 1, Z)," &
"702 ( bc_1, *, control, 1 )," &
"703 ( bc_1, mmc0_dat2, input, X )," &
"704 ( bc_1, gpmc_a0, output3, X, 705, 1, pull0)," &
"705 ( bc_1, *, control, 1 )," &
"706 ( bc_1, gpmc_a0, input, X )," &
"707 ( bc_1, gpmc_a1, output3, X, 708, 1, pull0)," &
"708 ( bc_1, *, control, 1 )," &
"709 ( bc_1, gpmc_a1, input, X )," &
"710 ( bc_1, gpmc_a2, output3, X, 711, 1, pull0)," &
"711 ( bc_1, *, control, 1 )," &
"712 ( bc_1, gpmc_a2, input, X )," &
"713 ( bc_1, gpmc_a3, output3, X, 714, 1, pull0)," &
"714 ( bc_1, *, control, 1 )," &
"715 ( bc_1, gpmc_a3, input, X )," &
"716 ( bc_1, gpmc_a4, output3, X, 717, 1, pull0)," &
"717 ( bc_1, *, control, 1 )," &
"718 ( bc_1, gpmc_a4, input, X )," &
"719 ( bc_1, gpmc_a5, output3, X, 720, 1, pull0)," &
"720 ( bc_1, *, control, 1 )," &
"721 ( bc_1, gpmc_a5, input, X )," &
"722 ( bc_1, gpmc_a6, output3, X, 723, 1, pull0)," &
"723 ( bc_1, *, control, 1 )," &
"724 ( bc_1, gpmc_a6, input, X )," &
"725 ( bc_1, gpmc_a7, output3, X, 726, 1, pull0)," &
"726 ( bc_1, *, control, 1 )," &
"727 ( bc_1, gpmc_a7, input, X )," &
"728 ( bc_1, gpmc_a8, output3, X, 729, 1, pull0)," &
"729 ( bc_1, *, control, 1 )," &
"730 ( bc_1, gpmc_a8, input, X )," &
"731 ( bc_1, gpmc_a9, output3, X, 732, 1, pull0)," &
"732 ( bc_1, *, control, 1 )," &
"733 ( bc_1, gpmc_a9, input, X )," &
"734 ( bc_1, gpmc_a10, output3, X, 735, 1, pull0)," &
"735 ( bc_1, *, control, 1 )," &
"736 ( bc_1, gpmc_a10, input, X ) " ;
attribute DESIGN_WARNING of AM437x: entity is
"BSD JTAG TAP may not work correctly unless device has completed Power on Reset sequence first " &
"This requires the device to be powered up will all voltages , PWRONRSTn de-asserted and then XTALIN to be " &
"pulsed for 5200 cycles or wait for a minimum of 2 micro seconds assuming a 27Mhz crystal connected to " &
"XTALIN/XTALOUT pads. If the BSDL tool does not use trstn pin, please put a 10K Ohm pull up resistor ." ;
end AM437x;
