-- ../../bsdl/54SX08A_fbga144.bsd
-- FAMILY: 54SXA
-- DEVICE: A54SX08A
-- PACKAGE: 144 FBGA
-- Version: 1.0
-- RESTRICT JTAG: 0
-- RESTRICT TRST: 0
--
-- This is a preliminary BSDL file which has not been verified.
-- This BSDL file reflects the pre-programming JTAG
-- behavior. To reflect the post-programming JTAG
-- behavior, edit this file as described below:
-- If the I/O is unused or configured as an output,
-- the input boundary scan cell becomes internal only.
-- The input buffer is turned off, and you can not
-- transfer data from the I/O pad into the input scan
-- cell. For example:
-- IO(1) is an output, the BSDL entry would be modified
-- from:
-- " 0 (BC_1, IO(1), input, X), "&
-- " 1 (BC_1, IO(1), output3, X, 2, 0, Z), "&
-- " 2 (BC_1, *, control, 0), "&
-- to:
-- " 0 (BC_1, *, internal, X), "&
-- " 1 (BC_1, IO(1), output3, X, 2, 0, Z), "&
-- " 2 (BC_1, *, control, 0), "&
-- No modification is necessary when the I/O is
-- configured as an input.
entity A54SX08Abga144 is
generic (PHYSICAL_PIN_MAP : string := "bga144");
port(
CLKA :in bit;
CLKB :in bit;
GND :linkage bit_vector (0 to 14 );
HCLK :in bit;
IO_A1 :out bit;
IO_A2 :out bit;
IO_A3 :out bit;
IO_A4 :out bit;
IO_A8 :out bit;
IO_A9 :out bit;
IO_B1 :out bit;
IO_B3 :out bit;
IO_B4 :out bit;
IO_B5 :out bit;
IO_B6 :out bit;
IO_B8 :out bit;
IO_B9 :out bit;
IO_C1 :out bit;
IO_C2 :out bit;
IO_C4 :out bit;
IO_C5 :out bit;
IO_C6 :out bit;
IO_C7 :out bit;
IO_C8 :out bit;
IO_C9 :out bit;
IO_D1 :out bit;
IO_D4 :out bit;
IO_D5 :out bit;
IO_D6 :out bit;
IO_D7 :out bit;
IO_D8 :out bit;
IO_D9 :out bit;
IO_E1 :out bit;
IO_E2 :out bit;
IO_E3 :out bit;
IO_E4 :out bit;
IO_F1 :out bit;
IO_F2 :out bit;
IO_F4 :out bit;
IO_F9 :out bit;
IO_G1 :out bit;
IO_G3 :out bit;
IO_G4 :out bit;
IO_G9 :out bit;
IO_H1 :out bit;
IO_H2 :out bit;
IO_H3 :out bit;
IO_H4 :out bit;
IO_J1 :out bit;
IO_J2 :out bit;
IO_J3 :out bit;
IO_J4 :out bit;
IO_J5 :out bit;
IO_J6 :out bit;
IO_J7 :out bit;
IO_J8 :out bit;
IO_J9 :out bit;
IO_K1 :out bit;
IO_K2 :out bit;
IO_K3 :out bit;
IO_K4 :out bit;
IO_K5 :out bit;
IO_K6 :out bit;
IO_K8 :out bit;
IO_K9 :out bit;
IO_L2 :out bit;
IO_L3 :out bit;
IO_L4 :out bit;
IO_L5 :out bit;
IO_L6 :out bit;
IO_L8 :out bit;
IO_L9 :out bit;
IO_M1 :out bit;
IO_M2 :out bit;
IO_M3 :out bit;
IO_M4 :out bit;
IO_M5 :out bit;
IO_M6 :out bit;
IO_M8 :out bit;
IO_M9 :out bit;
IO_A10 :out bit;
IO_A11 :out bit;
IO_A12 :out bit;
IO_B10 :out bit;
IO_B12 :out bit;
IO_C10 :out bit;
IO_C11 :out bit;
IO_C12 :out bit;
IO_D10 :out bit;
IO_D11 :out bit;
IO_D12 :out bit;
IO_E10 :out bit;
IO_E12 :out bit;
IO_F11 :out bit;
IO_F12 :out bit;
IO_G10 :out bit;
IO_G11 :out bit;
IO_G12 :out bit;
IO_H10 :out bit;
IO_H11 :out bit;
IO_J10 :out bit;
IO_J11 :out bit;
IO_K11 :out bit;
IO_K12 :out bit;
IO_L10 :out bit;
IO_L11 :out bit;
IO_L12 :out bit;
IO_M10 :out bit;
IO_M12 :out bit;
NC :linkage bit_vector (0 to 1 );
TCK :in bit;
TDI :in bit;
TDO :out bit;
TMS :in bit;
VCC :linkage bit_vector (0 to 14 )
);
use STD_1149_1_1990.all;
attribute PIN_MAP of A54SX08Abga144 : entity is PHYSICAL_PIN_MAP;
constant bga144 : PIN_MAP_STRING:=
"CLKA :A7, "&
"CLKB :B7, "&
"GND :(A6, B11, B2, E11, F10, F5, F6, "&
"F7, G2, G5, G6, G7, K10, K7, "&
"L1), "&
"HCLK :L7, "&
"IO_A1 :A1, "&
"IO_A2 :A2, "&
"IO_A3 :A3, "&
"IO_A4 :A4, "&
"IO_A8 :A8, "&
"IO_A9 :A9, "&
"IO_B1 :B1, "&
"IO_B3 :B3, "&
"IO_B4 :B4, "&
"IO_B5 :B5, "&
"IO_B6 :B6, "&
"IO_B8 :B8, "&
"IO_B9 :B9, "&
"IO_C1 :C1, "&
"IO_C2 :C2, "&
"IO_C4 :C4, "&
"IO_C5 :C5, "&
"IO_C6 :C6, "&
"IO_C7 :C7, "&
"IO_C8 :C8, "&
"IO_C9 :C9, "&
"IO_D1 :D1, "&
"IO_D4 :D4, "&
"IO_D5 :D5, "&
"IO_D6 :D6, "&
"IO_D7 :D7, "&
"IO_D8 :D8, "&
"IO_D9 :D9, "&
"IO_E1 :E1, "&
"IO_E2 :E2, "&
"IO_E3 :E3, "&
"IO_E4 :E4, "&
"IO_F1 :F1, "&
"IO_F2 :F2, "&
"IO_F4 :F4, "&
"IO_F9 :F9, "&
"IO_G1 :G1, "&
"IO_G3 :G3, "&
"IO_G4 :G4, "&
"IO_G9 :G9, "&
"IO_H1 :H1, "&
"IO_H2 :H2, "&
"IO_H3 :H3, "&
"IO_H4 :H4, "&
"IO_J1 :J1, "&
"IO_J2 :J2, "&
"IO_J3 :J3, "&
"IO_J4 :J4, "&
"IO_J5 :J5, "&
"IO_J6 :J6, "&
"IO_J7 :J7, "&
"IO_J8 :J8, "&
"IO_J9 :J9, "&
"IO_K1 :K1, "&
"IO_K2 :K2, "&
"IO_K3 :K3, "&
"IO_K4 :K4, "&
"IO_K5 :K5, "&
"IO_K6 :K6, "&
"IO_K8 :K8, "&
"IO_K9 :K9, "&
"IO_L2 :L2, "&
"IO_L3 :L3, "&
"IO_L4 :L4, "&
"IO_L5 :L5, "&
"IO_L6 :L6, "&
"IO_L8 :L8, "&
"IO_L9 :L9, "&
"IO_M1 :M1, "&
"IO_M2 :M2, "&
"IO_M3 :M3, "&
"IO_M4 :M4, "&
"IO_M5 :M5, "&
"IO_M6 :M6, "&
"IO_M8 :M8, "&
"IO_M9 :M9, "&
"IO_A10 :A10, "&
"IO_A11 :A11, "&
"IO_A12 :A12, "&
"IO_B10 :B10, "&
"IO_B12 :B12, "&
"IO_C10 :C10, "&
"IO_C11 :C11, "&
"IO_C12 :C12, "&
"IO_D10 :D10, "&
"IO_D11 :D11, "&
"IO_D12 :D12, "&
"IO_E10 :E10, "&
"IO_E12 :E12, "&
"IO_F11 :F11, "&
"IO_F12 :F12, "&
"IO_G10 :G10, "&
"IO_G11 :G11, "&
"IO_G12 :G12, "&
"IO_H10 :H10, "&
"IO_H11 :H11, "&
"IO_J10 :J10, "&
"IO_J11 :J11, "&
"IO_K11 :K11, "&
"IO_K12 :K12, "&
"IO_L10 :L10, "&
"IO_L11 :L11, "&
"IO_L12 :L12, "&
"IO_M10 :M10, "&
"IO_M12 :M12, "&
"NC :(F3, H12), "&
"TCK :C3, "&
"TDI :D3, "&
"TDO :M11, "&
"TMS :E5, "&
"VCC :(A5, D2, E6, E7, E8, E9, F8, "&
"G8, H5, H6, H7, H8, H9, J12, "&
"M7) ";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK :
signal is ( 1.00e+007, BOTH);
attribute INSTRUCTION_LENGTH of A54SX08Abga144 : entity is 5;
attribute INSTRUCTION_OPCODE of A54SX08Abga144 : entity is
"EXTEST (00000), "&
"SAMPLE (00001), "&
"INTEST (00010), "&
"USERCODE (00011), "&
"IDCODE (00100), "&
"HIGHZ (01110), "&
"CLAMP (01111), "&
"PROBE (10000), "&
"BYPASS (11111) ";
attribute INSTRUCTION_CAPTURE of A54SX08Abga144 : entity is "XXX01";
attribute INSTRUCTION_DISABLE of A54SX08Abga144 : entity is
"HIGHZ";
attribute INSTRUCTION_GUARD of A54SX08Abga144 : entity is
"CLAMP";
attribute INSTRUCTION_PRIVATE of A54SX08Abga144 : entity is
"PROBE";
attribute IDCODE_REGISTER of A54SX08Abga144 : entity is
"XXXX"& -- Version
"XXXXXXXXXXXXXXXX"& -- Device
"00000101111"& -- Manufacturer
"1"; -- Required
attribute USERCODE_REGISTER of A54SX08Abga144 : entity is
"00000000000000000000000000000000";
attribute REGISTER_ACCESS of A54SX08Abga144 : entity is
"BYPASS(HIGHZ, CLAMP)";
attribute BOUNDARY_CELLS of A54SX08Abga144 : entity is "BC_1";
attribute BOUNDARY_LENGTH of A54SX08Abga144 : entity is 381;
attribute BOUNDARY_REGISTER of A54SX08Abga144 : entity is
-- num cell port function safe [ccell disval rslt]
--BSR IO_J3 J3
" 0 (BC_1, *,internal, X), "&
" 1 (BC_1, IO_J3, output3, X, 2, 0, Z), "&
" 2 (BC_1, *, control, 0), "&
--BSR NC
" 3 (BC_1, *,internal, X), "&
" 4 (BC_1, *,internal, X), "&
" 5 (BC_1, *,internal, X), "&
--BSR IO_K2 K2
" 6 (BC_1, *,internal, X), "&
" 7 (BC_1, IO_K2, output3, X, 8, 0, Z), "&
" 8 (BC_1, *, control, 0), "&
--BSR NC
" 9 (BC_1, *,internal, X), "&
" 10 (BC_1, *,internal, X), "&
" 11 (BC_1, *,internal, X), "&
--BSR IO_K1 K1
" 12 (BC_1, *,internal, X), "&
" 13 (BC_1, IO_K1, output3, X, 14, 0, Z), "&
" 14 (BC_1, *, control, 0), "&
--BSR IO_J2 J2
" 15 (BC_1, *,internal, X), "&
" 16 (BC_1, IO_J2, output3, X, 17, 0, Z), "&
" 17 (BC_1, *, control, 0), "&
--BSR NC
" 18 (BC_1, *,internal, X), "&
" 19 (BC_1, *,internal, X), "&
" 20 (BC_1, *,internal, X), "&
--BSR IO_H4 H4
" 21 (BC_1, *,internal, X), "&
" 22 (BC_1, IO_H4, output3, X, 23, 0, Z), "&
" 23 (BC_1, *, control, 0), "&
--BSR NC
" 24 (BC_1, *,internal, X), "&
" 25 (BC_1, *,internal, X), "&
" 26 (BC_1, *,internal, X), "&
--BSR IO_H3 H3
" 27 (BC_1, *,internal, X), "&
" 28 (BC_1, IO_H3, output3, X, 29, 0, Z), "&
" 29 (BC_1, *, control, 0), "&
--BSR IO_J1 J1
" 30 (BC_1, *,internal, X), "&
" 31 (BC_1, IO_J1, output3, X, 32, 0, Z), "&
" 32 (BC_1, *, control, 0), "&
--BSR IO_G3 G3
" 33 (BC_1, *,internal, X), "&
" 34 (BC_1, IO_G3, output3, X, 35, 0, Z), "&
" 35 (BC_1, *, control, 0), "&
--BSR IO_H2 H2
" 36 (BC_1, *,internal, X), "&
" 37 (BC_1, IO_H2, output3, X, 38, 0, Z), "&
" 38 (BC_1, *, control, 0), "&
--BSR IO_G4 G4
" 39 (BC_1, *,internal, X), "&
" 40 (BC_1, IO_G4, output3, X, 41, 0, Z), "&
" 41 (BC_1, *, control, 0), "&
--BSR IO_H1 H1
" 42 (BC_1, *,internal, X), "&
" 43 (BC_1, IO_H1, output3, X, 44, 0, Z), "&
" 44 (BC_1, *, control, 0), "&
--BSR IO_G1 G1
" 45 (BC_1, *,internal, X), "&
" 46 (BC_1, IO_G1, output3, X, 47, 0, Z), "&
" 47 (BC_1, *, control, 0), "&
--BSR NC
" 48 (BC_1, *,internal, X), "&
" 49 (BC_1, *,internal, X), "&
" 50 (BC_1, *,internal, X), "&
--BSR NC
" 51 (BC_1, *,internal, X), "&
" 52 (BC_1, *,internal, X), "&
" 53 (BC_1, *,internal, X), "&
--BSR IO_F1 F1
" 54 (BC_1, *,internal, X), "&
" 55 (BC_1, IO_F1, output3, X, 56, 0, Z), "&
" 56 (BC_1, *, control, 0), "&
--BSR IO_F4 F4
" 57 (BC_1, *,internal, X), "&
" 58 (BC_1, IO_F4, output3, X, 59, 0, Z), "&
" 59 (BC_1, *, control, 0), "&
--BSR IO_F2 F2
" 60 (BC_1, *,internal, X), "&
" 61 (BC_1, IO_F2, output3, X, 62, 0, Z), "&
" 62 (BC_1, *, control, 0), "&
--BSR IO_D1 D1
" 63 (BC_1, *,internal, X), "&
" 64 (BC_1, IO_D1, output3, X, 65, 0, Z), "&
" 65 (BC_1, *, control, 0), "&
--BSR IO_E1 E1
" 66 (BC_1, *,internal, X), "&
" 67 (BC_1, IO_E1, output3, X, 68, 0, Z), "&
" 68 (BC_1, *, control, 0), "&
--BSR IO_E2 E2
" 69 (BC_1, *,internal, X), "&
" 70 (BC_1, IO_E2, output3, X, 71, 0, Z), "&
" 71 (BC_1, *, control, 0), "&
--BSR IO_E3 E3
" 72 (BC_1, *,internal, X), "&
" 73 (BC_1, IO_E3, output3, X, 74, 0, Z), "&
" 74 (BC_1, *, control, 0), "&
--BSR IO_C1 C1
" 75 (BC_1, *,internal, X), "&
" 76 (BC_1, IO_C1, output3, X, 77, 0, Z), "&
" 77 (BC_1, *, control, 0), "&
--BSR IO_E4 E4
" 78 (BC_1, *,internal, X), "&
" 79 (BC_1, IO_E4, output3, X, 80, 0, Z), "&
" 80 (BC_1, *, control, 0), "&
--BSR IO_B1 B1
" 81 (BC_1, *,internal, X), "&
" 82 (BC_1, IO_B1, output3, X, 83, 0, Z), "&
" 83 (BC_1, *, control, 0), "&
--BSR IO_C2 C2
" 84 (BC_1, *,internal, X), "&
" 85 (BC_1, IO_C2, output3, X, 86, 0, Z), "&
" 86 (BC_1, *, control, 0), "&
--BSR IO_D4 D4
" 87 (BC_1, *,internal, X), "&
" 88 (BC_1, IO_D4, output3, X, 89, 0, Z), "&
" 89 (BC_1, *, control, 0), "&
--BSR IO_A1 A1
" 90 (BC_1, *,internal, X), "&
" 91 (BC_1, IO_A1, output3, X, 92, 0, Z), "&
" 92 (BC_1, *, control, 0), "&
--BSR IO_D5 D5
" 93 (BC_1, *,internal, X), "&
" 94 (BC_1, IO_D5, output3, X, 95, 0, Z), "&
" 95 (BC_1, *, control, 0), "&
--BSR IO_B3 B3
" 96 (BC_1, *,internal, X), "&
" 97 (BC_1, IO_B3, output3, X, 98, 0, Z), "&
" 98 (BC_1, *, control, 0), "&
--BSR IO_B4 B4
" 99 (BC_1, *,internal, X), "&
" 100 (BC_1, IO_B4, output3, X, 101, 0, Z), "&
" 101 (BC_1, *, control, 0), "&
--BSR NC
" 102 (BC_1, *,internal, X), "&
" 103 (BC_1, *,internal, X), "&
" 104 (BC_1, *,internal, X), "&
--BSR IO_C4 C4
" 105 (BC_1, *,internal, X), "&
" 106 (BC_1, IO_C4, output3, X, 107, 0, Z), "&
" 107 (BC_1, *, control, 0), "&
--BSR IO_C5 C5
" 108 (BC_1, *,internal, X), "&
" 109 (BC_1, IO_C5, output3, X, 110, 0, Z), "&
" 110 (BC_1, *, control, 0), "&
--BSR IO_D6 D6
" 111 (BC_1, *,internal, X), "&
" 112 (BC_1, IO_D6, output3, X, 113, 0, Z), "&
" 113 (BC_1, *, control, 0), "&
--BSR IO_A2 A2
" 114 (BC_1, *,internal, X), "&
" 115 (BC_1, IO_A2, output3, X, 116, 0, Z), "&
" 116 (BC_1, *, control, 0), "&
--BSR IO_A3 A3
" 117 (BC_1, *,internal, X), "&
" 118 (BC_1, IO_A3, output3, X, 119, 0, Z), "&
" 119 (BC_1, *, control, 0), "&
--BSR IO_B5 B5
" 120 (BC_1, *,internal, X), "&
" 121 (BC_1, IO_B5, output3, X, 122, 0, Z), "&
" 122 (BC_1, *, control, 0), "&
--BSR IO_A4 A4
" 123 (BC_1, *,internal, X), "&
" 124 (BC_1, IO_A4, output3, X, 125, 0, Z), "&
" 125 (BC_1, *, control, 0), "&
--BSR NC
" 126 (BC_1, *,internal, X), "&
" 127 (BC_1, *,internal, X), "&
" 128 (BC_1, *,internal, X), "&
--BSR IO_C6 C6
" 129 (BC_1, *,internal, X), "&
" 130 (BC_1, IO_C6, output3, X, 131, 0, Z), "&
" 131 (BC_1, *, control, 0), "&
--BSR IO_B6 B6
" 132 (BC_1, *,internal, X), "&
" 133 (BC_1, IO_B6, output3, X, 134, 0, Z), "&
" 134 (BC_1, *, control, 0), "&
--BSR CLKB B7
" 135 (BC_1, CLKB, input, X), "&
--BSR CLKA A7
" 136 (BC_1, CLKA, input, X), "&
--BSR NC
" 137 (BC_1, *,internal, X), "&
" 138 (BC_1, *,internal, X), "&
" 139 (BC_1, *,internal, X), "&
--BSR IO_A9 A9
" 140 (BC_1, *,internal, X), "&
" 141 (BC_1, IO_A9, output3, X, 142, 0, Z), "&
" 142 (BC_1, *, control, 0), "&
--BSR IO_A8 A8
" 143 (BC_1, *,internal, X), "&
" 144 (BC_1, IO_A8, output3, X, 145, 0, Z), "&
" 145 (BC_1, *, control, 0), "&
--BSR IO_B8 B8
" 146 (BC_1, *,internal, X), "&
" 147 (BC_1, IO_B8, output3, X, 148, 0, Z), "&
" 148 (BC_1, *, control, 0), "&
--BSR IO_D7 D7
" 149 (BC_1, *,internal, X), "&
" 150 (BC_1, IO_D7, output3, X, 151, 0, Z), "&
" 151 (BC_1, *, control, 0), "&
--BSR IO_C7 C7
" 152 (BC_1, *,internal, X), "&
" 153 (BC_1, IO_C7, output3, X, 154, 0, Z), "&
" 154 (BC_1, *, control, 0), "&
--BSR IO_A10 A10
" 155 (BC_1, *,internal, X), "&
" 156 (BC_1, IO_A10, output3, X, 157, 0, Z), "&
" 157 (BC_1, *, control, 0), "&
--BSR IO_B9 B9
" 158 (BC_1, *,internal, X), "&
" 159 (BC_1, IO_B9, output3, X, 160, 0, Z), "&
" 160 (BC_1, *, control, 0), "&
--BSR IO_C8 C8
" 161 (BC_1, *,internal, X), "&
" 162 (BC_1, IO_C8, output3, X, 163, 0, Z), "&
" 163 (BC_1, *, control, 0), "&
--BSR IO_D8 D8
" 164 (BC_1, *,internal, X), "&
" 165 (BC_1, IO_D8, output3, X, 166, 0, Z), "&
" 166 (BC_1, *, control, 0), "&
--BSR NC
" 167 (BC_1, *,internal, X), "&
" 168 (BC_1, *,internal, X), "&
" 169 (BC_1, *,internal, X), "&
--BSR IO_A11 A11
" 170 (BC_1, *,internal, X), "&
" 171 (BC_1, IO_A11, output3, X, 172, 0, Z), "&
" 172 (BC_1, *, control, 0), "&
--BSR IO_C9 C9
" 173 (BC_1, *,internal, X), "&
" 174 (BC_1, IO_C9, output3, X, 175, 0, Z), "&
" 175 (BC_1, *, control, 0), "&
--BSR IO_A12 A12
" 176 (BC_1, *,internal, X), "&
" 177 (BC_1, IO_A12, output3, X, 178, 0, Z), "&
" 178 (BC_1, *, control, 0), "&
--BSR IO_B10 B10
" 179 (BC_1, *,internal, X), "&
" 180 (BC_1, IO_B10, output3, X, 181, 0, Z), "&
" 181 (BC_1, *, control, 0), "&
--BSR IO_C10 C10
" 182 (BC_1, *,internal, X), "&
" 183 (BC_1, IO_C10, output3, X, 184, 0, Z), "&
" 184 (BC_1, *, control, 0), "&
--BSR NC
" 185 (BC_1, *,internal, X), "&
" 186 (BC_1, *,internal, X), "&
" 187 (BC_1, *,internal, X), "&
--BSR IO_C11 C11
" 188 (BC_1, *,internal, X), "&
" 189 (BC_1, IO_C11, output3, X, 190, 0, Z), "&
" 190 (BC_1, *, control, 0), "&
--BSR IO_B12 B12
" 191 (BC_1, *,internal, X), "&
" 192 (BC_1, IO_B12, output3, X, 193, 0, Z), "&
" 193 (BC_1, *, control, 0), "&
--BSR IO_D9 D9
" 194 (BC_1, *,internal, X), "&
" 195 (BC_1, IO_D9, output3, X, 196, 0, Z), "&
" 196 (BC_1, *, control, 0), "&
--BSR IO_C12 C12
" 197 (BC_1, *,internal, X), "&
" 198 (BC_1, IO_C12, output3, X, 199, 0, Z), "&
" 199 (BC_1, *, control, 0), "&
--BSR IO_D10 D10
" 200 (BC_1, *,internal, X), "&
" 201 (BC_1, IO_D10, output3, X, 202, 0, Z), "&
" 202 (BC_1, *, control, 0), "&
--BSR IO_D11 D11
" 203 (BC_1, *,internal, X), "&
" 204 (BC_1, IO_D11, output3, X, 205, 0, Z), "&
" 205 (BC_1, *, control, 0), "&
--BSR IO_E10 E10
" 206 (BC_1, *,internal, X), "&
" 207 (BC_1, IO_E10, output3, X, 208, 0, Z), "&
" 208 (BC_1, *, control, 0), "&
--BSR IO_F9 F9
" 209 (BC_1, *,internal, X), "&
" 210 (BC_1, IO_F9, output3, X, 211, 0, Z), "&
" 211 (BC_1, *, control, 0), "&
--BSR IO_D12 D12
" 212 (BC_1, *,internal, X), "&
" 213 (BC_1, IO_D12, output3, X, 214, 0, Z), "&
" 214 (BC_1, *, control, 0), "&
--BSR IO_E12 E12
" 215 (BC_1, *,internal, X), "&
" 216 (BC_1, IO_E12, output3, X, 217, 0, Z), "&
" 217 (BC_1, *, control, 0), "&
--BSR IO_F12 F12
" 218 (BC_1, *,internal, X), "&
" 219 (BC_1, IO_F12, output3, X, 220, 0, Z), "&
" 220 (BC_1, *, control, 0), "&
--BSR IO_F11 F11
" 221 (BC_1, *,internal, X), "&
" 222 (BC_1, IO_F11, output3, X, 223, 0, Z), "&
" 223 (BC_1, *, control, 0), "&
--BSR IO_G12 G12
" 224 (BC_1, *,internal, X), "&
" 225 (BC_1, IO_G12, output3, X, 226, 0, Z), "&
" 226 (BC_1, *, control, 0), "&
--BSR NC
" 227 (BC_1, *,internal, X), "&
" 228 (BC_1, *,internal, X), "&
" 229 (BC_1, *,internal, X), "&
--BSR NC
" 230 (BC_1, *,internal, X), "&
" 231 (BC_1, *,internal, X), "&
" 232 (BC_1, *,internal, X), "&
--BSR NC
" 233 (BC_1, *,internal, X), "&
" 234 (BC_1, *,internal, X), "&
" 235 (BC_1, *,internal, X), "&
--BSR IO_G11 G11
" 236 (BC_1, *,internal, X), "&
" 237 (BC_1, IO_G11, output3, X, 238, 0, Z), "&
" 238 (BC_1, *, control, 0), "&
--BSR IO_G10 G10
" 239 (BC_1, *,internal, X), "&
" 240 (BC_1, IO_G10, output3, X, 241, 0, Z), "&
" 241 (BC_1, *, control, 0), "&
--BSR IO_K12 K12
" 242 (BC_1, *,internal, X), "&
" 243 (BC_1, IO_K12, output3, X, 244, 0, Z), "&
" 244 (BC_1, *, control, 0), "&
--BSR IO_G9 G9
" 245 (BC_1, *,internal, X), "&
" 246 (BC_1, IO_G9, output3, X, 247, 0, Z), "&
" 247 (BC_1, *, control, 0), "&
--BSR IO_H11 H11
" 248 (BC_1, *,internal, X), "&
" 249 (BC_1, IO_H11, output3, X, 250, 0, Z), "&
" 250 (BC_1, *, control, 0), "&
--BSR IO_J11 J11
" 251 (BC_1, *,internal, X), "&
" 252 (BC_1, IO_J11, output3, X, 253, 0, Z), "&
" 253 (BC_1, *, control, 0), "&
--BSR IO_H10 H10
" 254 (BC_1, *,internal, X), "&
" 255 (BC_1, IO_H10, output3, X, 256, 0, Z), "&
" 256 (BC_1, *, control, 0), "&
--BSR NC
" 257 (BC_1, *,internal, X), "&
" 258 (BC_1, *,internal, X), "&
" 259 (BC_1, *,internal, X), "&
--BSR IO_K11 K11
" 260 (BC_1, *,internal, X), "&
" 261 (BC_1, IO_K11, output3, X, 262, 0, Z), "&
" 262 (BC_1, *, control, 0), "&
--BSR IO_L12 L12
" 263 (BC_1, *,internal, X), "&
" 264 (BC_1, IO_L12, output3, X, 265, 0, Z), "&
" 265 (BC_1, *, control, 0), "&
--BSR IO_J9 J9
" 266 (BC_1, *,internal, X), "&
" 267 (BC_1, IO_J9, output3, X, 268, 0, Z), "&
" 268 (BC_1, *, control, 0), "&
--BSR IO_J10 J10
" 269 (BC_1, *,internal, X), "&
" 270 (BC_1, IO_J10, output3, X, 271, 0, Z), "&
" 271 (BC_1, *, control, 0), "&
--BSR IO_M12 M12
" 272 (BC_1, *,internal, X), "&
" 273 (BC_1, IO_M12, output3, X, 274, 0, Z), "&
" 274 (BC_1, *, control, 0), "&
--BSR NC
" 275 (BC_1, *,internal, X), "&
" 276 (BC_1, *,internal, X), "&
" 277 (BC_1, *,internal, X), "&
--BSR IO_L11 L11
" 278 (BC_1, *,internal, X), "&
" 279 (BC_1, IO_L11, output3, X, 280, 0, Z), "&
" 280 (BC_1, *, control, 0), "&
--BSR NC
" 281 (BC_1, *,internal, X), "&
" 282 (BC_1, *,internal, X), "&
" 283 (BC_1, *,internal, X), "&
--BSR IO_K9 K9
" 284 (BC_1, *,internal, X), "&
" 285 (BC_1, IO_K9, output3, X, 286, 0, Z), "&
" 286 (BC_1, *, control, 0), "&
--BSR NC
" 287 (BC_1, *,internal, X), "&
" 288 (BC_1, *,internal, X), "&
" 289 (BC_1, *,internal, X), "&
--BSR IO_L10 L10
" 290 (BC_1, *,internal, X), "&
" 291 (BC_1, IO_L10, output3, X, 292, 0, Z), "&
" 292 (BC_1, *, control, 0), "&
--BSR NC
" 293 (BC_1, *,internal, X), "&
" 294 (BC_1, *,internal, X), "&
" 295 (BC_1, *,internal, X), "&
--BSR IO_K8 K8
" 296 (BC_1, *,internal, X), "&
" 297 (BC_1, IO_K8, output3, X, 298, 0, Z), "&
" 298 (BC_1, *, control, 0), "&
--BSR IO_J8 J8
" 299 (BC_1, *,internal, X), "&
" 300 (BC_1, IO_J8, output3, X, 301, 0, Z), "&
" 301 (BC_1, *, control, 0), "&
--BSR IO_L9 L9
" 302 (BC_1, *,internal, X), "&
" 303 (BC_1, IO_L9, output3, X, 304, 0, Z), "&
" 304 (BC_1, *, control, 0), "&
--BSR IO_M10 M10
" 305 (BC_1, *,internal, X), "&
" 306 (BC_1, IO_M10, output3, X, 307, 0, Z), "&
" 307 (BC_1, *, control, 0), "&
--BSR IO_L8 L8
" 308 (BC_1, *,internal, X), "&
" 309 (BC_1, IO_L8, output3, X, 310, 0, Z), "&
" 310 (BC_1, *, control, 0), "&
--BSR IO_M8 M8
" 311 (BC_1, *,internal, X), "&
" 312 (BC_1, IO_M8, output3, X, 313, 0, Z), "&
" 313 (BC_1, *, control, 0), "&
--BSR NC
" 314 (BC_1, *,internal, X), "&
" 315 (BC_1, *,internal, X), "&
" 316 (BC_1, *,internal, X), "&
--BSR IO_M9 M9
" 317 (BC_1, *,internal, X), "&
" 318 (BC_1, IO_M9, output3, X, 319, 0, Z), "&
" 319 (BC_1, *, control, 0), "&
--BSR NC
" 320 (BC_1, *,internal, X), "&
" 321 (BC_1, *,internal, X), "&
" 322 (BC_1, *,internal, X), "&
--BSR HCLK L7
" 323 (BC_1, HCLK, input, X), "&
--BSR IO_J7 J7
" 324 (BC_1, *,internal, X), "&
" 325 (BC_1, IO_J7, output3, X, 326, 0, Z), "&
" 326 (BC_1, *, control, 0), "&
--BSR IO_M6 M6
" 327 (BC_1, *,internal, X), "&
" 328 (BC_1, IO_M6, output3, X, 329, 0, Z), "&
" 329 (BC_1, *, control, 0), "&
--BSR IO_J6 J6
" 330 (BC_1, *,internal, X), "&
" 331 (BC_1, IO_J6, output3, X, 332, 0, Z), "&
" 332 (BC_1, *, control, 0), "&
--BSR IO_M5 M5
" 333 (BC_1, *,internal, X), "&
" 334 (BC_1, IO_M5, output3, X, 335, 0, Z), "&
" 335 (BC_1, *, control, 0), "&
--BSR IO_M4 M4
" 336 (BC_1, *,internal, X), "&
" 337 (BC_1, IO_M4, output3, X, 338, 0, Z), "&
" 338 (BC_1, *, control, 0), "&
--BSR IO_L6 L6
" 339 (BC_1, *,internal, X), "&
" 340 (BC_1, IO_L6, output3, X, 341, 0, Z), "&
" 341 (BC_1, *, control, 0), "&
--BSR IO_L5 L5
" 342 (BC_1, *,internal, X), "&
" 343 (BC_1, IO_L5, output3, X, 344, 0, Z), "&
" 344 (BC_1, *, control, 0), "&
--BSR IO_K6 K6
" 345 (BC_1, *,internal, X), "&
" 346 (BC_1, IO_K6, output3, X, 347, 0, Z), "&
" 347 (BC_1, *, control, 0), "&
--BSR IO_M3 M3
" 348 (BC_1, *,internal, X), "&
" 349 (BC_1, IO_M3, output3, X, 350, 0, Z), "&
" 350 (BC_1, *, control, 0), "&
--BSR IO_L4 L4
" 351 (BC_1, *,internal, X), "&
" 352 (BC_1, IO_L4, output3, X, 353, 0, Z), "&
" 353 (BC_1, *, control, 0), "&
--BSR IO_K5 K5
" 354 (BC_1, *,internal, X), "&
" 355 (BC_1, IO_K5, output3, X, 356, 0, Z), "&
" 356 (BC_1, *, control, 0), "&
--BSR IO_K4 K4
" 357 (BC_1, *,internal, X), "&
" 358 (BC_1, IO_K4, output3, X, 359, 0, Z), "&
" 359 (BC_1, *, control, 0), "&
--BSR IO_J5 J5
" 360 (BC_1, *,internal, X), "&
" 361 (BC_1, IO_J5, output3, X, 362, 0, Z), "&
" 362 (BC_1, *, control, 0), "&
--BSR IO_M2 M2
" 363 (BC_1, *,internal, X), "&
" 364 (BC_1, IO_M2, output3, X, 365, 0, Z), "&
" 365 (BC_1, *, control, 0), "&
--BSR IO_J4 J4
" 366 (BC_1, *,internal, X), "&
" 367 (BC_1, IO_J4, output3, X, 368, 0, Z), "&
" 368 (BC_1, *, control, 0), "&
--BSR IO_M1 M1
" 369 (BC_1, *,internal, X), "&
" 370 (BC_1, IO_M1, output3, X, 371, 0, Z), "&
" 371 (BC_1, *, control, 0), "&
--BSR IO_L3 L3
" 372 (BC_1, *,internal, X), "&
" 373 (BC_1, IO_L3, output3, X, 374, 0, Z), "&
" 374 (BC_1, *, control, 0), "&
--BSR IO_L2 L2
" 375 (BC_1, *,internal, X), "&
" 376 (BC_1, IO_L2, output3, X, 377, 0, Z), "&
" 377 (BC_1, *, control, 0), "&
--BSR IO_K3 K3
" 378 (BC_1, *,internal, X), "&
" 379 (BC_1, IO_K3, output3, X, 380, 0, Z), "&
" 380 (BC_1, *, control, 0) ";
end A54SX08Abga144;