-- ***************************************************************
-- Company: Integrated Device Technology, Inc.
--
-- Document number: 35D7000_BS001_02
--
-- Title: BSDL file of Tsi620
-- Generated by : Andi Sugandi
--
-- Release status: formal issue
-- Security level: client use
-- BSDL Version 2001
-- Group ownership: DFT Revision Date:
-- Released by :
-- Revision History:
-- Oct 18, 2007: initial release
-- Jul 23, 2009: Updated with IDT formatting
--
-- BSDL Syntax Checker -> passed Oct 18, 2007
--
--
--
-- ***************************************************************
--
-- Generated by boundaryScanGenerate 4.2b-Build20051027.004 on 03/15/07 16:16:33
-- BSDL Version 2001
-- The default acjt_lvl[4:0] which is controlled by IRbits[34:30] is set to 2'h03,
-- tx_lvl which is controlled by IRbits[40:36] is set to 4'h1F
-- To program acjt_lvl and tx_lvl IRbits[35] has to be set to 0
-- Note: SPARE[1:0] are connected to Vdd or Gnd on system/board. So in bsdl put them as gnd or Vdd
-- HIGHZ has been removed
-- TRI_b (J22) renamed as VDD_PCI; core_vdd as VDD; core_vss as VSS
entity Tsi620 is
generic (PHYSICAL_PIN_MAP : string := "HSBGA_675_27");
port (
-- Port List
SP4_TD_p : out bit;
SP4_TD_n : out bit;
SP4_RD_p : in bit;
SP4_RD_n : in bit;
SP4_TC_p : out bit;
SP4_TC_n : out bit;
SP4_RC_p : in bit;
SP4_RC_n : in bit;
SP4_TB_p : out bit;
SP4_TB_n : out bit;
SP4_RB_p : in bit;
SP4_RB_n : in bit;
SP4_TA_p : out bit;
SP4_TA_n : out bit;
SP4_RA_p : in bit;
SP4_RA_n : in bit;
SP4_REXT : linkage bit;
SP2_TD_p : out bit;
SP2_TD_n : out bit;
SP2_RD_p : in bit;
SP2_RD_n : in bit;
SP2_TC_p : out bit;
SP2_TC_n : out bit;
SP2_RC_p : in bit;
SP2_RC_n : in bit;
SP2_TB_p : out bit;
SP2_TB_n : out bit;
SP2_RB_p : in bit;
SP2_RB_n : in bit;
SP2_TA_p : out bit;
SP2_TA_n : out bit;
SP2_RA_p : in bit;
SP2_RA_n : in bit;
SP2_REXT : linkage bit;
SP0_TD_p : out bit;
SP0_TD_n : out bit;
SP0_RD_p : in bit;
SP0_RD_n : in bit;
SP0_TC_p : out bit;
SP0_TC_n : out bit;
SP0_RC_p : in bit;
SP0_RC_n : in bit;
SP0_TB_p : out bit;
SP0_TB_n : out bit;
SP0_RB_p : in bit;
SP0_RB_n : in bit;
SP0_TA_p : out bit;
SP0_TA_n : out bit;
SP0_RA_p : in bit;
SP0_RA_n : in bit;
SP0_REXT : linkage bit;
GPIO : inout bit_vector( 31 downto 0 );
SP6_RXD : inout bit_vector( 31 downto 0 );
SP6_VREF : linkage bit_vector( 1 downto 0 );
SP6_RXCTL : inout bit_vector( 3 downto 0 );
SP6_RXCLK : inout bit;
SP6_TXD : out bit_vector( 31 downto 0 );
SP6_RX_ERROR : inout bit;
SP6_TXCTL : out bit_vector( 3 downto 0 );
SP6_TXCLK : out bit;
SP6_PHY_DISABLE : out bit;
SP0_MODE_SEL : inout bit;
SP2_MODE_SEL : inout bit;
MCES : inout bit;
SPARE : linkage bit_vector( 1 downto 0 );
SP4_MODE_SEL : inout bit;
SP6_MODE_SEL : inout bit;
SP6_PWRDN : inout bit;
SP1_PWRDN : inout bit;
SP2_PWRDN : inout bit;
SP3_PWRDN : inout bit;
SP4_PWRDN : inout bit;
SP_IO_SPEED : inout bit_vector( 1 downto 0 );
SP5_PWRDN : inout bit;
SP_MAST_EN : inout bit;
SP_RX_SWAP : inout bit;
SP_TX_SWAP : inout bit;
SP_HOST : inout bit;
SP_CLK_SEL : inout bit_vector( 1 downto 0 );
CHIP_RST_b : linkage bit;
BCE : in bit;
RST_IRQ_b : linkage bit;
SPY_CLK_1 : linkage bit;
INT_b : out bit;
TCK : in bit;
SPY_CLK_2 : linkage bit;
TDI : in bit;
BLK_RST_b : in bit;
TDO : out bit;
DO : out bit;
TMS : in bit;
I2C_SA : in bit_vector( 6 downto 0 );
TRST_b : in bit;
DI : in bit;
I2C_SD : inout bit;
I2C_MA : in bit;
I2C_SCLK : inout bit;
I2C_SEL : inout bit;
I2C_DISABLE : in bit;
PCI_PLL_BYPASS : in bit;
PCI_INTDn : inout bit;
PCI_HOLD_BOOT : in bit;
I2C_SLAVE : in bit;
PCI_CLK : in bit;
PCI_CLKO : out bit_vector( 4 downto 0 );
PCI_RSTDIR : in bit;
PCI_ARBEN : in bit;
PCI_INTCn : inout bit;
PCI_GNTn : inout bit_vector( 4 downto 1 );
PCI_INTAn : inout bit;
PCI_INTBn : inout bit;
PCI_RSTn : linkage bit;
PCI_REQn : inout bit_vector( 4 downto 1 );
PCI_AD : inout bit_vector( 31 downto 0 );
PCI_PMEn : inout bit;
PCI_IDSEL : in bit;
PCI_CBEn : inout bit_vector( 3 downto 0 );
PCI_IRDYn : inout bit;
PCI_FRAMEn : inout bit;
PCI_TRDYn : inout bit;
PCI_PAR : inout bit;
PCI_STOPn : inout bit;
PCI_DEVSELn : inout bit;
PCI_PERRn : inout bit;
PCI_SERRn : inout bit;
PCI_M66EN : in bit;
S_CLK_p : linkage bit;
S_CLK_n : linkage bit;
TCK2_p : linkage bit;
TCK2_n : linkage bit;
PCI_PLL_AVDD : linkage bit;
PCI_PLL_AVSS : linkage bit;
CLKGEN_PLL_AVDD : linkage bit;
CLKGEN_PLL_AVSS : linkage bit;
VDD_PCI : linkage bit_vector( 23 downto 0 );
VDD_HSTL : linkage bit_vector( 10 downto 0 );
SP_AVDD : linkage bit_vector( 14 downto 0 );
SP_VDD : linkage bit_vector( 39 downto 0 );
VDD : linkage bit_vector( 45 downto 0 );
VSS : linkage bit_vector( 177 downto 0 );
VSS_IO : linkage bit_vector( 63 downto 0 );
NC_SP6_TA_p : linkage bit;
NC_SP6_TA_n : linkage bit;
NC_SP0_REFCLK_p : linkage bit;
NC_SP0_REFCLK_n : linkage bit;
NC_SP2_REFCLK_p : linkage bit;
NC_SP2_REFCLK_n : linkage bit;
NC_SP4_REFCLK_p : linkage bit;
NC_SP4_REFCLK_n : linkage bit;
NC_SP6_RA_p : linkage bit;
NC_SP6_RA_n : linkage bit;
NC_SP6_REXT : linkage bit;
NC_SP6_REFCLK_n : linkage bit;
NC_SP6_REFCLK_p : linkage bit);
use STD_1149_1_2001.all;
use STD_1149_6_2003.all;
use LVS_BSCAN_CELLS.all;
attribute COMPONENT_CONFORMANCE of Tsi620: entity is "STD_1149_1_2001";
--Pin mappings
attribute PIN_MAP of Tsi620: entity is PHYSICAL_PIN_MAP;
constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING :=
"SP4_TD_p : AE13 , " &
"SP4_TD_n : AF13 , " &
"SP4_RD_p : AB13 , " &
"SP4_RD_n : AC13 , " &
"SP4_TC_p : AE11 , " &
"SP4_TC_n : AF11 , " &
"SP4_RC_p : AB11 , " &
"SP4_RC_n : AC11 , " &
"SP4_TB_p : AF9 , " &
"SP4_TB_n : AE9 , " &
"SP4_RB_p : AC9 , " &
"SP4_RB_n : AB9 , " &
"SP4_TA_p : AE7 , " &
"SP4_TA_n : AF7 , " &
"SP4_RA_p : AB7 , " &
"SP4_RA_n : AC7 , " &
"SP4_REXT : AC10 , " &
"SP2_TD_p : AE21 , " &
"SP2_TD_n : AF21 , " &
"SP2_RD_p : AB21 , " &
"SP2_RD_n : AC21 , " &
"SP2_TC_p : AE19 , " &
"SP2_TC_n : AF19 , " &
"SP2_RC_p : AC19 , " &
"SP2_RC_n : AB19 , " &
"SP2_TB_p : AF17 , " &
"SP2_TB_n : AE17 , " &
"SP2_RB_p : AB17 , " &
"SP2_RB_n : AC17 , " &
"SP2_TA_p : AE15 , " &
"SP2_TA_n : AF15 , " &
"SP2_RA_p : AB15 , " &
"SP2_RA_n : AC15 , " &
"SP2_REXT : AC18 , " &
"SP0_TD_p : P26 , " &
"SP0_TD_n : P25 , " &
"SP0_RD_p : P23 , " &
"SP0_RD_n : P22 , " &
"SP0_TC_p : T26 , " &
"SP0_TC_n : T25 , " &
"SP0_RC_p : T22 , " &
"SP0_RC_n : T23 , " &
"SP0_TB_p : V25 , " &
"SP0_TB_n : V26 , " &
"SP0_RB_p : V23 , " &
"SP0_RB_n : V22 , " &
"SP0_TA_p : Y25 , " &
"SP0_TA_n : Y26 , " &
"SP0_RA_p : Y22 , " &
"SP0_RA_n : Y23 , " &
"SP0_REXT : U23 , " &
"GPIO :(H5 , " & -- GPIO[31]
"H4 , " & -- GPIO[30]
"H3 , " & -- GPIO[29]
"H2 , " & -- GPIO[28]
"H1 , " & -- GPIO[27]
"G5 , " & -- GPIO[26]
"G3 , " & -- GPIO[25]
"G1 , " & -- GPIO[24]
"F5 , " & -- GPIO[23]
"F4 , " & -- GPIO[22]
"F3 , " & -- GPIO[21]
"F2 , " & -- GPIO[20]
"F1 , " & -- GPIO[19]
"E5 , " & -- GPIO[18]
"E4 , " & -- GPIO[17]
"E3 , " & -- GPIO[16]
"E2 , " & -- GPIO[15]
"E1 , " & -- GPIO[14]
"D4 , " & -- GPIO[13]
"D3 , " & -- GPIO[12]
"D1 , " & -- GPIO[11]
"C5 , " & -- GPIO[10]
"C4 , " & -- GPIO[9]
"C3 , " & -- GPIO[8]
"C2 , " & -- GPIO[7]
"C1 , " & -- GPIO[6]
"B4 , " & -- GPIO[5]
"B3 , " & -- GPIO[4]
"B1 , " & -- GPIO[3]
"A4 , " & -- GPIO[2]
"A3 , " & -- GPIO[1]
"A2 ), " & -- GPIO[0]
"SP6_RXD :(U3 , " & -- SP6_RXD[31]
"U2 , " & -- SP6_RXD[30]
"U1 , " & -- SP6_RXD[29]
"T5 , " & -- SP6_RXD[28]
"T3 , " & -- SP6_RXD[27]
"T1 , " & -- SP6_RXD[26]
"R5 , " & -- SP6_RXD[25]
"R4 , " & -- SP6_RXD[24]
"R2 , " & -- SP6_RXD[23]
"R1 , " & -- SP6_RXD[22]
"P5 , " & -- SP6_RXD[21]
"P4 , " & -- SP6_RXD[20]
"P3 , " & -- SP6_RXD[19]
"P2 , " & -- SP6_RXD[18]
"N5 , " & -- SP6_RXD[17]
"N1 , " & -- SP6_RXD[16]
"M4 , " & -- SP6_RXD[15]
"M3 , " & -- SP6_RXD[14]
"M2 , " & -- SP6_RXD[13]
"M1 , " & -- SP6_RXD[12]
"L5 , " & -- SP6_RXD[11]
"L4 , " & -- SP6_RXD[10]
"L3 , " & -- SP6_RXD[9]
"L2 , " & -- SP6_RXD[8]
"K5 , " & -- SP6_RXD[7]
"K3 , " & -- SP6_RXD[6]
"K1 , " & -- SP6_RXD[5]
"J5 , " & -- SP6_RXD[4]
"J4 , " & -- SP6_RXD[3]
"J3 , " & -- SP6_RXD[2]
"J2 , " & -- SP6_RXD[1]
"J1 ), " & -- SP6_RXD[0]
"SP6_VREF :(N3 , " & -- SP6_VREF[1]
"AB3 ), " & -- SP6_VREF[0]
"SP6_RXCTL :(U4 , " & -- SP6_RXCTL[3]
"R3 , " & -- SP6_RXCTL[2]
"M5 , " & -- SP6_RXCTL[1]
"L1 ), " & -- SP6_RXCTL[0]
"SP6_RXCLK : P1 , " &
"SP6_TXD :(AF3 , " & -- SP6_TXD[31]
"AF2 , " & -- SP6_TXD[30]
"AF1 , " & -- SP6_TXD[29]
"AE5 , " & -- SP6_TXD[28]
"AE3 , " & -- SP6_TXD[27]
"AE1 , " & -- SP6_TXD[26]
"AD5 , " & -- SP6_TXD[25]
"AD4 , " & -- SP6_TXD[24]
"AD2 , " & -- SP6_TXD[23]
"AD1 , " & -- SP6_TXD[22]
"AC5 , " & -- SP6_TXD[21]
"AC4 , " & -- SP6_TXD[20]
"AC3 , " & -- SP6_TXD[19]
"AC2 , " & -- SP6_TXD[18]
"AC1 , " & -- SP6_TXD[17]
"AB5 , " & -- SP6_TXD[16]
"AA5 , " & -- SP6_TXD[15]
"AA4 , " & -- SP6_TXD[14]
"AA2 , " & -- SP6_TXD[13]
"AA1 , " & -- SP6_TXD[12]
"Y5 , " & -- SP6_TXD[11]
"Y4 , " & -- SP6_TXD[10]
"Y3 , " & -- SP6_TXD[9]
"Y2 , " & -- SP6_TXD[8]
"W5 , " & -- SP6_TXD[7]
"W3 , " & -- SP6_TXD[6]
"W1 , " & -- SP6_TXD[5]
"V5 , " & -- SP6_TXD[4]
"V4 , " & -- SP6_TXD[3]
"V3 , " & -- SP6_TXD[2]
"V2 , " & -- SP6_TXD[1]
"V1 ), " & -- SP6_TXD[0]
"SP6_RX_ERROR : U5 , " &
"SP6_TXCTL :(AF4 , " & -- SP6_TXCTL[3]
"AD3 , " & -- SP6_TXCTL[2]
"AB1 , " & -- SP6_TXCTL[1]
"Y1 ), " & -- SP6_TXCTL[0]
"SP6_TXCLK : AA3 , " &
"SP6_PHY_DISABLE : AF5 , " &
"SP0_MODE_SEL : M26 , " &
"SP2_MODE_SEL : M25 , " &
"MCES : M24 , " &
"SPARE :(M23 , " & -- SPARE[1]
"M22 ), " & -- SPARE[0]
"SP4_MODE_SEL : L26 , " &
"SP6_MODE_SEL : L25 , " &
"SP6_PWRDN : L24 , " &
"SP1_PWRDN : L23 , " &
"SP2_PWRDN : L22 , " &
"SP3_PWRDN : K26 , " &
"SP4_PWRDN : K24 , " &
"SP_IO_SPEED :(J25 , " & -- SP_IO_SPEED[1]
"J26 ), " & -- SP_IO_SPEED[0]
"SP5_PWRDN : K22 , " &
"SP_MAST_EN : H26 , " &
"SP_RX_SWAP : J24 , " &
"SP_TX_SWAP : J23 , " &
"SP_HOST : H25 , " &
"SP_CLK_SEL :(H24 , " & -- SP_CLK_SEL[1]
"H23 ), " & -- SP_CLK_SEL[0]
"CHIP_RST_b : G26 , " &
"BCE : F26 , " &
"RST_IRQ_b : G24 , " &
"SPY_CLK_1 : F25 , " &
"INT_b : H22 , " &
"TCK : E26 , " &
"SPY_CLK_2 : F24 , " &
"TDI : D26 , " &
"BLK_RST_b : G22 , " &
"TDO : E25 , " &
"DO : F23 , " &
"TMS : E24 , " &
"I2C_SA :(B22 , " & -- I2C_SA[6]
"A26 , " & -- I2C_SA[5]
"B24 , " & -- I2C_SA[4]
"C22 , " & -- I2C_SA[3]
"A25 , " & -- I2C_SA[2]
"E23 , " & -- I2C_SA[1]
"C25 ), " & -- I2C_SA[0]
"TRST_b : D24 , " &
"DI : F22 , " &
"I2C_SD : C24 , " &
"I2C_MA : E22 , " &
"I2C_SCLK : C23 , " &
"I2C_SEL : D22 , " &
"I2C_DISABLE : E21 , " &
"PCI_PLL_BYPASS : D21 , " &
"PCI_INTDn : E20 , " &
"PCI_HOLD_BOOT : C21 , " &
"I2C_SLAVE : A22 , " &
"PCI_CLK : B21 , " &
"PCI_CLKO :(E19 , " & -- PCI_CLKO[4]
"D19 , " & -- PCI_CLKO[3]
"C18 , " & -- PCI_CLKO[2]
"B18 , " & -- PCI_CLKO[1]
"A21 ), " & -- PCI_CLKO[0]
"PCI_RSTDIR : C20 , " &
"PCI_ARBEN : A20 , " &
"PCI_INTCn : C19 , " &
"PCI_GNTn :(E18 , " & -- PCI_GNTn[4]
"D18 , " & -- PCI_GNTn[3]
"E17 , " & -- PCI_GNTn[2]
"A17 ), " & -- PCI_GNTn[1]
"PCI_INTAn : B19 , " &
"PCI_INTBn : A19 , " &
"PCI_RSTn : A18 , " &
"PCI_REQn :(E16 , " & -- PCI_REQn[4]
"D16 , " & -- PCI_REQn[3]
"C16 , " & -- PCI_REQn[2]
"C17 ), " & -- PCI_REQn[1]
"PCI_AD :(D15 , " & -- PCI_AD[31]
"B16 , " & -- PCI_AD[30]
"C15 , " & -- PCI_AD[29]
"A15 , " & -- PCI_AD[28]
"E14 , " & -- PCI_AD[27]
"B15 , " & -- PCI_AD[26]
"E15 , " & -- PCI_AD[25]
"A14 , " & -- PCI_AD[24]
"C13 , " & -- PCI_AD[23]
"A13 , " & -- PCI_AD[22]
"C12 , " & -- PCI_AD[21]
"B13 , " & -- PCI_AD[20]
"E13 , " & -- PCI_AD[19]
"A12 , " & -- PCI_AD[18]
"E12 , " & -- PCI_AD[17]
"B12 , " & -- PCI_AD[16]
"A9 , " & -- PCI_AD[15]
"C10 , " & -- PCI_AD[14]
"B9 , " & -- PCI_AD[13]
"C9 , " & -- PCI_AD[12]
"A8 , " & -- PCI_AD[11]
"E7 , " & -- PCI_AD[10]
"C8 , " & -- PCI_AD[9]
"D7 , " & -- PCI_AD[8]
"C7 , " & -- PCI_AD[7]
"B7 , " & -- PCI_AD[6]
"C6 , " & -- PCI_AD[5]
"A6 , " & -- PCI_AD[4]
"E6 , " & -- PCI_AD[3]
"B6 , " & -- PCI_AD[2]
"D6 , " & -- PCI_AD[1]
"A5 ), " & -- PCI_AD[0]
"PCI_PMEn : A16 , " &
"PCI_IDSEL : C14 , " &
"PCI_CBEn :(D13 , " & -- PCI_CBEn[3]
"E11 , " & -- PCI_CBEn[2]
"D9 , " & -- PCI_CBEn[1]
"A7 ), " & -- PCI_CBEn[0]
"PCI_IRDYn : D12 , " &
"PCI_FRAMEn : A11 , " &
"PCI_TRDYn : C11 , " &
"PCI_PAR : B10 , " &
"PCI_STOPn : A10 , " &
"PCI_DEVSELn : D10 , " &
"PCI_PERRn : E10 , " &
"PCI_SERRn : E9 , " &
"PCI_M66EN : E8 , " &
"S_CLK_p : AE23 , " &
"S_CLK_n : AD23 , " &
"TCK2_p : AE25 , " &
"TCK2_n : AD25 , " &
"PCI_PLL_AVDD : C26 , " &
"PCI_PLL_AVSS : B26 , " &
"CLKGEN_PLL_AVDD : A24 , " &
"CLKGEN_PLL_AVSS : A23 , " &
"VDD_PCI :(N20 , " & -- VDD_PCI[23]
"J22 , " & -- VDD_PCI[22]
"M21 , " & -- VDD_PCI[21]
"L20 , " & -- VDD_PCI[20]
"K21 , " & -- VDD_PCI[19]
"J20 , " & -- VDD_PCI[18]
"H21 , " & -- VDD_PCI[17]
"H7 , " & -- VDD_PCI[16]
"G20 , " & -- VDD_PCI[15]
"G18 , " & -- VDD_PCI[14]
"G16 , " & -- VDD_PCI[13]
"G14 , " & -- VDD_PCI[12]
"G12 , " & -- VDD_PCI[11]
"G10 , " & -- VDD_PCI[10]
"G8 , " & -- VDD_PCI[9]
"G6 , " & -- VDD_PCI[8]
"F21 , " & -- VDD_PCI[7]
"F19 , " & -- VDD_PCI[6]
"F17 , " & -- VDD_PCI[5]
"F15 , " & -- VDD_PCI[4]
"F13 , " & -- VDD_PCI[3]
"F11 , " & -- VDD_PCI[2]
"F9 , " & -- VDD_PCI[1]
"F7 ), " & -- VDD_PCI[0]
"VSS_IO :(AE4 , " & -- VSS_IO[63]
"AE2 , " & -- VSS_IO[62]
"AB4 , " & -- VSS_IO[61]
"AB2 , " & -- VSS_IO[60]
"W4 , " & -- VSS_IO[59]
"W2 , " & -- VSS_IO[58]
"V6 , " & -- VSS_IO[57]
"U7 , " & -- VSS_IO[56]
"T6 , " & -- VSS_IO[55]
"T4 , " & -- VSS_IO[54]
"T2 , " & -- VSS_IO[53]
"R7 , " & -- VSS_IO[52]
"P6 , " & -- VSS_IO[51]
"N7 , " & -- VSS_IO[50]
"N4 , " & -- VSS_IO[49]
"N2 , " & -- VSS_IO[48]
"M20 , " & -- VSS_IO[47]
"M6 , " & -- VSS_IO[46]
"L21 , " & -- VSS_IO[45]
"L7 , " & -- VSS_IO[44]
"K25 , " & -- VSS_IO[43]
"K23 , " & -- VSS_IO[42]
"K20 , " & -- VSS_IO[41]
"K6 , " & -- VSS_IO[40]
"K4 , " & -- VSS_IO[39]
"K2 , " & -- VSS_IO[38]
"J21 , " & -- VSS_IO[37]
"J7 , " & -- VSS_IO[36]
"H20 , " & -- VSS_IO[35]
"H6 , " & -- VSS_IO[34]
"G23 , " & -- VSS_IO[33]
"G21 , " & -- VSS_IO[32]
"G19 , " & -- VSS_IO[31]
"G17 , " & -- VSS_IO[30]
"G15 , " & -- VSS_IO[29]
"G13 , " & -- VSS_IO[28]
"G11 , " & -- VSS_IO[27]
"G9 , " & -- VSS_IO[26]
"G7 , " & -- VSS_IO[25]
"G4 , " & -- VSS_IO[24]
"G2 , " & -- VSS_IO[23]
"F20 , " & -- VSS_IO[22]
"F18 , " & -- VSS_IO[21]
"F16 , " & -- VSS_IO[20]
"F14 , " & -- VSS_IO[19]
"F12 , " & -- VSS_IO[18]
"F10 , " & -- VSS_IO[17]
"F8 , " & -- VSS_IO[16]
"F6 , " & -- VSS_IO[15]
"D25 , " & -- VSS_IO[14]
"D20 , " & -- VSS_IO[13]
"D17 , " & -- VSS_IO[12]
"D14 , " & -- VSS_IO[11]
"D11 , " & -- VSS_IO[10]
"D8 , " & -- VSS_IO[9]
"D2 , " & -- VSS_IO[8]
"B25 , " & -- VSS_IO[7]
"B23 , " & -- VSS_IO[6]
"B20 , " & -- VSS_IO[5]
"B17 , " & -- VSS_IO[4]
"B14 , " & -- VSS_IO[3]
"B11 , " & -- VSS_IO[2]
"B8 , " & -- VSS_IO[1]
"B5 ), " & -- VSS_IO[0]
"VDD_HSTL :(W6 , " & -- VDD_HSTL[10]
"V7 , " & -- VDD_HSTL[9]
"U6 , " & -- VDD_HSTL[8]
"T7 , " & -- VDD_HSTL[7]
"R6 , " & -- VDD_HSTL[6]
"P7 , " & -- VDD_HSTL[5]
"N6 , " & -- VDD_HSTL[4]
"M7 , " & -- VDD_HSTL[3]
"L6 , " & -- VDD_HSTL[2]
"K7 , " & -- VDD_HSTL[1]
"J6 ), " & -- VDD_HSTL[0]
"SP_AVDD :(W19 , " & -- SP_AVDD[14]
"Y17 , " & -- SP_AVDD[13]
"Y13 , " & -- SP_AVDD[12]
"Y9 , " & -- SP_AVDD[11]
"W18 , " & -- SP_AVDD[10]
"W16 , " & -- SP_AVDD[9]
"W15 , " & -- SP_AVDD[8]
"W14 , " & -- SP_AVDD[7]
"W12 , " & -- SP_AVDD[6]
"W11 , " & -- SP_AVDD[5]
"W10 , " & -- SP_AVDD[4]
"V19 , " & -- SP_AVDD[3]
"U19 , " & -- SP_AVDD[2]
"T20 , " & -- SP_AVDD[1]
"R19 ), " & -- SP_AVDD[0]
"SP_VDD :(AF24 , " & -- SP_VDD[39]
"AE20 , " & -- SP_VDD[38]
"AE18 , " & -- SP_VDD[37]
"AE16 , " & -- SP_VDD[36]
"AE14 , " & -- SP_VDD[35]
"AE12 , " & -- SP_VDD[34]
"AE10 , " & -- SP_VDD[33]
"AE8 , " & -- SP_VDD[32]
"AD21 , " & -- SP_VDD[31]
"AD19 , " & -- SP_VDD[30]
"AD17 , " & -- SP_VDD[29]
"AD15 , " & -- SP_VDD[28]
"AD13 , " & -- SP_VDD[27]
"AD11 , " & -- SP_VDD[26]
"AD9 , " & -- SP_VDD[25]
"AD7 , " & -- SP_VDD[24]
"AC24 , " & -- SP_VDD[23]
"AB20 , " & -- SP_VDD[22]
"AB18 , " & -- SP_VDD[21]
"AB16 , " & -- SP_VDD[20]
"AB14 , " & -- SP_VDD[19]
"AB12 , " & -- SP_VDD[18]
"AB10 , " & -- SP_VDD[17]
"AB8 , " & -- SP_VDD[16]
"AA19 , " & -- SP_VDD[15]
"AA15 , " & -- SP_VDD[14]
"AA11 , " & -- SP_VDD[13]
"AA7 , " & -- SP_VDD[12]
"Y24 , " & -- SP_VDD[11]
"W25 , " & -- SP_VDD[10]
"W22 , " & -- SP_VDD[9]
"V24 , " & -- SP_VDD[8]
"V21 , " & -- SP_VDD[7]
"U25 , " & -- SP_VDD[6]
"U22 , " & -- SP_VDD[5]
"T24 , " & -- SP_VDD[4]
"R25 , " & -- SP_VDD[3]
"R22 , " & -- SP_VDD[2]
"P24 , " & -- SP_VDD[1]
"P21 ), " & -- SP_VDD[0]
"VDD :(W8 , " & -- VDD[45]
"V16 , " & -- VDD[44]
"V14 , " & -- VDD[43]
"V12 , " & -- VDD[42]
"V10 , " & -- VDD[41]
"V8 , " & -- VDD[40]
"U18 , " & -- VDD[39]
"U9 , " & -- VDD[38]
"U8 , " & -- VDD[37]
"T8 , " & -- VDD[36]
"R18 , " & -- VDD[35]
"R9 , " & -- VDD[34]
"R8 , " & -- VDD[33]
"P19 , " & -- VDD[32]
"P8 , " & -- VDD[31]
"N19 , " & -- VDD[30]
"N18 , " & -- VDD[29]
"N9 , " & -- VDD[28]
"N8 , " & -- VDD[27]
"M19 , " & -- VDD[26]
"M8 , " & -- VDD[25]
"L19 , " & -- VDD[24]
"L18 , " & -- VDD[23]
"L9 , " & -- VDD[22]
"L8 , " & -- VDD[21]
"K19 , " & -- VDD[20]
"K8 , " & -- VDD[19]
"J19 , " & -- VDD[18]
"J17 , " & -- VDD[17]
"J15 , " & -- VDD[16]
"J13 , " & -- VDD[15]
"J11 , " & -- VDD[14]
"J9 , " & -- VDD[13]
"J8 , " & -- VDD[12]
"H19 , " & -- VDD[11]
"H18 , " & -- VDD[10]
"H17 , " & -- VDD[9]
"H16 , " & -- VDD[8]
"H15 , " & -- VDD[7]
"H14 , " & -- VDD[6]
"H13 , " & -- VDD[5]
"H12 , " & -- VDD[4]
"H11 , " & -- VDD[3]
"H10 , " & -- VDD[2]
"H9 , " & -- VDD[1]
"H8 ), " & -- VDD[0]
"VSS :(AF26 , " & -- VSS[177]
"AF25 , " & -- VSS[176]
"AF23 , " & -- VSS[175]
"AF22 , " & -- VSS[174]
"AF20 , " & -- VSS[173]
"AF18 , " & -- VSS[172]
"AF16 , " & -- VSS[171]
"AF14 , " & -- VSS[170]
"AF12 , " & -- VSS[169]
"AF10 , " & -- VSS[168]
"AF8 , " & -- VSS[167]
"AF6 , " & -- VSS[166]
"AE26 , " & -- VSS[165]
"AE24 , " & -- VSS[164]
"AE22 , " & -- VSS[163]
"AE6 , " & -- VSS[162]
"AD26 , " & -- VSS[161]
"AD24 , " & -- VSS[160]
"AD22 , " & -- VSS[159]
"AD20 , " & -- VSS[158]
"AD18 , " & -- VSS[157]
"AD16 , " & -- VSS[156]
"AD14 , " & -- VSS[155]
"AD12 , " & -- VSS[154]
"AD10 , " & -- VSS[153]
"AD8 , " & -- VSS[152]
"AD6 , " & -- VSS[151]
"AC26 , " & -- VSS[150]
"AC25 , " & -- VSS[149]
"AC23 , " & -- VSS[148]
"AC22 , " & -- VSS[147]
"AC20 , " & -- VSS[146]
"AC16 , " & -- VSS[145]
"AC14 , " & -- VSS[144]
"AC12 , " & -- VSS[143]
"AC8 , " & -- VSS[142]
"AB26 , " & -- VSS[141]
"AB25 , " & -- VSS[140]
"AB24 , " & -- VSS[139]
"AB23 , " & -- VSS[138]
"AB22 , " & -- VSS[137]
"AA26 , " & -- VSS[136]
"AA25 , " & -- VSS[135]
"AA24 , " & -- VSS[134]
"AA23 , " & -- VSS[133]
"AA22 , " & -- VSS[132]
"AA21 , " & -- VSS[131]
"AA20 , " & -- VSS[130]
"AA18 , " & -- VSS[129]
"AA17 , " & -- VSS[128]
"AA16 , " & -- VSS[127]
"AA14 , " & -- VSS[126]
"AA13 , " & -- VSS[125]
"AA12 , " & -- VSS[124]
"AA10 , " & -- VSS[123]
"AA9 , " & -- VSS[122]
"AA8 , " & -- VSS[121]
"Y21 , " & -- VSS[120]
"Y20 , " & -- VSS[119]
"Y19 , " & -- VSS[118]
"Y18 , " & -- VSS[117]
"Y16 , " & -- VSS[116]
"Y15 , " & -- VSS[115]
"Y14 , " & -- VSS[114]
"Y12 , " & -- VSS[113]
"Y11 , " & -- VSS[112]
"Y10 , " & -- VSS[111]
"Y8 , " & -- VSS[110]
"W26 , " & -- VSS[109]
"W24 , " & -- VSS[108]
"W23 , " & -- VSS[107]
"W21 , " & -- VSS[106]
"W20 , " & -- VSS[105]
"W17 , " & -- VSS[104]
"W13 , " & -- VSS[103]
"W9 , " & -- VSS[102]
"L17 , " & -- VSS[101]
"V20 , " & -- VSS[100]
"V18 , " & -- VSS[99]
"V17 , " & -- VSS[98]
"V15 , " & -- VSS[97]
"V13 , " & -- VSS[96]
"V11 , " & -- VSS[95]
"V9 , " & -- VSS[94]
"U26 , " & -- VSS[93]
"U24 , " & -- VSS[92]
"U21 , " & -- VSS[91]
"U20 , " & -- VSS[90]
"U17 , " & -- VSS[89]
"U16 , " & -- VSS[88]
"U15 , " & -- VSS[87]
"U14 , " & -- VSS[86]
"U13 , " & -- VSS[85]
"U12 , " & -- VSS[84]
"U11 , " & -- VSS[83]
"U10 , " & -- VSS[82]
"T21 , " & -- VSS[81]
"T19 , " & -- VSS[80]
"T18 , " & -- VSS[79]
"T17 , " & -- VSS[78]
"T16 , " & -- VSS[77]
"T15 , " & -- VSS[76]
"T14 , " & -- VSS[75]
"T13 , " & -- VSS[74]
"T12 , " & -- VSS[73]
"T11 , " & -- VSS[72]
"T10 , " & -- VSS[71]
"T9 , " & -- VSS[70]
"R26 , " & -- VSS[69]
"R24 , " & -- VSS[68]
"R23 , " & -- VSS[67]
"R21 , " & -- VSS[66]
"R20 , " & -- VSS[65]
"R17 , " & -- VSS[64]
"R16 , " & -- VSS[63]
"R15 , " & -- VSS[62]
"R14 , " & -- VSS[61]
"R13 , " & -- VSS[60]
"R12 , " & -- VSS[59]
"R11 , " & -- VSS[58]
"R10 , " & -- VSS[57]
"P20 , " & -- VSS[56]
"P18 , " & -- VSS[55]
"P17 , " & -- VSS[54]
"P16 , " & -- VSS[53]
"P15 , " & -- VSS[52]
"P14 , " & -- VSS[51]
"P13 , " & -- VSS[50]
"P12 , " & -- VSS[49]
"P11 , " & -- VSS[48]
"P10 , " & -- VSS[47]
"P9 , " & -- VSS[46]
"N26 , " & -- VSS[45]
"N25 , " & -- VSS[44]
"N24 , " & -- VSS[43]
"N23 , " & -- VSS[42]
"N22 , " & -- VSS[41]
"N21 , " & -- VSS[40]
"N17 , " & -- VSS[39]
"N16 , " & -- VSS[38]
"N15 , " & -- VSS[37]
"N14 , " & -- VSS[36]
"N13 , " & -- VSS[35]
"N12 , " & -- VSS[34]
"N11 , " & -- VSS[33]
"N10 , " & -- VSS[32]
"M18 , " & -- VSS[31]
"M17 , " & -- VSS[30]
"M16 , " & -- VSS[29]
"M15 , " & -- VSS[28]
"M14 , " & -- VSS[27]
"M13 , " & -- VSS[26]
"M12 , " & -- VSS[25]
"M11 , " & -- VSS[24]
"M10 , " & -- VSS[23]
"M9 , " & -- VSS[22]
"L16 , " & -- VSS[21]
"L15 , " & -- VSS[20]
"L14 , " & -- VSS[19]
"L13 , " & -- VSS[18]
"L12 , " & -- VSS[17]
"L11 , " & -- VSS[16]
"L10 , " & -- VSS[15]
"K18 , " & -- VSS[14]
"K17 , " & -- VSS[13]
"K16 , " & -- VSS[12]
"K15 , " & -- VSS[11]
"K14 , " & -- VSS[10]
"K13 , " & -- VSS[9]
"K12 , " & -- VSS[8]
"K11 , " & -- VSS[7]
"K10 , " & -- VSS[6]
"K9 , " & -- VSS[5]
"J18 , " & -- VSS[4]
"J16 , " & -- VSS[3]
"J14 , " & -- VSS[2]
"J12 , " & -- VSS[1]
"J10 ), " & -- VSS[0]
"NC_SP6_TA_p : 328 , " &
"NC_SP6_TA_n : 329 , " &
"NC_SP0_REFCLK_p : 330 , " &
"NC_SP0_REFCLK_n : 331 , " &
"NC_SP2_REFCLK_p : 332 , " &
"NC_SP2_REFCLK_n : 333 , " &
"NC_SP4_REFCLK_p : 334 , " &
"NC_SP4_REFCLK_n : 335 , " &
"NC_SP6_RA_p : 336 , " &
"NC_SP6_RA_n : 337 , " &
"NC_SP6_REXT : 338 , " &
"NC_SP6_REFCLK_n : 339 , " &
"NC_SP6_REFCLK_p : 340 " ;
attribute PORT_GROUPING of Tsi620 : entity is
"Differential_Current ( (SP4_TB_p, SP4_TB_n), " &
"(SP4_RB_p, SP4_RB_n), " &
"(SP4_TA_p, SP4_TA_n), " &
"(SP4_RA_p, SP4_RA_n), " &
"(SP4_TC_p, SP4_TC_n), " &
"(SP4_RC_p, SP4_RC_n), " &
"(SP4_TD_p, SP4_TD_n), " &
"(SP4_RD_p, SP4_RD_n), " &
"(SP2_TB_p, SP2_TB_n), " &
"(SP2_RB_p, SP2_RB_n), " &
"(SP2_TA_p, SP2_TA_n), " &
"(SP2_RA_p, SP2_RA_n), " &
"(SP2_TC_p, SP2_TC_n), " &
"(SP2_RC_p, SP2_RC_n), " &
"(SP2_TD_p, SP2_TD_n), " &
"(SP2_RD_p, SP2_RD_n), " &
"(SP0_TB_p, SP0_TB_n), " &
"(SP0_RB_p, SP0_RB_n), " &
"(SP0_TA_p, SP0_TA_n), " &
"(SP0_RA_p, SP0_RA_n), " &
"(SP0_TC_p, SP0_TC_n), " &
"(SP0_RC_p, SP0_RC_n), " &
"(SP0_TD_p, SP0_TD_n), " &
"(SP0_RD_p, SP0_RD_n)) " ;
attribute TAP_SCAN_RESET of TRST_b : signal is true;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (1.0000000000000000000e+07, BOTH);
attribute COMPLIANCE_PATTERNS of Tsi620 : entity is
"(BCE) (1)";
attribute INSTRUCTION_LENGTH of Tsi620: entity is 123;
attribute INSTRUCTION_OPCODE of Tsi620: entity is
"IDCODE (111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110)," &
"BYPASS (000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111)," &
"EXTEST (111111111111111111111111111111111111111111111111111111111111111111111111111111111100000011100101111111111111111111111101000)," &
"EXTEST_PULSE (111111111111111111111111111111111111111111111111111111111111111111111111111111111100000011100101111111111101111111111101000)," &
"EXTEST_TRAIN (111111111111111111111111111111111111111111111111111111111111111111111111111111111100000011100101111111111011111111111101000)," &
"SAMPLE (111111111111111111111111111111111111111111111111111111111111111111111111111111111100000011100101111111111111111111111111000)," &
"PRELOAD (111111111111111111111111111111111111111111111111111111111111111111111111111111111100000011100101111111111111111111111111000)," &
"CLAMP (111111111111111111111111111111111111111111111111111111111111111111111111111111111100000011100101111111111111111111111101111) " ;
attribute INSTRUCTION_CAPTURE of Tsi620: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01";
attribute IDCODE_REGISTER of Tsi620: entity is
"0000" & -- version
"0000011000100000" & -- part number
"00010110011" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of Tsi620: entity is
"BOUNDARY ( EXTEST_PULSE, EXTEST_TRAIN )," &
"BOUNDARY ( SAMPLE, PRELOAD )," &
"BYPASS ( CLAMP, BYPASS ) " ;
--Boundary scan definition
attribute BOUNDARY_LENGTH of Tsi620: entity is 439;
attribute BOUNDARY_REGISTER of Tsi620: entity is
-- num cell port function safe [ccell disval rslt]
" 438 (BC_1 , * , control , 0 ) ,"&
" 437 (AC_1 , SP4_TB_p , output3 , X , 438 , 0 , Z ),"&
" 436 (BC_4 , SP4_RB_p , observe_only , X ) ,"&
" 435 (BC_4 , SP4_RB_n , observe_only , X ) ,"&
" 434 (BC_1 , * , control , 0 ) ,"&
" 433 (AC_1 , SP4_TA_p , output3 , X , 434 , 0 , Z ),"&
" 432 (BC_4 , SP4_RA_p , observe_only , X ) ,"&
" 431 (BC_4 , SP4_RA_n , observe_only , X ) ,"&
" 430 (BC_1 , * , control , 0 ) ,"&
" 429 (AC_1 , SP4_TC_p , output3 , X , 430 , 0 , Z ),"&
" 428 (BC_4 , SP4_RC_p , observe_only , X ) ,"&
" 427 (BC_4 , SP4_RC_n , observe_only , X ) ,"&
" 426 (BC_1 , * , control , 0 ) ,"&
" 425 (AC_1 , SP4_TD_p , output3 , X , 426 , 0 , Z ),"&
" 424 (BC_4 , SP4_RD_p , observe_only , X ) ,"&
" 423 (BC_4 , SP4_RD_n , observe_only , X ) ,"&
" 422 (BC_1 , * , control , 0 ) ,"&
" 421 (AC_1 , SP2_TB_p , output3 , X , 422 , 0 , Z ),"&
" 420 (BC_4 , SP2_RB_p , observe_only , X ) ,"&
" 419 (BC_4 , SP2_RB_n , observe_only , X ) ,"&
" 418 (BC_1 , * , control , 0 ) ,"&
" 417 (AC_1 , SP2_TA_p , output3 , X , 418 , 0 , Z ),"&
" 416 (BC_4 , SP2_RA_p , observe_only , X ) ,"&
" 415 (BC_4 , SP2_RA_n , observe_only , X ) ,"&
" 414 (BC_1 , * , control , 0 ) ,"&
" 413 (AC_1 , SP2_TC_p , output3 , X , 414 , 0 , Z ),"&
" 412 (BC_4 , SP2_RC_p , observe_only , X ) ,"&
" 411 (BC_4 , SP2_RC_n , observe_only , X ) ,"&
" 410 (BC_1 , * , control , 0 ) ,"&
" 409 (AC_1 , SP2_TD_p , output3 , X , 410 , 0 , Z ),"&
" 408 (BC_4 , SP2_RD_p , observe_only , X ) ,"&
" 407 (BC_4 , SP2_RD_n , observe_only , X ) ,"&
" 406 (BC_1 , * , control , 0 ) ,"&
" 405 (AC_1 , SP0_TB_p , output3 , X , 406 , 0 , Z ),"&
" 404 (BC_4 , SP0_RB_p , observe_only , X ) ,"&
" 403 (BC_4 , SP0_RB_n , observe_only , X ) ,"&
" 402 (BC_1 , * , control , 0 ) ,"&
" 401 (AC_1 , SP0_TA_p , output3 , X , 402 , 0 , Z ),"&
" 400 (BC_4 , SP0_RA_p , observe_only , X ) ,"&
" 399 (BC_4 , SP0_RA_n , observe_only , X ) ,"&
" 398 (BC_1 , * , control , 0 ) ,"&
" 397 (AC_1 , SP0_TC_p , output3 , X , 398 , 0 , Z ),"&
" 396 (BC_4 , SP0_RC_p , observe_only , X ) ,"&
" 395 (BC_4 , SP0_RC_n , observe_only , X ) ,"&
" 394 (BC_1 , * , control , 0 ) ,"&
" 393 (AC_1 , SP0_TD_p , output3 , X , 394 , 0 , Z ),"&
" 392 (BC_4 , SP0_RD_p , observe_only , X ) ,"&
" 391 (BC_4 , SP0_RD_n , observe_only , X ) ,"&
" 390 (BC_2 , * , control , 0 ) ,"&
" 389 (LV_BC_7 , GPIO(11) , bidir , X , 390 , 0 , Z ),"&
" 388 (BC_2 , * , control , 0 ) ,"&
" 387 (LV_BC_7 , GPIO(15) , bidir , X , 388 , 0 , Z ),"&
" 386 (BC_2 , * , control , 0 ) ,"&
" 385 (LV_BC_7 , GPIO(14) , bidir , X , 386 , 0 , Z ),"&
" 384 (BC_2 , * , control , 0 ) ,"&
" 383 (LV_BC_7 , GPIO(21) , bidir , X , 384 , 0 , Z ),"&
" 382 (BC_2 , * , control , 0 ) ,"&
" 381 (LV_BC_7 , GPIO(31) , bidir , X , 382 , 0 , Z ),"&
" 380 (BC_2 , * , control , 0 ) ,"&
" 379 (LV_BC_7 , GPIO(20) , bidir , X , 380 , 0 , Z ),"&
" 378 (BC_2 , * , control , 0 ) ,"&
" 377 (LV_BC_7 , GPIO(25) , bidir , X , 378 , 0 , Z ),"&
" 376 (BC_2 , * , control , 0 ) ,"&
" 375 (LV_BC_7 , GPIO(19) , bidir , X , 376 , 0 , Z ),"&
" 374 (BC_2 , * , control , 0 ) ,"&
" 373 (LV_BC_7 , GPIO(24) , bidir , X , 374 , 0 , Z ),"&
" 372 (BC_2 , * , control , 0 ) ,"&
" 371 (LV_BC_7 , GPIO(30) , bidir , X , 372 , 0 , Z ),"&
" 370 (BC_2 , * , control , 0 ) ,"&
" 369 (LV_BC_7 , GPIO(29) , bidir , X , 370 , 0 , Z ),"&
" 368 (BC_2 , * , control , 0 ) ,"&
" 367 (LV_BC_7 , GPIO(28) , bidir , X , 368 , 0 , Z ),"&
" 366 (BC_2 , * , control , 0 ) ,"&
" 365 (LV_BC_7 , GPIO(27) , bidir , X , 366 , 0 , Z ),"&
" 364 (BC_2 , * , control , 1 ) ,"&
" 363 (LV_BC_7 , SP6_RXD(4) , bidir , X , 364 , 1 , Z ),"&
" 362 (BC_2 , * , control , 1 ) ,"&
" 361 (LV_BC_7 , SP6_RXD(3) , bidir , X , 362 , 1 , Z ),"&
" 360 (BC_2 , * , control , 1 ) ,"&
" 359 (LV_BC_7 , SP6_RXD(2) , bidir , X , 360 , 1 , Z ),"&
" 358 (BC_2 , * , control , 1 ) ,"&
" 357 (LV_BC_7 , SP6_RXD(1) , bidir , X , 358 , 1 , Z ),"&
" 356 (BC_2 , * , control , 1 ) ,"&
" 355 (LV_BC_7 , SP6_RXD(0) , bidir , X , 356 , 1 , Z ),"&
" 354 (BC_2 , * , control , 1 ) ,"&
" 353 (LV_BC_7 , SP6_RXD(7) , bidir , X , 354 , 1 , Z ),"&
" 352 (BC_2 , * , control , 1 ) ,"&
" 351 (LV_BC_7 , SP6_RXD(6) , bidir , X , 352 , 1 , Z ),"&
" 350 (BC_2 , * , control , 1 ) ,"&
" 349 (LV_BC_7 , SP6_RXD(5) , bidir , X , 350 , 1 , Z ),"&
" 348 (BC_2 , * , control , 1 ) ,"&
" 347 (LV_BC_7 , SP6_RXD(11) , bidir , X , 348 , 1 , Z ),"&
" 346 (BC_2 , * , control , 1 ) ,"&
" 345 (LV_BC_7 , SP6_RXD(10) , bidir , X , 346 , 1 , Z ),"&
" 344 (BC_2 , * , control , 1 ) ,"&
" 343 (LV_BC_7 , SP6_RXD(9) , bidir , X , 344 , 1 , Z ),"&
" 342 (BC_2 , * , control , 1 ) ,"&
" 341 (LV_BC_7 , SP6_RXD(8) , bidir , X , 342 , 1 , Z ),"&
" 340 (BC_2 , * , control , 1 ) ,"&
" 339 (LV_BC_7 , SP6_RXCTL(0) , bidir , X , 340 , 1 , Z ),"&
" 338 (BC_2 , * , control , 1 ) ,"&
" 337 (LV_BC_7 , SP6_RXD(12) , bidir , X , 338 , 1 , Z ),"&
" 336 (BC_2 , * , control , 1 ) ,"&
" 335 (LV_BC_7 , SP6_RXD(13) , bidir , X , 336 , 1 , Z ),"&
" 334 (BC_2 , * , control , 1 ) ,"&
" 333 (LV_BC_7 , SP6_RXD(14) , bidir , X , 334 , 1 , Z ),"&
" 332 (BC_2 , * , control , 1 ) ,"&
" 331 (LV_BC_7 , SP6_RXD(15) , bidir , X , 332 , 1 , Z ),"&
" 330 (BC_2 , * , control , 1 ) ,"&
" 329 (LV_BC_7 , SP6_RXCTL(1) , bidir , X , 330 , 1 , Z ),"&
" 328 (BC_2 , * , control , 1 ) ,"&
" 327 (LV_BC_7 , SP6_RXD(16) , bidir , X , 328 , 1 , Z ),"&
" 326 (BC_2 , * , control , 1 ) ,"&
" 325 (LV_BC_7 , SP6_RXD(17) , bidir , X , 326 , 1 , Z ),"&
" 324 (BC_2 , * , control , 1 ) ,"&
" 323 (LV_BC_7 , SP6_RXCLK , bidir , X , 324 , 1 , Z ),"&
" 322 (BC_2 , * , control , 1 ) ,"&
" 321 (LV_BC_7 , SP6_RXD(18) , bidir , X , 322 , 1 , Z ),"&
" 320 (BC_2 , * , control , 1 ) ,"&
" 319 (LV_BC_7 , SP6_RXD(19) , bidir , X , 320 , 1 , Z ),"&
" 318 (BC_2 , * , control , 1 ) ,"&
" 317 (LV_BC_7 , SP6_RXD(20) , bidir , X , 318 , 1 , Z ),"&
" 316 (BC_2 , * , control , 1 ) ,"&
" 315 (LV_BC_7 , SP6_RXD(22) , bidir , X , 316 , 1 , Z ),"&
" 314 (BC_2 , * , control , 1 ) ,"&
" 313 (LV_BC_7 , SP6_RXD(21) , bidir , X , 314 , 1 , Z ),"&
" 312 (BC_2 , * , control , 1 ) ,"&
" 311 (LV_BC_7 , SP6_RXD(23) , bidir , X , 312 , 1 , Z ),"&
" 310 (BC_2 , * , control , 1 ) ,"&
" 309 (LV_BC_7 , SP6_RXCTL(2) , bidir , X , 310 , 1 , Z ),"&
" 308 (BC_2 , * , control , 1 ) ,"&
" 307 (LV_BC_7 , SP6_RXD(26) , bidir , X , 308 , 1 , Z ),"&
" 306 (BC_2 , * , control , 1 ) ,"&
" 305 (LV_BC_7 , SP6_RXD(24) , bidir , X , 306 , 1 , Z ),"&
" 304 (BC_2 , * , control , 1 ) ,"&
" 303 (LV_BC_7 , SP6_RXD(25) , bidir , X , 304 , 1 , Z ),"&
" 302 (BC_2 , * , control , 1 ) ,"&
" 301 (LV_BC_7 , SP6_RXD(27) , bidir , X , 302 , 1 , Z ),"&
" 300 (BC_2 , * , control , 1 ) ,"&
" 299 (LV_BC_7 , SP6_RXD(29) , bidir , X , 300 , 1 , Z ),"&
" 298 (BC_2 , * , control , 1 ) ,"&
" 297 (LV_BC_7 , SP6_RXD(30) , bidir , X , 298 , 1 , Z ),"&
" 296 (BC_2 , * , control , 1 ) ,"&
" 295 (BC_2 , SP6_TXD(0) , output3 , X , 296 , 1 , Z ),"&
" 294 (BC_2 , * , control , 1 ) ,"&
" 293 (LV_BC_7 , SP6_RXD(31) , bidir , X , 294 , 1 , Z ),"&
" 292 (BC_2 , * , control , 1 ) ,"&
" 291 (LV_BC_7 , SP6_RXD(28) , bidir , X , 292 , 1 , Z ),"&
" 290 (BC_2 , * , control , 1 ) ,"&
" 289 (BC_2 , SP6_TXD(1) , output3 , X , 290 , 1 , Z ),"&
" 288 (BC_2 , * , control , 1 ) ,"&
" 287 (LV_BC_7 , SP6_RXCTL(3) , bidir , X , 288 , 1 , Z ),"&
" 286 (BC_2 , * , control , 1 ) ,"&
" 285 (BC_2 , SP6_TXD(5) , output3 , X , 286 , 1 , Z ),"&
" 284 (BC_2 , * , control , 1 ) ,"&
" 283 (BC_2 , SP6_TXD(2) , output3 , X , 284 , 1 , Z ),"&
" 282 (BC_2 , * , control , 1 ) ,"&
" 281 (LV_BC_7 , SP6_RX_ERROR , bidir , X , 282 , 1 , Z ),"&
" 280 (BC_2 , * , control , 1 ) ,"&
" 279 (BC_2 , SP6_TXCTL(0) , output3 , X , 280 , 1 , Z ),"&
" 278 (BC_2 , * , control , 1 ) ,"&
" 277 (BC_2 , SP6_TXD(3) , output3 , X , 278 , 1 , Z ),"&
" 276 (BC_2 , * , control , 1 ) ,"&
" 275 (BC_2 , SP6_TXD(6) , output3 , X , 276 , 1 , Z ),"&
" 274 (BC_2 , * , control , 1 ) ,"&
" 273 (BC_2 , SP6_TXD(8) , output3 , X , 274 , 1 , Z ),"&
" 272 (BC_2 , * , control , 1 ) ,"&
" 271 (BC_2 , SP6_TXD(12) , output3 , X , 272 , 1 , Z ),"&
" 270 (BC_2 , * , control , 1 ) ,"&
" 269 (BC_2 , SP6_TXD(4) , output3 , X , 270 , 1 , Z ),"&
" 268 (BC_2 , * , control , 1 ) ,"&
" 267 (BC_2 , SP6_TXD(9) , output3 , X , 268 , 1 , Z ),"&
" 266 (BC_2 , * , control , 1 ) ,"&
" 265 (BC_2 , SP6_TXD(13) , output3 , X , 266 , 1 , Z ),"&
" 264 (BC_2 , * , control , 1 ) ,"&
" 263 (BC_2 , SP6_TXCTL(1) , output3 , X , 264 , 1 , Z ),"&
" 262 (BC_2 , * , control , 1 ) ,"&
" 261 (BC_2 , SP6_TXD(7) , output3 , X , 262 , 1 , Z ),"&
" 260 (BC_2 , * , control , 1 ) ,"&
" 259 (BC_2 , SP6_TXD(10) , output3 , X , 260 , 1 , Z ),"&
" 258 (BC_2 , * , control , 1 ) ,"&
" 257 (BC_2 , SP6_TXCLK , output3 , X , 258 , 1 , Z ),"&
" 256 (BC_2 , * , control , 1 ) ,"&
" 255 (BC_2 , SP6_TXD(17) , output3 , X , 256 , 1 , Z ),"&
" 254 (BC_2 , * , control , 1 ) ,"&
" 253 (BC_2 , SP6_TXD(22) , output3 , X , 254 , 1 , Z ),"&
" 252 (BC_2 , * , control , 1 ) ,"&
" 251 (BC_2 , SP6_TXD(14) , output3 , X , 252 , 1 , Z ),"&
" 250 (BC_2 , * , control , 1 ) ,"&
" 249 (BC_2 , SP6_TXD(11) , output3 , X , 250 , 1 , Z ),"&
" 248 (BC_2 , * , control , 1 ) ,"&
" 247 (BC_2 , SP6_TXD(18) , output3 , X , 248 , 1 , Z ),"&
" 246 (BC_2 , * , control , 1 ) ,"&
" 245 (BC_2 , SP6_TXD(26) , output3 , X , 246 , 1 , Z ),"&
" 244 (BC_2 , * , control , 1 ) ,"&
" 243 (BC_2 , SP6_TXD(23) , output3 , X , 244 , 1 , Z ),"&
" 242 (BC_2 , * , control , 1 ) ,"&
" 241 (BC_2 , SP6_TXD(19) , output3 , X , 242 , 1 , Z ),"&
" 240 (BC_2 , * , control , 1 ) ,"&
" 239 (BC_2 , SP6_TXD(15) , output3 , X , 240 , 1 , Z ),"&
" 238 (BC_2 , * , control , 1 ) ,"&
" 237 (BC_2 , SP6_TXD(29) , output3 , X , 238 , 1 , Z ),"&
" 236 (BC_2 , * , control , 1 ) ,"&
" 235 (BC_2 , SP6_TXCTL(2) , output3 , X , 236 , 1 , Z ),"&
" 234 (BC_2 , * , control , 1 ) ,"&
" 233 (BC_2 , SP6_TXD(20) , output3 , X , 234 , 1 , Z ),"&
" 232 (BC_2 , * , control , 1 ) ,"&
" 231 (BC_2 , SP6_TXD(16) , output3 , X , 232 , 1 , Z ),"&
" 230 (BC_2 , * , control , 1 ) ,"&
" 229 (BC_2 , SP6_TXD(30) , output3 , X , 230 , 1 , Z ),"&
" 228 (BC_2 , * , control , 1 ) ,"&
" 227 (BC_2 , SP6_TXD(27) , output3 , X , 228 , 1 , Z ),"&
" 226 (BC_2 , * , control , 1 ) ,"&
" 225 (BC_2 , SP6_TXD(24) , output3 , X , 226 , 1 , Z ),"&
" 224 (BC_2 , * , control , 1 ) ,"&
" 223 (BC_2 , SP6_TXD(21) , output3 , X , 224 , 1 , Z ),"&
" 222 (BC_2 , * , control , 1 ) ,"&
" 221 (BC_2 , SP6_TXD(31) , output3 , X , 222 , 1 , Z ),"&
" 220 (BC_2 , * , control , 1 ) ,"&
" 219 (BC_2 , SP6_TXD(25) , output3 , X , 220 , 1 , Z ),"&
" 218 (BC_2 , * , control , 1 ) ,"&
" 217 (BC_2 , SP6_TXCTL(3) , output3 , X , 218 , 1 , Z ),"&
" 216 (BC_2 , * , control , 1 ) ,"&
" 215 (BC_2 , SP6_TXD(28) , output3 , X , 216 , 1 , Z ),"&
" 214 (BC_2 , * , control , 1 ) ,"&
" 213 (BC_2 , SP6_PHY_DISABLE , output3 , X , 214 , 1 , Z ),"&
" 212 (BC_2 , * , control , 0 ) ,"&
" 211 (LV_BC_7 , SP0_MODE_SEL , bidir , X , 212 , 0 , Z ),"&
" 210 (LV_BC_7 , SP2_MODE_SEL , bidir , X , 212 , 0 , Z ),"&
" 209 (BC_2 , * , control , 0 ) ,"&
" 208 (LV_BC_7 , MCES , bidir , X , 209 , 0 , Z ),"&
" 207 (LV_BC_7 , SP4_MODE_SEL , bidir , X , 212 , 0 , Z ),"&
" 206 (LV_BC_7 , SP6_MODE_SEL , bidir , X , 212 , 0 , Z ),"&
" 205 (BC_2 , * , control , 0 ) ,"&
" 204 (LV_BC_7 , SP6_PWRDN , bidir , X , 205 , 0 , Z ),"&
" 203 (LV_BC_7 , SP1_PWRDN , bidir , X , 205 , 0 , Z ),"&
" 202 (LV_BC_7 , SP2_PWRDN , bidir , X , 205 , 0 , Z ),"&
" 201 (LV_BC_7 , SP3_PWRDN , bidir , X , 205 , 0 , Z ),"&
" 200 (BC_2 , * , control , 0 ) ,"&
" 199 (LV_BC_7 , SP4_PWRDN , bidir , X , 200 , 0 , Z ),"&
" 198 (LV_BC_7 , SP_IO_SPEED(1) , bidir , X , 200 , 0 , Z ),"&
" 197 (LV_BC_7 , SP_IO_SPEED(0) , bidir , X , 200 , 0 , Z ),"&
" 196 (LV_BC_7 , SP5_PWRDN , bidir , X , 200 , 0 , Z ),"&
" 195 (BC_2 , * , control , 0 ) ,"&
" 194 (LV_BC_7 , SP_MAST_EN , bidir , X , 195 , 0 , Z ),"&
" 193 (LV_BC_7 , SP_RX_SWAP , bidir , X , 195 , 0 , Z ),"&
" 192 (LV_BC_7 , SP_TX_SWAP , bidir , X , 195 , 0 , Z ),"&
" 191 (LV_BC_7 , SP_HOST , bidir , X , 195 , 0 , Z ),"&
" 190 (BC_2 , * , control , 0 ) ,"&
" 189 (LV_BC_7 , SP_CLK_SEL(1) , bidir , X , 190 , 0 , Z ),"&
" 188 (LV_BC_7 , SP_CLK_SEL(0) , bidir , X , 190 , 0 , Z ),"&
" 187 (BC_2 , * , control , 0 ) ,"&
" 186 (BC_2 , INT_b , output3 , X , 187 , 0 , Z ),"&
" 185 (BC_2 , BLK_RST_b , input , X ) ,"&
" 184 (BC_2 , * , control , 0 ) ,"&
" 183 (BC_2 , DO , output3 , X , 184 , 0 , Z ),"&
" 182 (BC_2 , I2C_SA(0) , input , X ) ,"&
" 181 (BC_2 , I2C_SA(1) , input , X ) ,"&
" 180 (BC_2 , I2C_SA(5) , input , X ) ,"&
" 179 (BC_2 , DI , input , X ) ,"&
" 178 (BC_2 , * , control , 0 ) ,"&
" 177 (LV_BC_7 , I2C_SD , bidir , X , 178 , 0 , Z ),"&
" 176 (BC_2 , I2C_SA(2) , input , X ) ,"&
" 175 (BC_2 , I2C_MA , input , X ) ,"&
" 174 (BC_2 , * , control , 0 ) ,"&
" 173 (LV_BC_7 , I2C_SCLK , bidir , X , 174 , 0 , Z ),"&
" 172 (BC_2 , I2C_SA(4) , input , X ) ,"&
" 171 (BC_2 , * , control , 0 ) ,"&
" 170 (LV_BC_7 , I2C_SEL , bidir , X , 171 , 0 , Z ),"&
" 169 (BC_2 , I2C_DISABLE , input , X ) ,"&
" 168 (BC_2 , I2C_SA(3) , input , X ) ,"&
" 167 (BC_2 , PCI_PLL_BYPASS , input , X ) ,"&
" 166 (BC_2 , * , control , 0 ) ,"&
" 165 (LV_BC_7 , PCI_INTDn , bidir , X , 166 , 0 , Z ),"&
" 164 (BC_2 , I2C_SA(6) , input , X ) ,"&
" 163 (BC_2 , PCI_HOLD_BOOT , input , X ) ,"&
" 162 (BC_2 , I2C_SLAVE , input , X ) ,"&
" 161 (BC_4 , PCI_CLK , clock , X ) ,"&
" 160 (BC_2 , * , control , 0 ) ,"&
" 159 (BC_2 , PCI_CLKO(4) , output3 , X , 160 , 0 , Z ),"&
" 158 (BC_2 , PCI_RSTDIR , input , X ) ,"&
" 157 (BC_2 , * , control , 0 ) ,"&
" 156 (BC_2 , PCI_CLKO(0) , output3 , X , 157 , 0 , Z ),"&
" 155 (BC_2 , PCI_ARBEN , input , X ) ,"&
" 154 (BC_2 , * , control , 0 ) ,"&
" 153 (BC_2 , PCI_CLKO(3) , output3 , X , 154 , 0 , Z ),"&
" 152 (BC_2 , * , control , 0 ) ,"&
" 151 (LV_BC_7 , PCI_INTCn , bidir , X , 152 , 0 , Z ),"&
" 150 (BC_2 , * , control , 0 ) ,"&
" 149 (LV_BC_7 , PCI_GNTn(3) , bidir , X , 150 , 0 , Z ),"&
" 148 (BC_2 , * , control , 0 ) ,"&
" 147 (LV_BC_7 , PCI_GNTn(2) , bidir , X , 148 , 0 , Z ),"&
" 146 (BC_2 , * , control , 0 ) ,"&
" 145 (LV_BC_7 , PCI_INTAn , bidir , X , 146 , 0 , Z ),"&
" 144 (BC_2 , * , control , 0 ) ,"&
" 143 (LV_BC_7 , PCI_INTBn , bidir , X , 144 , 0 , Z ),"&
" 142 (BC_2 , * , control , 0 ) ,"&
" 141 (BC_2 , PCI_CLKO(2) , output3 , X , 142 , 0 , Z ),"&
" 140 (BC_2 , * , control , 0 ) ,"&
" 139 (LV_BC_7 , PCI_GNTn(1) , bidir , X , 140 , 0 , Z ),"&
" 138 (BC_2 , * , control , 0 ) ,"&
" 137 (BC_2 , PCI_CLKO(1) , output3 , X , 138 , 0 , Z ),"&
" 136 (LV_BC_7 , PCI_REQn(4) , bidir , X , 171 , 0 , Z ),"&
" 135 (BC_2 , * , control , 0 ) ,"&
" 134 (LV_BC_7 , PCI_GNTn(4) , bidir , X , 135 , 0 , Z ),"&
" 133 (LV_BC_7 , PCI_REQn(3) , bidir , X , 171 , 0 , Z ),"&
" 132 (LV_BC_7 , PCI_REQn(2) , bidir , X , 171 , 0 , Z ),"&
" 131 (BC_2 , * , control , 0 ) ,"&
" 130 (LV_BC_7 , PCI_REQn(1) , bidir , X , 131 , 0 , Z ),"&
" 129 (BC_2 , * , control , 0 ) ,"&
" 128 (LV_BC_7 , PCI_AD(30) , bidir , X , 129 , 0 , Z ),"&
" 127 (BC_2 , * , control , 0 ) ,"&
" 126 (LV_BC_7 , PCI_PMEn , bidir , X , 127 , 0 , Z ),"&
" 125 (BC_2 , * , control , 0 ) ,"&
" 124 (LV_BC_7 , PCI_AD(25) , bidir , X , 125 , 0 , Z ),"&
" 123 (BC_2 , * , control , 0 ) ,"&
" 122 (LV_BC_7 , PCI_AD(31) , bidir , X , 123 , 0 , Z ),"&
" 121 (BC_2 , * , control , 0 ) ,"&
" 120 (LV_BC_7 , PCI_AD(29) , bidir , X , 121 , 0 , Z ),"&
" 119 (BC_2 , * , control , 0 ) ,"&
" 118 (LV_BC_7 , PCI_AD(26) , bidir , X , 119 , 0 , Z ),"&
" 117 (BC_2 , * , control , 0 ) ,"&
" 116 (LV_BC_7 , PCI_AD(28) , bidir , X , 117 , 0 , Z ),"&
" 115 (BC_2 , * , control , 0 ) ,"&
" 114 (LV_BC_7 , PCI_AD(24) , bidir , X , 115 , 0 , Z ),"&
" 113 (BC_2 , PCI_IDSEL , input , X ) ,"&
" 112 (BC_2 , * , control , 0 ) ,"&
" 111 (LV_BC_7 , PCI_AD(27) , bidir , X , 112 , 0 , Z ),"&
" 110 (BC_2 , * , control , 0 ) ,"&
" 109 (LV_BC_7 , PCI_AD(22) , bidir , X , 110 , 0 , Z ),"&
" 108 (BC_2 , * , control , 0 ) ,"&
" 107 (LV_BC_7 , PCI_AD(20) , bidir , X , 108 , 0 , Z ),"&
" 106 (BC_2 , * , control , 0 ) ,"&
" 105 (LV_BC_7 , PCI_AD(23) , bidir , X , 106 , 0 , Z ),"&
" 104 (BC_2 , * , control , 0 ) ,"&
" 103 (LV_BC_7 , PCI_CBEn(3) , bidir , X , 104 , 0 , Z ),"&
" 102 (BC_2 , * , control , 0 ) ,"&
" 101 (LV_BC_7 , PCI_AD(19) , bidir , X , 102 , 0 , Z ),"&
" 100 (BC_2 , * , control , 0 ) ,"&
" 99 (LV_BC_7 , PCI_AD(18) , bidir , X , 100 , 0 , Z ),"&
" 98 (BC_2 , * , control , 0 ) ,"&
" 97 (LV_BC_7 , PCI_AD(16) , bidir , X , 98 , 0 , Z ),"&
" 96 (BC_2 , * , control , 0 ) ,"&
" 95 (LV_BC_7 , PCI_AD(21) , bidir , X , 96 , 0 , Z ),"&
" 94 (BC_2 , * , control , 0 ) ,"&
" 93 (LV_BC_7 , PCI_IRDYn , bidir , X , 94 , 0 , Z ),"&
" 92 (BC_2 , * , control , 0 ) ,"&
" 91 (LV_BC_7 , PCI_FRAMEn , bidir , X , 92 , 0 , Z ),"&
" 90 (BC_2 , * , control , 0 ) ,"&
" 89 (LV_BC_7 , PCI_AD(17) , bidir , X , 90 , 0 , Z ),"&
" 88 (BC_2 , * , control , 0 ) ,"&
" 87 (LV_BC_7 , PCI_TRDYn , bidir , X , 88 , 0 , Z ),"&
" 86 (BC_2 , * , control , 0 ) ,"&
" 85 (LV_BC_7 , PCI_PAR , bidir , X , 86 , 0 , Z ),"&
" 84 (BC_2 , * , control , 0 ) ,"&
" 83 (LV_BC_7 , PCI_STOPn , bidir , X , 84 , 0 , Z ),"&
" 82 (BC_2 , * , control , 0 ) ,"&
" 81 (LV_BC_7 , PCI_CBEn(2) , bidir , X , 82 , 0 , Z ),"&
" 80 (BC_2 , * , control , 0 ) ,"&
" 79 (LV_BC_7 , PCI_AD(14) , bidir , X , 80 , 0 , Z ),"&
" 78 (BC_2 , * , control , 0 ) ,"&
" 77 (LV_BC_7 , PCI_AD(15) , bidir , X , 78 , 0 , Z ),"&
" 76 (BC_2 , * , control , 0 ) ,"&
" 75 (LV_BC_7 , PCI_DEVSELn , bidir , X , 76 , 0 , Z ),"&
" 74 (BC_2 , * , control , 0 ) ,"&
" 73 (LV_BC_7 , PCI_AD(13) , bidir , X , 74 , 0 , Z ),"&
" 72 (BC_2 , * , control , 0 ) ,"&
" 71 (LV_BC_7 , PCI_AD(11) , bidir , X , 72 , 0 , Z ),"&
" 70 (BC_2 , * , control , 0 ) ,"&
" 69 (LV_BC_7 , PCI_PERRn , bidir , X , 70 , 0 , Z ),"&
" 68 (BC_2 , * , control , 0 ) ,"&
" 67 (LV_BC_7 , PCI_AD(12) , bidir , X , 68 , 0 , Z ),"&
" 66 (BC_2 , * , control , 0 ) ,"&
" 65 (LV_BC_7 , PCI_CBEn(1) , bidir , X , 66 , 0 , Z ),"&
" 64 (BC_2 , * , control , 0 ) ,"&
" 63 (LV_BC_7 , PCI_CBEn(0) , bidir , X , 64 , 0 , Z ),"&
" 62 (BC_2 , * , control , 0 ) ,"&
" 61 (LV_BC_7 , PCI_AD(9) , bidir , X , 62 , 0 , Z ),"&
" 60 (BC_2 , * , control , 0 ) ,"&
" 59 (LV_BC_7 , PCI_AD(6) , bidir , X , 60 , 0 , Z ),"&
" 58 (BC_2 , * , control , 0 ) ,"&
" 57 (LV_BC_7 , PCI_SERRn , bidir , X , 58 , 0 , Z ),"&
" 56 (BC_2 , * , control , 0 ) ,"&
" 55 (LV_BC_7 , PCI_AD(4) , bidir , X , 56 , 0 , Z ),"&
" 54 (BC_2 , * , control , 0 ) ,"&
" 53 (LV_BC_7 , PCI_AD(7) , bidir , X , 54 , 0 , Z ),"&
" 52 (BC_2 , * , control , 0 ) ,"&
" 51 (LV_BC_7 , PCI_AD(0) , bidir , X , 52 , 0 , Z ),"&
" 50 (BC_2 , * , control , 0 ) ,"&
" 49 (LV_BC_7 , PCI_AD(2) , bidir , X , 50 , 0 , Z ),"&
" 48 (BC_2 , PCI_M66EN , input , X ) ,"&
" 47 (BC_2 , * , control , 0 ) ,"&
" 46 (LV_BC_7 , PCI_AD(8) , bidir , X , 47 , 0 , Z ),"&
" 45 (BC_2 , * , control , 0 ) ,"&
" 44 (LV_BC_7 , PCI_AD(5) , bidir , X , 45 , 0 , Z ),"&
" 43 (BC_2 , * , control , 0 ) ,"&
" 42 (LV_BC_7 , PCI_AD(10) , bidir , X , 43 , 0 , Z ),"&
" 41 (BC_2 , * , control , 0 ) ,"&
" 40 (LV_BC_7 , GPIO(2) , bidir , X , 41 , 0 , Z ),"&
" 39 (BC_2 , * , control , 0 ) ,"&
" 38 (LV_BC_7 , PCI_AD(1) , bidir , X , 39 , 0 , Z ),"&
" 37 (BC_2 , * , control , 0 ) ,"&
" 36 (LV_BC_7 , GPIO(10) , bidir , X , 37 , 0 , Z ),"&
" 35 (BC_2 , * , control , 0 ) ,"&
" 34 (LV_BC_7 , GPIO(5) , bidir , X , 35 , 0 , Z ),"&
" 33 (BC_2 , * , control , 0 ) ,"&
" 32 (LV_BC_7 , GPIO(1) , bidir , X , 33 , 0 , Z ),"&
" 31 (BC_2 , * , control , 0 ) ,"&
" 30 (LV_BC_7 , GPIO(9) , bidir , X , 31 , 0 , Z ),"&
" 29 (BC_2 , * , control , 0 ) ,"&
" 28 (LV_BC_7 , GPIO(0) , bidir , X , 29 , 0 , Z ),"&
" 27 (BC_2 , * , control , 0 ) ,"&
" 26 (LV_BC_7 , GPIO(4) , bidir , X , 27 , 0 , Z ),"&
" 25 (BC_2 , * , control , 0 ) ,"&
" 24 (LV_BC_7 , PCI_AD(3) , bidir , X , 25 , 0 , Z ),"&
" 23 (BC_2 , * , control , 0 ) ,"&
" 22 (LV_BC_7 , GPIO(8) , bidir , X , 23 , 0 , Z ),"&
" 21 (BC_2 , * , control , 0 ) ,"&
" 20 (LV_BC_7 , GPIO(18) , bidir , X , 21 , 0 , Z ),"&
" 19 (BC_2 , * , control , 0 ) ,"&
" 18 (LV_BC_7 , GPIO(3) , bidir , X , 19 , 0 , Z ),"&
" 17 (BC_2 , * , control , 0 ) ,"&
" 16 (LV_BC_7 , GPIO(13) , bidir , X , 17 , 0 , Z ),"&
" 15 (BC_2 , * , control , 0 ) ,"&
" 14 (LV_BC_7 , GPIO(7) , bidir , X , 15 , 0 , Z ),"&
" 13 (BC_2 , * , control , 0 ) ,"&
" 12 (LV_BC_7 , GPIO(17) , bidir , X , 13 , 0 , Z ),"&
" 11 (BC_2 , * , control , 0 ) ,"&
" 10 (LV_BC_7 , GPIO(23) , bidir , X , 11 , 0 , Z ),"&
" 9 (BC_2 , * , control , 0 ) ,"&
" 8 (LV_BC_7 , GPIO(12) , bidir , X , 9 , 0 , Z ),"&
" 7 (BC_2 , * , control , 0 ) ,"&
" 6 (LV_BC_7 , GPIO(16) , bidir , X , 7 , 0 , Z ),"&
" 5 (BC_2 , * , control , 0 ) ,"&
" 4 (LV_BC_7 , GPIO(26) , bidir , X , 5 , 0 , Z ),"&
" 3 (BC_2 , * , control , 0 ) ,"&
" 2 (LV_BC_7 , GPIO(6) , bidir , X , 3 , 0 , Z ),"&
" 1 (BC_2 , * , control , 0 ) ,"&
" 0 (LV_BC_7 , GPIO(22) , bidir , X , 1 , 0 , Z ) ";
attribute AIO_COMPONENT_CONFORMANCE of Tsi620: entity is "STD_1149_6_2003";
attribute AIO_Pin_Behavior of Tsi620: entity is
"SP4_TD_p;"&
"SP4_TC_p;"&
"SP4_TB_p;"&
"SP4_TA_p;"&
"SP2_TD_p;"&
"SP2_TC_p;"&
"SP2_TB_p;"&
"SP2_TA_p;"&
"SP0_TD_p;"&
"SP0_TC_p;"&
"SP0_TB_p;"&
"SP0_TA_p;"&
"SP4_RB_p[436] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP4_RA_p[432] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP4_RC_p[428] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP4_RD_p[424] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP2_RB_p[420] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP2_RA_p[416] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP2_RC_p[412] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP2_RD_p[408] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP0_RB_p[404] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP0_RA_p[400] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP0_RC_p[396] : LP_Time=2.30e-07 HP_Time=7.00e-06;"&
"SP0_RD_p[392] : LP_Time=2.30e-07 HP_Time=7.00e-06";
end Tsi620;
--
-- VHDL package to be uploaded
--package LVS_BSCAN_CELLS is
-- use STD_1149_1_2001.all;
-- constant LV_BC_7: CELL_INFO;
--
--end LVS_BSCAN_CELLS;
--package body LVS_BSCAN_CELLS is
-- use STD_1149_1_2001.all;
-- constant LV_BC_7: CELL_INFO :=
-- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO),
-- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
-- (BIDIR_IN, INTEST, X), (BIDIR_OUT, INTEST, PI));
--
--end LVS_BSCAN_CELLS;