-- $ XILINX$RCSfile: xc2c128_tq144.bsd,v $
-- $ XILINX$Revision: 1.11 $
--
-- BSDL file for device xc2c128_tq144
-- Xilinx, Inc. $State: PRELIMINARY $ $Date: 2006/10/17 16:41:55 $
-- Generated by ABSDG 0.4 on loco
-- =================================================
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entity XC2C128_TQ144 is
generic (PHYSICAL_PIN_MAP : string := "TQ144");
port (
TCK : in bit;
TDI : in bit;
TDO : out bit;
TMS : in bit;
IO_0 : inout bit;
IO_1 : inout bit;
IO_2 : inout bit;
IO_3 : inout bit;
IO_4 : inout bit;
IO_5 : inout bit;
IO_6 : inout bit;
IO_7 : inout bit;
IO_8 : inout bit;
IO_9 : inout bit;
IO_10 : inout bit;
IO_11 : inout bit;
IO_12 : inout bit;
IO_13 : inout bit;
IO_14 : inout bit;
IO_15 : inout bit;
IO_16 : inout bit;
IO_17 : inout bit;
IO_18 : inout bit;
IO_19 : inout bit;
IO_20 : inout bit;
IO_21 : inout bit;
IO_22 : inout bit;
IO_23 : inout bit;
IO_24 : inout bit;
IO_25 : inout bit;
IO_26 : inout bit;
IO_27 : inout bit;
IO_28 : inout bit;
IO_29 : inout bit;
IO_30 : inout bit;
IO_31 : inout bit;
IO_32 : inout bit;
IO_33 : inout bit;
IO_34 : inout bit;
IO_35 : inout bit;
IO_36 : inout bit;
IO_37 : inout bit;
IO_38 : inout bit;
IO_39 : inout bit;
IO_40 : inout bit;
IO_41 : inout bit;
IO_42 : inout bit;
IO_43 : inout bit;
IO_44 : inout bit;
IO_45 : inout bit;
IO_46 : inout bit;
IO_47 : inout bit;
IO_48 : inout bit;
IO_49 : inout bit;
IO_50 : inout bit;
IO_51 : inout bit;
IO_52 : inout bit;
IO_53 : inout bit;
IO_54 : inout bit;
IO_55 : inout bit;
IO_56 : inout bit;
IO_57 : inout bit;
IO_58 : inout bit;
IO_59 : inout bit;
IO_60 : inout bit;
IO_61 : inout bit;
IO_62 : inout bit;
IO_63 : inout bit;
IO_64 : inout bit;
IO_65 : inout bit;
IO_66 : inout bit;
IO_67 : inout bit;
IO_68 : inout bit;
IO_69 : inout bit;
IO_70 : inout bit;
IO_71 : inout bit;
IO_72 : inout bit;
IO_73 : inout bit;
IO_74 : inout bit;
IO_75 : inout bit;
IO_76 : inout bit;
IO_77 : inout bit;
IO_78 : inout bit;
IO_79 : inout bit;
IO_80 : inout bit;
IO_81 : inout bit;
IO_82 : inout bit;
IO_83 : inout bit;
IO_84 : inout bit;
IO_85 : inout bit;
IO_86 : inout bit;
IO_87 : inout bit;
IO_88 : inout bit;
IO_89 : inout bit;
IO_90 : inout bit;
IO_91 : inout bit;
IO_92 : inout bit;
IO_93 : inout bit;
IO_94 : inout bit;
IO_95 : inout bit;
IO_96 : inout bit;
IO_97 : inout bit;
IO_98 : inout bit;
IO_99 : inout bit;
GND : linkage bit_vector(0 to 10);
VDD : linkage bit_vector (0 to 9));
use std_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of XC2C128_TQ144 : entity is "std_1149_1_1993";
attribute PIN_MAP of XC2C128_TQ144 : entity is PHYSICAL_PIN_MAP;
constant TQ144 : PIN_MAP_STRING :=
"TCK : 67, TDI : 63, TDO : 122, TMS : 65, " &
"IO_0 : 17, IO_1 : 16, IO_2 : 15, IO_3 : 14, " &
"IO_4 : 13, IO_5 : 12, IO_6 : 11, IO_7 : 10, " &
"IO_8 : 9, IO_9 : 7, IO_10 : 6, IO_11 : 5, " &
"IO_12 : 19, IO_13 : 21, IO_14 : 22, IO_15 : 23, " &
"IO_16 : 24, IO_17 : 25, IO_18 : 26, IO_19 : 28, " &
"IO_20 : 30, IO_21 : 32, IO_22 : 35, IO_23 : 38, " &
"IO_24 : 4, IO_25 : 3, IO_26 : 2, IO_27 : 143, " &
"IO_28 : 140, IO_29 : 138, IO_30 : 136, IO_31 : 134, " &
"IO_32 : 133, IO_33 : 132, IO_34 : 131, IO_35 : 130, " &
"IO_36 : 129, IO_37 : 39, IO_38 : 40, IO_39 : 41, " &
"IO_40 : 43, IO_41 : 45, IO_42 : 49, IO_43 : 50, " &
"IO_44 : 51, IO_45 : 52, IO_46 : 53, IO_47 : 54, " &
"IO_48 : 56, IO_49 : 57, IO_50 : 94, IO_51 : 95, " &
"IO_52 : 96, IO_53 : 97, IO_54 : 98, IO_55 : 100, " &
"IO_56 : 101, IO_57 : 102, IO_58 : 103, IO_59 : 104, " &
"IO_60 : 105, IO_61 : 110, IO_62 : 111, IO_63 : 92, " &
"IO_64 : 91, IO_65 : 88, IO_66 : 87, IO_67 : 86, " &
"IO_68 : 85, IO_69 : 83, IO_70 : 82, IO_71 : 81, " &
"IO_72 : 80, IO_73 : 79, IO_74 : 78, IO_75 : 112, " &
"IO_76 : 113, IO_77 : 115, IO_78 : 116, IO_79 : 117, " &
"IO_80 : 118, IO_81 : 119, IO_82 : 120, IO_83 : 121, " &
"IO_84 : 124, IO_85 : 125, IO_86 : 126, IO_87 : 128, " &
"IO_88 : 77, IO_89 : 76, IO_90 : 74, IO_91 : 71, " &
"IO_92 : 70, IO_93 : 69, IO_94 : 68, IO_95 : 64, " &
"IO_96 : 61, IO_97 : 60, IO_98 : 59, IO_99 : 58, " &
"GND : (29, 36, 47, 62, 72, 89, 90, 99, 108, 123, 144), VDD : (1, 27, 37, 55, 73, 84, 93, 109, 127, 141)";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (33.0e6, both);
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute INSTRUCTION_LENGTH of XC2C128_TQ144 : entity is 8;
attribute INSTRUCTION_OPCODE of XC2C128_TQ144 : entity is
"INTEST (00000010)," &
"BYPASS (11111111)," &
"SAMPLE (00000011)," &
"EXTEST (00000000)," &
"IDCODE (00000001)," &
"USERCODE (11111101)," &
"HIGHZ (11111100)," &
"ISC_ENABLE_CLAMP (11101001)," &
"ISC_ENABLEOTF (11100100)," &
"ISC_ENABLE (11101000)," &
"ISC_SRAM_READ (11100111)," &
"ISC_SRAM_WRITE (11100110)," &
"ISC_ERASE (11101101)," &
"ISC_PROGRAM (11101010)," &
"ISC_READ (11101110)," &
"ISC_INIT (11110000)," &
"ISC_DISABLE (11000000)," &
"TEST_ENABLE (00010001)," &
"BULKPROG (00010010)," &
"ERASE_ALL (00010100)," &
"MVERIFY (00010011)," &
"TEST_DISABLE (00010101)," &
-- "STCTEST (00010110)," &
"ISC_NOOP (11100000)";
attribute INSTRUCTION_CAPTURE of XC2C128_TQ144 : entity is "XXXXXX01" ;
attribute IDCODE_REGISTER of XC2C128_TQ144 : entity is "XXXX0110110110001100000010010011";
attribute USERCODE_REGISTER of XC2C128_TQ144 : entity is "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
attribute REGISTER_ACCESS of XC2C128_TQ144 : entity is
"BYPASS (BYPASS)," &
"BYPASS (HIGHZ)," &
"BOUNDARY (SAMPLE)," &
"BOUNDARY (EXTEST)," &
"BOUNDARY (INTEST)," &
"DATAREG[759] (ISC_ENABLEOTF)," &
"DATAREG[759] (ISC_ENABLE)," &
"DATAREG[759] (ISC_SRAM_READ)," &
"DATAREG[759] (ISC_SRAM_WRITE)," &
"DATAREG[759] (ISC_ERASE)," &
"DATAREG[759] (ISC_PROGRAM)," &
"DATAREG[759] (ISC_READ)," &
"DATAREG[759] (ISC_INIT)," &
"DATAREG[759] (ISC_DISABLE)," &
"DATAREG[759] (TEST_ENABLE)," &
"DATAREG[759] (BULKPROG)," &
"DATAREG[759] (ERASE_ALL)," &
"DATAREG[759] (MVERIFY)," &
"DATAREG[759] (TEST_DISABLE)," &
-- "STC[] (STCTEST)," &
"ISC_DEFAULT[1] (ISC_NOOP)," &
"DEVICE_ID (IDCODE, USERCODE)," &
"ISC_DEFAULT[1] (ISC_ENABLE_CLAMP)";
attribute BOUNDARY_LENGTH of XC2C128_TQ144 : entity is 300;
attribute BOUNDARY_REGISTER of XC2C128_TQ144 : entity is
" 299 (BC_1, IO_0, INPUT, X),"&
" 298 (BC_1, IO_0, OUTPUT3, X, 297, 0,Z),"&
" 297 (BC_1, *, CONTROL, 0),"&
" 296 (BC_1, IO_1, INPUT, X),"&
" 295 (BC_1, IO_1, OUTPUT3, X, 294, 0,Z),"&
" 294 (BC_1, *, CONTROL, 0),"&
" 293 (BC_1, IO_2, INPUT, X),"&
" 292 (BC_1, IO_2, OUTPUT3, X, 291, 0,Z),"&
" 291 (BC_1, *, CONTROL, 0),"&
" 290 (BC_1, IO_3, INPUT, X),"&
" 289 (BC_1, IO_3, OUTPUT3, X, 288, 0,Z),"&
" 288 (BC_1, *, CONTROL, 0),"&
" 287 (BC_1, IO_4, INPUT, X),"&
" 286 (BC_1, IO_4, OUTPUT3, X, 285, 0,Z),"&
" 285 (BC_1, *, CONTROL, 0),"&
" 284 (BC_1, IO_5, INPUT, X),"&
" 283 (BC_1, IO_5, OUTPUT3, X, 282, 0,Z),"&
" 282 (BC_1, *, CONTROL, 0),"&
" 281 (BC_1, IO_6, INPUT, X),"&
" 280 (BC_1, IO_6, OUTPUT3, X, 279, 0,Z),"&
" 279 (BC_1, *, CONTROL, 0),"&
" 278 (BC_1, IO_7, INPUT, X),"&
" 277 (BC_1, IO_7, OUTPUT3, X, 276, 0,Z),"&
" 276 (BC_1, *, CONTROL, 0),"&
" 275 (BC_1, IO_8, INPUT, X),"&
" 274 (BC_1, IO_8, OUTPUT3, X, 273, 0,Z),"&
" 273 (BC_1, *, CONTROL, 0),"&
" 272 (BC_1, IO_9, INPUT, X),"&
" 271 (BC_1, IO_9, OUTPUT3, X, 270, 0,Z),"&
" 270 (BC_1, *, CONTROL, 0),"&
" 269 (BC_1, IO_10, INPUT, X),"&
" 268 (BC_1, IO_10, OUTPUT3, X, 267, 0,Z),"&
" 267 (BC_1, *, CONTROL, 0),"&
" 266 (BC_1, IO_11, INPUT, X),"&
" 265 (BC_1, IO_11, OUTPUT3, X, 264, 0,Z),"&
" 264 (BC_1, *, CONTROL, 0),"&
" 263 (BC_1, IO_24, INPUT, X),"&
" 262 (BC_1, IO_24, OUTPUT3, X, 261, 0,Z),"&
" 261 (BC_1, *, CONTROL, 0),"&
" 260 (BC_1, IO_25, INPUT, X),"&
" 259 (BC_1, IO_25, OUTPUT3, X, 258, 0,Z),"&
" 258 (BC_1, *, CONTROL, 0),"&
" 257 (BC_1, IO_26, INPUT, X),"&
" 256 (BC_1, IO_26, OUTPUT3, X, 255, 0,Z),"&
" 255 (BC_1, *, CONTROL, 0),"&
" 254 (BC_1, IO_27, INPUT, X),"&
" 253 (BC_1, IO_27, OUTPUT3, X, 252, 0,Z),"&
" 252 (BC_1, *, CONTROL, 0),"&
" 251 (BC_1, IO_28, INPUT, X),"&
" 250 (BC_1, IO_28, OUTPUT3, X, 249, 0,Z),"&
" 249 (BC_1, *, CONTROL, 0),"&
" 248 (BC_1, IO_29, INPUT, X),"&
" 247 (BC_1, IO_29, OUTPUT3, X, 246, 0,Z),"&
" 246 (BC_1, *, CONTROL, 0),"&
" 245 (BC_1, IO_30, INPUT, X),"&
" 244 (BC_1, IO_30, OUTPUT3, X, 243, 0,Z),"&
" 243 (BC_1, *, CONTROL, 0),"&
" 242 (BC_1, IO_31, INPUT, X),"&
" 241 (BC_1, IO_31, OUTPUT3, X, 240, 0,Z),"&
" 240 (BC_1, *, CONTROL, 0),"&
" 239 (BC_1, IO_32, INPUT, X),"&
" 238 (BC_1, IO_32, OUTPUT3, X, 237, 0,Z),"&
" 237 (BC_1, *, CONTROL, 0),"&
" 236 (BC_1, IO_33, INPUT, X),"&
" 235 (BC_1, IO_33, OUTPUT3, X, 234, 0,Z),"&
" 234 (BC_1, *, CONTROL, 0),"&
" 233 (BC_1, IO_34, INPUT, X),"&
" 232 (BC_1, IO_34, OUTPUT3, X, 231, 0,Z),"&
" 231 (BC_1, *, CONTROL, 0),"&
" 230 (BC_1, IO_35, INPUT, X),"&
" 229 (BC_1, IO_35, OUTPUT3, X, 228, 0,Z),"&
" 228 (BC_1, *, CONTROL, 0),"&
" 227 (BC_1, IO_36, INPUT, X),"&
" 226 (BC_1, IO_36, OUTPUT3, X, 225, 0,Z),"&
" 225 (BC_1, *, CONTROL, 0),"&
" 224 (BC_1, IO_12, INPUT, X),"&
" 223 (BC_1, IO_12, OUTPUT3, X, 222, 0,Z),"&
" 222 (BC_1, *, CONTROL, 0),"&
" 221 (BC_1, IO_13, INPUT, X),"&
" 220 (BC_1, IO_13, OUTPUT3, X, 219, 0,Z),"&
" 219 (BC_1, *, CONTROL, 0),"&
" 218 (BC_1, IO_14, INPUT, X),"&
" 217 (BC_1, IO_14, OUTPUT3, X, 216, 0,Z),"&
" 216 (BC_1, *, CONTROL, 0),"&
" 215 (BC_1, IO_15, INPUT, X),"&
" 214 (BC_1, IO_15, OUTPUT3, X, 213, 0,Z),"&
" 213 (BC_1, *, CONTROL, 0),"&
" 212 (BC_1, IO_16, INPUT, X),"&
" 211 (BC_1, IO_16, OUTPUT3, X, 210, 0,Z),"&
" 210 (BC_1, *, CONTROL, 0),"&
" 209 (BC_1, IO_17, INPUT, X),"&
" 208 (BC_1, IO_17, OUTPUT3, X, 207, 0,Z),"&
" 207 (BC_1, *, CONTROL, 0),"&
" 206 (BC_1, IO_18, INPUT, X),"&
" 205 (BC_1, IO_18, OUTPUT3, X, 204, 0,Z),"&
" 204 (BC_1, *, CONTROL, 0),"&
" 203 (BC_1, IO_19, INPUT, X),"&
" 202 (BC_1, IO_19, OUTPUT3, X, 201, 0,Z),"&
" 201 (BC_1, *, CONTROL, 0),"&
" 200 (BC_1, IO_20, INPUT, X),"&
" 199 (BC_1, IO_20, OUTPUT3, X, 198, 0,Z),"&
" 198 (BC_1, *, CONTROL, 0),"&
" 197 (BC_1, IO_21, INPUT, X),"&
" 196 (BC_1, IO_21, OUTPUT3, X, 195, 0,Z),"&
" 195 (BC_1, *, CONTROL, 0),"&
" 194 (BC_1, IO_22, INPUT, X),"&
" 193 (BC_1, IO_22, OUTPUT3, X, 192, 0,Z),"&
" 192 (BC_1, *, CONTROL, 0),"&
" 191 (BC_1, IO_23, INPUT, X),"&
" 190 (BC_1, IO_23, OUTPUT3, X, 189, 0,Z),"&
" 189 (BC_1, *, CONTROL, 0),"&
" 188 (BC_1, IO_37, INPUT, X),"&
" 187 (BC_1, IO_37, OUTPUT3, X, 186, 0,Z),"&
" 186 (BC_1, *, CONTROL, 0),"&
" 185 (BC_1, IO_38, INPUT, X),"&
" 184 (BC_1, IO_38, OUTPUT3, X, 183, 0,Z),"&
" 183 (BC_1, *, CONTROL, 0),"&
" 182 (BC_1, IO_39, INPUT, X),"&
" 181 (BC_1, IO_39, OUTPUT3, X, 180, 0,Z),"&
" 180 (BC_1, *, CONTROL, 0),"&
" 179 (BC_1, IO_40, INPUT, X),"&
" 178 (BC_1, IO_40, OUTPUT3, X, 177, 0,Z),"&
" 177 (BC_1, *, CONTROL, 0),"&
" 176 (BC_1, IO_41, INPUT, X),"&
" 175 (BC_1, IO_41, OUTPUT3, X, 174, 0,Z),"&
" 174 (BC_1, *, CONTROL, 0),"&
" 173 (BC_1, IO_42, INPUT, X),"&
" 172 (BC_1, IO_42, OUTPUT3, X, 171, 0,Z),"&
" 171 (BC_1, *, CONTROL, 0),"&
" 170 (BC_1, IO_43, INPUT, X),"&
" 169 (BC_1, IO_43, OUTPUT3, X, 168, 0,Z),"&
" 168 (BC_1, *, CONTROL, 0),"&
" 167 (BC_1, IO_44, INPUT, X),"&
" 166 (BC_1, IO_44, OUTPUT3, X, 165, 0,Z),"&
" 165 (BC_1, *, CONTROL, 0),"&
" 164 (BC_1, IO_45, INPUT, X),"&
" 163 (BC_1, IO_45, OUTPUT3, X, 162, 0,Z),"&
" 162 (BC_1, *, CONTROL, 0),"&
" 161 (BC_1, IO_46, INPUT, X),"&
" 160 (BC_1, IO_46, OUTPUT3, X, 159, 0,Z),"&
" 159 (BC_1, *, CONTROL, 0),"&
" 158 (BC_1, IO_47, INPUT, X),"&
" 157 (BC_1, IO_47, OUTPUT3, X, 156, 0,Z),"&
" 156 (BC_1, *, CONTROL, 0),"&
" 155 (BC_1, IO_48, INPUT, X),"&
" 154 (BC_1, IO_48, OUTPUT3, X, 153, 0,Z),"&
" 153 (BC_1, *, CONTROL, 0),"&
" 152 (BC_1, IO_49, INPUT, X),"&
" 151 (BC_1, IO_49, OUTPUT3, X, 150, 0,Z),"&
" 150 (BC_1, *, CONTROL, 0),"&
" 149 (BC_1, IO_50, INPUT, X),"&
" 148 (BC_1, IO_50, OUTPUT3, X, 147, 0,Z),"&
" 147 (BC_1, *, CONTROL, 0),"&
" 146 (BC_1, IO_51, INPUT, X),"&
" 145 (BC_1, IO_51, OUTPUT3, X, 144, 0,Z),"&
" 144 (BC_1, *, CONTROL, 0),"&
" 143 (BC_1, IO_52, INPUT, X),"&
" 142 (BC_1, IO_52, OUTPUT3, X, 141, 0,Z),"&
" 141 (BC_1, *, CONTROL, 0),"&
" 140 (BC_1, IO_53, INPUT, X),"&
" 139 (BC_1, IO_53, OUTPUT3, X, 138, 0,Z),"&
" 138 (BC_1, *, CONTROL, 0),"&
" 137 (BC_1, IO_54, INPUT, X),"&
" 136 (BC_1, IO_54, OUTPUT3, X, 135, 0,Z),"&
" 135 (BC_1, *, CONTROL, 0),"&
" 134 (BC_1, IO_55, INPUT, X),"&
" 133 (BC_1, IO_55, OUTPUT3, X, 132, 0,Z),"&
" 132 (BC_1, *, CONTROL, 0),"&
" 131 (BC_1, IO_56, INPUT, X),"&
" 130 (BC_1, IO_56, OUTPUT3, X, 129, 0,Z),"&
" 129 (BC_1, *, CONTROL, 0),"&
" 128 (BC_1, IO_57, INPUT, X),"&
" 127 (BC_1, IO_57, OUTPUT3, X, 126, 0,Z),"&
" 126 (BC_1, *, CONTROL, 0),"&
" 125 (BC_1, IO_58, INPUT, X),"&
" 124 (BC_1, IO_58, OUTPUT3, X, 123, 0,Z),"&
" 123 (BC_1, *, CONTROL, 0),"&
" 122 (BC_1, IO_59, INPUT, X),"&
" 121 (BC_1, IO_59, OUTPUT3, X, 120, 0,Z),"&
" 120 (BC_1, *, CONTROL, 0),"&
" 119 (BC_1, IO_60, INPUT, X),"&
" 118 (BC_1, IO_60, OUTPUT3, X, 117, 0,Z),"&
" 117 (BC_1, *, CONTROL, 0),"&
" 116 (BC_1, IO_61, INPUT, X),"&
" 115 (BC_1, IO_61, OUTPUT3, X, 114, 0,Z),"&
" 114 (BC_1, *, CONTROL, 0),"&
" 113 (BC_1, IO_62, INPUT, X),"&
" 112 (BC_1, IO_62, OUTPUT3, X, 111, 0,Z),"&
" 111 (BC_1, *, CONTROL, 0),"&
" 110 (BC_1, IO_75, INPUT, X),"&
" 109 (BC_1, IO_75, OUTPUT3, X, 108, 0,Z),"&
" 108 (BC_1, *, CONTROL, 0),"&
" 107 (BC_1, IO_76, INPUT, X),"&
" 106 (BC_1, IO_76, OUTPUT3, X, 105, 0,Z),"&
" 105 (BC_1, *, CONTROL, 0),"&
" 104 (BC_1, IO_77, INPUT, X),"&
" 103 (BC_1, IO_77, OUTPUT3, X, 102, 0,Z),"&
" 102 (BC_1, *, CONTROL, 0),"&
" 101 (BC_1, IO_78, INPUT, X),"&
" 100 (BC_1, IO_78, OUTPUT3, X, 99, 0,Z),"&
" 99 (BC_1, *, CONTROL, 0),"&
" 98 (BC_1, IO_79, INPUT, X),"&
" 97 (BC_1, IO_79, OUTPUT3, X, 96, 0,Z),"&
" 96 (BC_1, *, CONTROL, 0),"&
" 95 (BC_1, IO_80, INPUT, X),"&
" 94 (BC_1, IO_80, OUTPUT3, X, 93, 0,Z),"&
" 93 (BC_1, *, CONTROL, 0),"&
" 92 (BC_1, IO_81, INPUT, X),"&
" 91 (BC_1, IO_81, OUTPUT3, X, 90, 0,Z),"&
" 90 (BC_1, *, CONTROL, 0),"&
" 89 (BC_1, IO_82, INPUT, X),"&
" 88 (BC_1, IO_82, OUTPUT3, X, 87, 0,Z),"&
" 87 (BC_1, *, CONTROL, 0),"&
" 86 (BC_1, IO_83, INPUT, X),"&
" 85 (BC_1, IO_83, OUTPUT3, X, 84, 0,Z),"&
" 84 (BC_1, *, CONTROL, 0),"&
" 83 (BC_1, IO_84, INPUT, X),"&
" 82 (BC_1, IO_84, OUTPUT3, X, 81, 0,Z),"&
" 81 (BC_1, *, CONTROL, 0),"&
" 80 (BC_1, IO_85, INPUT, X),"&
" 79 (BC_1, IO_85, OUTPUT3, X, 78, 0,Z),"&
" 78 (BC_1, *, CONTROL, 0),"&
" 77 (BC_1, IO_86, INPUT, X),"&
" 76 (BC_1, IO_86, OUTPUT3, X, 75, 0,Z),"&
" 75 (BC_1, *, CONTROL, 0),"&
" 74 (BC_1, IO_87, INPUT, X),"&
" 73 (BC_1, IO_87, OUTPUT3, X, 72, 0,Z),"&
" 72 (BC_1, *, CONTROL, 0),"&
" 71 (BC_1, IO_63, INPUT, X),"&
" 70 (BC_1, IO_63, OUTPUT3, X, 69, 0,Z),"&
" 69 (BC_1, *, CONTROL, 0),"&
" 68 (BC_1, IO_64, INPUT, X),"&
" 67 (BC_1, IO_64, OUTPUT3, X, 66, 0,Z),"&
" 66 (BC_1, *, CONTROL, 0),"&
" 65 (BC_1, IO_65, INPUT, X),"&
" 64 (BC_1, IO_65, OUTPUT3, X, 63, 0,Z),"&
" 63 (BC_1, *, CONTROL, 0),"&
" 62 (BC_1, IO_66, INPUT, X),"&
" 61 (BC_1, IO_66, OUTPUT3, X, 60, 0,Z),"&
" 60 (BC_1, *, CONTROL, 0),"&
" 59 (BC_1, IO_67, INPUT, X),"&
" 58 (BC_1, IO_67, OUTPUT3, X, 57, 0,Z),"&
" 57 (BC_1, *, CONTROL, 0),"&
" 56 (BC_1, IO_68, INPUT, X),"&
" 55 (BC_1, IO_68, OUTPUT3, X, 54, 0,Z),"&
" 54 (BC_1, *, CONTROL, 0),"&
" 53 (BC_1, IO_69, INPUT, X),"&
" 52 (BC_1, IO_69, OUTPUT3, X, 51, 0,Z),"&
" 51 (BC_1, *, CONTROL, 0),"&
" 50 (BC_1, IO_70, INPUT, X),"&
" 49 (BC_1, IO_70, OUTPUT3, X, 48, 0,Z),"&
" 48 (BC_1, *, CONTROL, 0),"&
" 47 (BC_1, IO_71, INPUT, X),"&
" 46 (BC_1, IO_71, OUTPUT3, X, 45, 0,Z),"&
" 45 (BC_1, *, CONTROL, 0),"&
" 44 (BC_1, IO_72, INPUT, X),"&
" 43 (BC_1, IO_72, OUTPUT3, X, 42, 0,Z),"&
" 42 (BC_1, *, CONTROL, 0),"&
" 41 (BC_1, IO_73, INPUT, X),"&
" 40 (BC_1, IO_73, OUTPUT3, X, 39, 0,Z),"&
" 39 (BC_1, *, CONTROL, 0),"&
" 38 (BC_1, IO_74, INPUT, X),"&
" 37 (BC_1, IO_74, OUTPUT3, X, 36, 0,Z),"&
" 36 (BC_1, *, CONTROL, 0),"&
" 35 (BC_1, IO_88, INPUT, X),"&
" 34 (BC_1, IO_88, OUTPUT3, X, 33, 0,Z),"&
" 33 (BC_1, *, CONTROL, 0),"&
" 32 (BC_1, IO_89, INPUT, X),"&
" 31 (BC_1, IO_89, OUTPUT3, X, 30, 0,Z),"&
" 30 (BC_1, *, CONTROL, 0),"&
" 29 (BC_1, IO_90, INPUT, X),"&
" 28 (BC_1, IO_90, OUTPUT3, X, 27, 0,Z),"&
" 27 (BC_1, *, CONTROL, 0),"&
" 26 (BC_1, IO_91, INPUT, X),"&
" 25 (BC_1, IO_91, OUTPUT3, X, 24, 0,Z),"&
" 24 (BC_1, *, CONTROL, 0),"&
" 23 (BC_1, IO_92, INPUT, X),"&
" 22 (BC_1, IO_92, OUTPUT3, X, 21, 0,Z),"&
" 21 (BC_1, *, CONTROL, 0),"&
" 20 (BC_1, IO_93, INPUT, X),"&
" 19 (BC_1, IO_93, OUTPUT3, X, 18, 0,Z),"&
" 18 (BC_1, *, CONTROL, 0),"&
" 17 (BC_1, IO_94, INPUT, X),"&
" 16 (BC_1, IO_94, OUTPUT3, X, 15, 0,Z),"&
" 15 (BC_1, *, CONTROL, 0),"&
" 14 (BC_1, IO_95, INPUT, X),"&
" 13 (BC_1, IO_95, OUTPUT3, X, 12, 0,Z),"&
" 12 (BC_1, *, CONTROL, 0),"&
" 11 (BC_1, IO_96, INPUT, X),"&
" 10 (BC_1, IO_96, OUTPUT3, X, 9, 0,Z),"&
" 9 (BC_1, *, CONTROL, 0),"&
" 8 (BC_1, IO_97, INPUT, X),"&
" 7 (BC_1, IO_97, OUTPUT3, X, 6, 0,Z),"&
" 6 (BC_1, *, CONTROL, 0),"&
" 5 (BC_1, IO_98, INPUT, X),"&
" 4 (BC_1, IO_98, OUTPUT3, X, 3, 0,Z),"&
" 3 (BC_1, *, CONTROL, 0),"&
" 2 (BC_1, IO_99, INPUT, X),"&
" 1 (BC_1, IO_99, OUTPUT3, X, 0, 0,Z),"&
" 0 (BC_1, *, CONTROL, 0)" ;
end XC2C128_TQ144 ;