-------------------------------------------------------------------------------
-- Motorola PowerPC 603 (TM) Microprocessor Boundary Scan Description Language-
-------------------------------------------------------------------------------
-- Boundary Scan Description Language (IEEE 1149.1b) --
-- --
-- Device : MPC603 Revision 3 --
-- File Version : D --
-- File Name : MPC603.R3D --
-- File created : Dec. 27, 1995 --
-- Package types : CQFP, CBGA --
-------------------------------------------------------------------------------
-- Revision History: --
-- A - Original version --
-- B - Corrected CI_L, WT_L, CSE, TC(0), and TC(1) pin types. --
-- These five pins were identified as "inout" (bidir). The pins are now --
-- type "out" (output3) with bounadry cell type of BC_2 (not BC_6). --
-- C - Changed HRESET_ and CKSTP_ to compliance enable pins (see NOTE below.)--
-- - Changed the output enable cells from "controlr" to "control". --
-- - Changed the TCK clock frequency. --
-- - Changed the COMPONENT_CONFORMANCE. --
-- D - Corrected a typo in the COMPLIANCE_PATTERN statement --
-- - Changed the number of no connect (NC) pins for the BGA package. --
-- - Added warning about the Exit2-IR state to ShiftIR state bug --
-- - Corrected power and ground pins for the CQFP and CBGA packages --
-- --
-- NOTE: Active low ports are designated with a "_L" suffix. --
-- --
-- NOTE: Lines commented by "--##" note statements that can be modified to --
-- support tools using earlier proposed draft versions of BSDL. --
-- --
-- NOTE: The MPC603 is not fully IEEE 1149.1 compliant. Asserting HRESET_ --
-- and CKSTP_ input pins can cause the system logic to interfere with --
-- the IEEE 1149.1 PRELOAD/SAMPLE and EXTEST instructions operation. --
-- The SAMPLE instruction can interfere with the behavior of the --
-- CKSTP_ pin for disabling input pins. An internally generated --
-- checkstop can cause the same non-compliant symptoms as asserting --
-- the CKSTP_ pin. For full details of the non-compliant issues, --
-- please see contact your sales office for the device Errata. --
-- --
-- As a workaround for the non-compliancies, this BSDL file defines --
-- the HRESET_ and CKSTP_ pins as compliance enable pins with a --
-- compliance pattern with the pins held high (unasserted). The input --
-- boundary cells originally associated with the two pins are defined --
-- as internal cells. Additionally, the users are required to --
-- execute a power on hardware reset sequence prior to executing an --
-- EXTEST instruction. HRESET_ and CKSTP_ can be interconnect --
-- tested by comparing the boundary cell values for the two pins --
-- for a high during one normal Shift-DR scan out of EXTEST. --
-- Then, a special EXTEST Shift-DR scan out is required with HRESET_ --
-- and CKSTP_ held low during the Capture-DR and the two cell values --
-- compared for a low with all other TDO scanned out values set to --
-- don't care. This work around is also non-compliant because HRESET_ --
-- and CKSTP_ do not meet the definition for a standard compliance --
-- enable pin. However, the work around will enable SAMPLE/PRELOAD --
-- and EXTEST to work as expected except in the case of an internally --
-- generated checkstop. --
-- --
-- The TAP state machine transistion from the Exit2-IR to the Shift-IR --
-- state erroneously causes the instruction register to do a capture --
-- of the instruction register similar to the Capture-IR state. --
-- --
-- The work-around is to not utilize this data path or to ignore the --
-- eight instruction register bits when they are shifted of TDO after --
-- executing the Exit2-IR to Shift-IR state transistion. --
-- --
-- Board level interconnection tests should function as expected other --
-- than as stated here. --
-- --
-- NOTE: For assistance with this file, contact your sales office. --
-- --
-------------------------------------------------------------------------------
-- --
--===========================================================================--
-- IMPORTANT NOTICE --
-- This information is provided on an AS IS basis and without warranty. --
-- IN NO EVENT SHALL MOTOROLA BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL --
-- DAMAGES ARISING FROM USE OF THIS INFORMATION. THIS DISCLAIMER OF --
-- WARRANTY EXTENDS TO THE USER OF THE INFORMATION, AND TO THEIR CUSTOMERS --
-- OR USERS OF PRODUCTS AND IS IN LIEU OF ALL WARRANTIES WHETHER EXPRESS, --
-- IMPLIED, OR STATUTORY, INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY --
-- OR FITNESS FOR PARTICULAR PURPOSE. --
-- --
-- MOTOROLA does not represent or warrant that the information furnished --
-- hereunder is free of infringement of any third party patents, --
-- copyrights, trade secrets, or other intellectual property rights. --
-- MOTOROLA does not represent or warrant that the information is free of --
-- defect, or that it meets any particular standard, requirements or need --
-- of the user of the infomation or their customers. --
-- --
-- MOTOROLA reserves the right to change the information in this file --
-- without notice. The latest version of the file is available on the --
-- Motorola Freeware Data Services Bulletin Board system at (512)891-FREE --
-- (3733). Modem settings are 8-bit data, no parity, and one start and one --
-- stop bit. Asynchronous transmission rates to 9600 bits per second are --
-- supported. --
-- --
--===========================================================================--
entity mpc603 is
generic (PHYSICAL_PIN_MAP : string := "QFP");
-- PORT DESCRIPTION TERMS
-- in = input only
-- out = three-state output (0, Z, 1)
-- buffer = two-state output (0, 1)
-- inout = bidirectional
-- linkage = OTHER (vdd, vss, analog)
-- bit = single pin
-- bit_vector = group of pins with suffix 0 to n
port ( TCK: in bit;
TDI: in bit;
TDO: out bit;
TMS: in bit;
TRST_L: in bit;
PLL_CFG: in bit_vector(0 to 3);
SYSCLK: in bit;
LSSD_MODE_L: in bit;
L1_TSTCLK: in bit;
L2_TSTCLK: in bit;
CKSTP_L: in bit;
HRESET_L: in bit;
--## LSSD_MODE_L: linkage bit; --Uncomment these five lines and
--## L1_TSTCLK: linkage bit; --comment the five previous lines
--## L2_TSTCLK: linkage bit; --for use with tools that don't
--## CKSTP_L: linkage bit; --handle compliance pins
--## HRESET_L: linkage bit;
TSIZ: inout bit_vector(0 to 2);
TBST_L: inout bit;
TT: inout bit_vector(0 to 4);
SRESET_L: in bit;
INT_L: in bit;
SMI_L: in bit;
MCP_L: in bit;
A: inout bit_vector(0 to 31);
DRTRY_L: in bit;
TA_L: in bit;
TEA_L: in bit;
DBDIS_L: in bit;
XATS_L: inout bit;
TS_L: inout bit;
DBB_L: inout bit;
DL: inout bit_vector(0 to 31);
DH: inout bit_vector(0 to 31);
DP: inout bit_vector(0 to 7);
ABB_L: inout bit;
ARTRY_L: inout bit;
QREQ_L: buffer bit;
AACK_L: in bit;
BG_L: in bit;
DBG_L: in bit;
DBWO_L: in bit;
GBL_L: inout bit;
CI_L: out bit;
WT_L: out bit;
QACK_L: in bit;
TBEN: in bit;
TLBISYNC_L: in bit;
RSRV_L: buffer bit;
AP: inout bit_vector(0 to 3);
CSE: out bit;
TC: out bit_vector(0 to 1);
CLK_OUT: out bit;
BR_L: buffer bit;
APE_L: out bit;
DPE_L: out bit;
CHECKSTOP_L: out bit;
AVDD: linkage bit;
-- The QFP package has 13 VDD, 15 GND, 23 OVDD, and 23 OGND pin.
VDD_qfp: linkage bit_vector(0 to 12);
GND_qfp: linkage bit_vector(0 to 14);
OVDD_qfp: linkage bit_vector(0 to 22);
OGND_qfp: linkage bit_vector(0 to 22);
-- The BGA package has 39 VDD and 40 VSS pins and 10 No connect pins.
VDD_bga: linkage bit_vector(0 to 38);
VSS_bga: linkage bit_vector(0 to 39);
NC_bga: linkage bit_vector(0 to 9));
--## Some proposed BDSL versions require the 1990 version instead of 1994.
--## use STD_1149_1_1990.all;
use STD_1149_1_1994.all;
--## Some proposed BSDL versions did not support "attribute
--## COMPONENT_CONFORMANCE". This statement may be need to be commented out
--## for some users.
attribute COMPONENT_CONFORMANCE of mpc603 : entity is "STD_1149_1_1993";
attribute PIN_MAP of mpc603 : entity is PHYSICAL_PIN_MAP;
constant QFP: PIN_MAP_STRING :=
-- CQFP PINOUT DIAGRAM
"GBL_L: 1, " &
"A: (179,2,178,3,176,5,175,6,174,7,170,11,169,12,168,13,166, "&
"15,165,16,164,17,160,21,159,22,158,23,151,30,144,37), "&
"VDD_qfp: (4,14,24,34,44,59,122,137,147,157,167,177,207), " &
"OGND_qfp: (8,18,33,43,53,60,69,77,86,95,103,111,120,127,136, "&
"146,161,171,181,193,220,228,238), " &
"GND_qfp: (9,19,29,39,49,65,116,132,142,152,162,172,182,206,239), " &
"OVDD_qfp: (10,20,35,45,54,61,70,79,88,96,104,112,121,128,138, " &
"148,163,173,183,194,222,229,240), " &
"AVDD: 209, " &
"DBWO_L: 25, " &
"DBG_L: 26, " &
"BG_L: 27, " &
"AACK_L: 28, " &
"QREQ_L: 31, " &
"ARTRY_L: 32, " &
"ABB_L: 36, " &
"DP: (38,40,41,42,46,47,48,50), "&
"DL: (143,141,140,139,135,134,133,131,130,129,126,125,124, " &
"123,119,118,117,107,106,105,102,101,100,51, 52, 55, 56, " &
"57, 58, 62, 63, 64), "&
"DH: (115,114,113,110,109,108,99,98,97,94,93,92,91,90,89,87, " &
"85, 84, 83, 82, 81, 80, 78,76,75,74,73,72,71,68,67,66), " &
"DBB_L: 145, " &
"TS_L: 149, " &
"XATS_L: 150, " &
"DBDIS_L: 153, " &
"TEA_L: 154, " &
"TA_L: 155, " &
"DRTRY_L: 156, " &
"TT: (191,190,185,184,180), "&
"MCP_L: 186, " &
"SMI_L: 187, " &
"INT_L: 188, " &
"SRESET_L: 189, " &
"TBST_L: 192, " &
"TSIZ: (197,196,195), "&
"TDO: 198, " &
"TDI: 199, " &
"TMS: 200, " &
"TCK: 201, " &
"TRST_L: 202, " &
"L2_TSTCLK: 203, " &
"L1_TSTCLK: 204, " &
"LSSD_MODE_L: 205, " &
"PLL_CFG: (213,211,210,208), "&
"SYSCLK: 212, " &
"HRESET_L: 214, " &
"CKSTP_L: 215, " &
"CHECKSTOP_L: 216, " &
"DPE_L: 217, " &
"APE_L: 218, " &
"BR_L: 219, " &
"CLK_OUT: 221, " &
"TC: (224,223), " &
"CSE: 225, " &
"AP: (231,230,227, 226), "&
"RSRV_L: 232, " &
"TLBISYNC_L: 233, " &
"TBEN: 234, " &
"QACK_L: 235, " &
"WT_L: 236, " &
"CI_L: 237 ";
constant BGA: PIN_MAP_STRING :=
-- CBGA PINOUT DIAGRAM
"A: (C16,E4,D13,F2,D14,G1,D15,E2,D16,D4,E13,G2,E15,H1,E16,H2, " &
"F13,J1,F14,J2,F15,H3,F16,F4,G13,K1,G15,K2,H16,M1,J15,P1),"&
"AACK_L: L2, " &
"ABB_L: K4, " &
"APE_L: A4, " &
"AP: (C1,B4,B3,B2), " &
"ARTRY_L: J4, " &
"AVDD: A10, " &
"BG_L: L1, " &
"BR_L: B6, " &
"CHECKSTOP_L: A6, " &
"CI_L: E1, " &
"CKSTP_L: D8, " &
"CLK_OUT: D7, " &
"CSE: B1, " &
"DBB_L: J14, " &
"DBDIS_L: H15, " &
"DBG_L: N1, " &
"DBWO_L: G4, " &
"DH: (P14,T16,R15,T15,R13,R12,P11,N11,R11,T12,T11,R10,P9, " &
"N9,T10,R9,T9,P8,N8,R8,T8,N7,R7,T7,P6,N6,R6,T6,R5, " &
"N5,T5,T4), " &
"DL: (K13,K15,K16,L16,L15,L13,L14,M16,M15,M13,N16,N15,N13, " &
"N14,P16,P15,R16,R14,T14,N10,P13,N12,T13,P3,N3,N4,R3, " &
"T1,T2,P4,T3,R4), " &
"DPE_L: A5, " &
"DP: (M2,L3,N2,L4,R1,P2,M4,R2), " &
"DRTRY_L: G16, " &
"GBL_L: F1, " &
"HRESET_L: A7, " &
"INT_L: B15, " &
"L1_TSTCLK: D11, " &
"L2_TSTCLK: D12, " &
"LSSD_MODE_L: B10, " &
"MCP_L: C13, " &
"NC_bga: (B5,B7,B8,C3,C6,C8,D5,D6,F3,H4), " & -- No Connects
"PLL_CFG: (A8,B9,A9,D9), " &
"QACK_L: D3, " &
"QREQ_L: J3, " &
"RSRV_L: D1, " &
"SMI_L: A16, " &
"SRESET_L: B14, " &
"SYSCLK: C9, " &
"TA_L: H14, " &
"TBEN: C2, " &
"TBST_L: A14, " &
"TCK: C11, " &
"TC: (A2,A3), " &
"TDI: A11, " &
"TDO: A12, " &
"TEA_L: H13, " &
"TLBISYNC_L: C4, " &
"TMS: B11, " &
"TRST_L: C10, " &
"TSIZ: (A13,D10,B12), " &
"TS_L: J13, " &
"TT: (B13,A15,B16,C14,C15), " &
"VDD_bga: (C7,E5,E7,E10,E12,F6,F8,F9,F11,G3,G5,G7,G10,G12,G14, " &
"H6,H8,H9,H11,J6,J8,J9,J11,K3,K5,K7,K10,K12,K14,L6, " &
"L8,L9,L11,M5,M7,M10,M12,P7,P10), " &
"VSS_bga: (C5,C12,E3,E6,E8,E9,E11,E14,F5,F7,F10,F12,G6,G8,G9, " &
"G11,H5,H7,H10,H12,J5,J7,J10,J12,K6,K8,K9,K11,L5,L7, " &
"L10,L12,M3,M6,M8,M9,M11,M14,P5,P12), " &
"WT_L: D2, " &
"XATS_L: J16 ";
-- Other Pin Maps here when documented
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (62.5e6, BOTH);
attribute TAP_SCAN_RESET of TRST_L : signal is true;
--## Some proposed versions of BSDL used the "attribute COMPLIANCE_ENABLE"
--## statements. These statements may be uncommented if needed.
--## attribute COMPLIANCE_ENABLE of LSSD_MODE_L : signal is true;
--## attribute COMPLIANCE_ENABLE of L1_TSTCLK : signal is true;
--## attribute COMPLIANCE_ENABLE of L2_TSTCLK : signal is true;
--## attribute COMPLIANCE_ENABLE of HRESET_L : signal is true;
--## attribute COMPLIANCE_ENABLE of CKSTP_L : signal is true;
--## Some proposed versions of BSDL did not support "attribute
--## COMPLIANCE_PATTERNS". If you comment out this statement, then declare
--## LSSD_MODE_L, L1_TSTCLK, L2_TSTCLK, HRESET_L, and CKSTP_L to be linkage
--## pins in the port list.
attribute COMPLIANCE_PATTERNS of mpc603: entity is
"(LSSD_MODE_L, L1_TSTCLK, L2_TSTCLK, HRESET_L, CKSTP_L) (11111)";
attribute INSTRUCTION_LENGTH of mpc603 : entity is 8;
attribute INSTRUCTION_OPCODE of mpc603 : entity is
"EXTEST (00000000), "&
"SAMPLE (11000000), "&
"BYPASS (11111111), "&
"PRIVATE001 (00000001), PRIVATE002 (00000010), "&
"PRIVATE003 (00000011), PRIVATE004 (00000100), "&
"PRIVATE005 (00000101), PRIVATE006 (00000110), "&
"PRIVATE007 (00000111), PRIVATE008 (00001000), "&
"PRIVATE009 (00001001), PRIVATE010 (00001010), "&
"PRIVATE011 (00001011), PRIVATE012 (00001100), "&
"PRIVATE013 (00001101), PRIVATE014 (00001110), "&
"PRIVATE015 (00001111), PRIVATE016 (00010000), "&
"PRIVATE017 (00010001), PRIVATE018 (00010010), "&
"PRIVATE019 (00010011), PRIVATE020 (00010100), "&
"PRIVATE021 (00010101), PRIVATE022 (00010110), "&
"PRIVATE023 (00010111), PRIVATE024 (00011000), "&
"PRIVATE025 (00011001), PRIVATE026 (00011010), "&
"PRIVATE027 (00011011), PRIVATE028 (00011100), "&
"PRIVATE029 (00011101), PRIVATE030 (00011110), "&
"PRIVATE031 (00011111), PRIVATE032 (00100000), "&
"PRIVATE033 (00100001), PRIVATE034 (00100010), "&
"PRIVATE035 (00100011), PRIVATE036 (00100100), "&
"PRIVATE037 (00100101), PRIVATE038 (00100110), "&
"PRIVATE039 (00100111), PRIVATE040 (00101000), "&
"PRIVATE041 (00101001), PRIVATE042 (00101010), "&
"PRIVATE043 (00101011), PRIVATE044 (00101100), "&
"PRIVATE045 (00101101), PRIVATE046 (00101110), "&
"PRIVATE047 (00101111), PRIVATE048 (00110000), "&
"PRIVATE049 (00110001), PRIVATE050 (00110010), "&
"PRIVATE051 (00110011), PRIVATE052 (00110100), "&
"PRIVATE053 (00110101), PRIVATE054 (00110110), "&
"PRIVATE055 (00110111), PRIVATE056 (00111000), "&
"PRIVATE057 (00111001), PRIVATE058 (00111010), "&
"PRIVATE059 (00111011), PRIVATE060 (00111100), "&
"PRIVATE061 (00111101), PRIVATE062 (00111110), "&
"PRIVATE063 (00111111), PRIVATE064 (01000000), "&
"PRIVATE065 (01000001), PRIVATE066 (01000010), "&
"PRIVATE067 (01000011), PRIVATE068 (01000100), "&
"PRIVATE069 (01000101), PRIVATE070 (01000110), "&
"PRIVATE071 (01000111), PRIVATE072 (01001000), "&
"PRIVATE073 (01001001), PRIVATE074 (01001010), "&
"PRIVATE075 (01001011), PRIVATE076 (01001100), "&
"PRIVATE077 (01001101), PRIVATE078 (01001110), "&
"PRIVATE079 (01001111), PRIVATE080 (01010000), "&
"PRIVATE081 (01010001), PRIVATE082 (01010010), "&
"PRIVATE083 (01010011), PRIVATE084 (01010100), "&
"PRIVATE085 (01010101), PRIVATE086 (01010110), "&
"PRIVATE087 (01010111), PRIVATE088 (01011000), "&
"PRIVATE089 (01011001), PRIVATE090 (01011010), "&
"PRIVATE091 (01011011), PRIVATE092 (01011100), "&
"PRIVATE093 (01011101), PRIVATE094 (01011110), "&
"PRIVATE095 (01011111), PRIVATE096 (01100000), "&
"PRIVATE097 (01100001), PRIVATE098 (01100010), "&
"PRIVATE099 (01100011), PRIVATE100 (01100100), "&
"PRIVATE101 (01100101), PRIVATE102 (01100110), "&
"PRIVATE103 (01100111), PRIVATE104 (01101000), "&
"PRIVATE105 (01101001), PRIVATE106 (01101010), "&
"PRIVATE107 (01101011), PRIVATE108 (01101100), "&
"PRIVATE109 (01101101), PRIVATE110 (01101110), "&
"PRIVATE111 (01101111), PRIVATE112 (01110000), "&
"PRIVATE113 (01110001), PRIVATE114 (01110010), "&
"PRIVATE115 (01110011), PRIVATE116 (01110100), "&
"PRIVATE117 (01110101), PRIVATE118 (01110110), "&
"PRIVATE119 (01110111), PRIVATE120 (01111000), "&
"PRIVATE121 (01111001), PRIVATE122 (01111010), "&
"PRIVATE123 (01111011), PRIVATE124 (01111100), "&
"PRIVATE125 (01111101), PRIVATE126 (01111110), "&
"PRIVATE127 (01111111), PRIVATE128 (10000000), "&
"PRIVATE129 (10000001), PRIVATE130 (10000010), "&
"PRIVATE131 (10000011), PRIVATE132 (10000100), "&
"PRIVATE133 (10000101), PRIVATE134 (10000110), "&
"PRIVATE135 (10000111), PRIVATE136 (10001000), "&
"PRIVATE137 (10001001), PRIVATE138 (10001010), "&
"PRIVATE139 (10001011), PRIVATE140 (10001100), "&
"PRIVATE141 (10001101), PRIVATE142 (10001110), "&
"PRIVATE143 (10001111), PRIVATE144 (10010000), "&
"PRIVATE145 (10010001), PRIVATE146 (10010010), "&
"PRIVATE147 (10010011), PRIVATE148 (10010100), "&
"PRIVATE149 (10010101), PRIVATE150 (10010110), "&
"PRIVATE151 (10010111), PRIVATE152 (10011000), "&
"PRIVATE153 (10011001), PRIVATE154 (10011010), "&
"PRIVATE155 (10011011), PRIVATE156 (10011100), "&
"PRIVATE157 (10011101), PRIVATE158 (10011110), "&
"PRIVATE159 (10011111), PRIVATE160 (10100000), "&
"PRIVATE161 (10100001), PRIVATE162 (10100010), "&
"PRIVATE163 (10100011), PRIVATE164 (10100100), "&
"PRIVATE165 (10100101), PRIVATE166 (10100110), "&
"PRIVATE167 (10100111), PRIVATE168 (10101000), "&
"PRIVATE169 (10101001), PRIVATE170 (10101010), "&
"PRIVATE171 (10101011), PRIVATE172 (10101100), "&
"PRIVATE173 (10101101), PRIVATE174 (10101110), "&
"PRIVATE175 (10101111), PRIVATE176 (10110000), "&
"PRIVATE177 (10110001), PRIVATE178 (10110010), "&
"PRIVATE179 (10110011), PRIVATE180 (10110100), "&
"PRIVATE181 (10110101), PRIVATE182 (10110110), "&
"PRIVATE183 (10110111), PRIVATE184 (10111000), "&
"PRIVATE185 (10111001), PRIVATE186 (10111010), "&
"PRIVATE187 (10111011), PRIVATE188 (10111100), "&
"PRIVATE189 (10111101), PRIVATE190 (10111110), "&
"PRIVATE191 (10111111), "& -- SAMPLE (11000000)
"PRIVATE193 (11000001), PRIVATE194 (11000010), "&
"PRIVATE195 (11000011), PRIVATE196 (11000100), "&
"PRIVATE197 (11000101), PRIVATE198 (11000110), "&
"PRIVATE199 (11000111), PRIVATE200 (11001000), "&
"PRIVATE201 (11001001), PRIVATE202 (11001010), "&
"PRIVATE203 (11001011), PRIVATE204 (11001100), "&
"PRIVATE205 (11001101), PRIVATE206 (11001110), "&
"PRIVATE207 (11001111), PRIVATE208 (11010000), "&
"PRIVATE209 (11010001), PRIVATE210 (11010010), "&
"PRIVATE211 (11010011), PRIVATE212 (11010100), "&
"PRIVATE213 (11010101), PRIVATE214 (11010110), "&
"PRIVATE215 (11010111), PRIVATE216 (11011000), "&
"PRIVATE217 (11011001), PRIVATE218 (11011010), "&
"PRIVATE219 (11011011), PRIVATE220 (11011100), "&
"PRIVATE221 (11011101), PRIVATE222 (11011110), "&
"PRIVATE223 (11011111), PRIVATE224 (11100000), "&
"PRIVATE225 (11100001), PRIVATE226 (11100010), "&
"PRIVATE227 (11100011), PRIVATE228 (11100100), "&
"PRIVATE229 (11100101), PRIVATE230 (11100110), "&
"PRIVATE231 (11100111), PRIVATE232 (11101000), "&
"PRIVATE233 (11101001), PRIVATE234 (11101010), "&
"PRIVATE235 (11101011), PRIVATE236 (11101100), "&
"PRIVATE237 (11101101), PRIVATE238 (11101110), "&
"PRIVATE239 (11101111), PRIVATE240 (11110000), "&
"PRIVATE241 (11110001), PRIVATE242 (11110010), "&
"PRIVATE243 (11110011), PRIVATE244 (11110100), "&
"PRIVATE245 (11110101), PRIVATE246 (11110110), "&
"PRIVATE247 (11110111), PRIVATE248 (11111000), "&
"PRIVATE249 (11111001), PRIVATE250 (11111010), "&
"PRIVATE251 (11111011), PRIVATE252 (11111100), "&
"PRIVATE253 (11111101), PRIVATE254 (11111110)";
attribute INSTRUCTION_CAPTURE of mpc603 : entity is "xxxxxx01";
-- Use of some private opcodes can result in damage to the circuit,
-- board, or system.
attribute INSTRUCTION_PRIVATE of mpc603 : entity is
"PRIVATE001, PRIVATE002, PRIVATE003, PRIVATE004, "&
"PRIVATE005, PRIVATE006, PRIVATE007, PRIVATE008, "&
"PRIVATE009, PRIVATE010, PRIVATE011, PRIVATE012, "&
"PRIVATE013, PRIVATE014, PRIVATE015, PRIVATE016, "&
"PRIVATE017, PRIVATE018, PRIVATE019, PRIVATE020, "&
"PRIVATE021, PRIVATE022, PRIVATE023, PRIVATE024, "&
"PRIVATE025, PRIVATE026, PRIVATE027, PRIVATE028, "&
"PRIVATE029, PRIVATE030, PRIVATE031, PRIVATE032, "&
"PRIVATE033, PRIVATE034, PRIVATE035, PRIVATE036, "&
"PRIVATE037, PRIVATE038, PRIVATE039, PRIVATE040, "&
"PRIVATE041, PRIVATE042, PRIVATE043, PRIVATE044, "&
"PRIVATE045, PRIVATE046, PRIVATE047, PRIVATE048, "&
"PRIVATE049, PRIVATE050, PRIVATE051, PRIVATE052, "&
"PRIVATE053, PRIVATE054, PRIVATE055, PRIVATE056, "&
"PRIVATE057, PRIVATE058, PRIVATE059, PRIVATE060, "&
"PRIVATE061, PRIVATE062, PRIVATE063, PRIVATE064, "&
"PRIVATE065, PRIVATE066, PRIVATE067, PRIVATE068, "&
"PRIVATE069, PRIVATE070, PRIVATE071, PRIVATE072, "&
"PRIVATE073, PRIVATE074, PRIVATE075, PRIVATE076, "&
"PRIVATE077, PRIVATE078, PRIVATE079, PRIVATE080, "&
"PRIVATE081, PRIVATE082, PRIVATE083, PRIVATE084, "&
"PRIVATE085, PRIVATE086, PRIVATE087, PRIVATE088, "&
"PRIVATE089, PRIVATE090, PRIVATE091, PRIVATE092, "&
"PRIVATE093, PRIVATE094, PRIVATE095, PRIVATE096, "&
"PRIVATE097, PRIVATE098, PRIVATE099, PRIVATE100, "&
"PRIVATE101, PRIVATE102, PRIVATE103, PRIVATE104, "&
"PRIVATE105, PRIVATE106, PRIVATE107, PRIVATE108, "&
"PRIVATE109, PRIVATE110, PRIVATE111, PRIVATE112, "&
"PRIVATE113, PRIVATE114, PRIVATE115, PRIVATE116, "&
"PRIVATE117, PRIVATE118, PRIVATE119, PRIVATE120, "&
"PRIVATE121, PRIVATE122, PRIVATE123, PRIVATE124, "&
"PRIVATE125, PRIVATE126, PRIVATE127, PRIVATE128, "&
"PRIVATE129, PRIVATE130, PRIVATE131, PRIVATE132, "&
"PRIVATE133, PRIVATE134, PRIVATE135, PRIVATE136, "&
"PRIVATE137, PRIVATE138, PRIVATE139, PRIVATE140, "&
"PRIVATE141, PRIVATE142, PRIVATE143, PRIVATE144, "&
"PRIVATE145, PRIVATE146, PRIVATE147, PRIVATE148, "&
"PRIVATE149, PRIVATE150, PRIVATE151, PRIVATE152, "&
"PRIVATE153, PRIVATE154, PRIVATE155, PRIVATE156, "&
"PRIVATE157, PRIVATE158, PRIVATE159, PRIVATE160, "&
"PRIVATE161, PRIVATE162, PRIVATE163, PRIVATE164, "&
"PRIVATE165, PRIVATE166, PRIVATE167, PRIVATE168, "&
"PRIVATE169, PRIVATE170, PRIVATE171, PRIVATE172, "&
"PRIVATE173, PRIVATE174, PRIVATE175, PRIVATE176, "&
"PRIVATE177, PRIVATE178, PRIVATE179, PRIVATE180, "&
"PRIVATE181, PRIVATE182, PRIVATE183, PRIVATE184, "&
"PRIVATE185, PRIVATE186, PRIVATE187, PRIVATE188, "&
"PRIVATE189, PRIVATE190, PRIVATE191, "&
"PRIVATE193, PRIVATE194, PRIVATE195, PRIVATE196, "&
"PRIVATE197, PRIVATE198, PRIVATE199, PRIVATE200, "&
"PRIVATE201, PRIVATE202, PRIVATE203, PRIVATE204, "&
"PRIVATE205, PRIVATE206, PRIVATE207, PRIVATE208, "&
"PRIVATE209, PRIVATE210, PRIVATE211, PRIVATE212, "&
"PRIVATE213, PRIVATE214, PRIVATE215, PRIVATE216, "&
"PRIVATE217, PRIVATE218, PRIVATE219, PRIVATE220, "&
"PRIVATE221, PRIVATE222, PRIVATE223, PRIVATE224, "&
"PRIVATE225, PRIVATE226, PRIVATE227, PRIVATE228, "&
"PRIVATE229, PRIVATE230, PRIVATE231, PRIVATE232, "&
"PRIVATE233, PRIVATE234, PRIVATE235, PRIVATE236, "&
"PRIVATE237, PRIVATE238, PRIVATE239, PRIVATE240, "&
"PRIVATE241, PRIVATE242, PRIVATE243, PRIVATE244, "&
"PRIVATE245, PRIVATE246, PRIVATE247, PRIVATE248, "&
"PRIVATE249, PRIVATE250, PRIVATE251, PRIVATE252, "&
"PRIVATE253, PRIVATE254 ";
attribute REGISTER_ACCESS of mpc603 : entity is
"BYPASS(BYPASS)";
--## Some proposed versions of BSDL used the "attribute BOUNDARY_CELLS"
--## statement. This may be uncommented if needed.
--## attribute BOUNDARY_CELLS of mpc603 : entity is "BC_2, BC_6";
attribute BOUNDARY_LENGTH of mpc603 : entity is 189;
attribute BOUNDARY_REGISTER of mpc603 : entity is
-- PORT DESCRIPTION TERMS
-- cell type: BC_6 bidirectional else BC_2
-- port: port name with index if port description says bit_vector
-- function
-- input = input only
-- bidir = bidirectional
-- control = control cell
-- output2 = two state output
-- output3 = three state ouput
-- safe = value in control cell to make input = 0 for bidir and controlr
-- ccell = controlling cell number for I/O direction
-- dsval = disabling (input) value
-- rslt = result if disabled (input = Z)
--tdo = first cell shifted out during ShiftDR
--num cell port function safe ccell dsval rslt
"0 (BC_2, *, internal, X), "& -- CKSTP_ (see header note)
"1 (BC_2, *, internal, X), "& -- HRESET_ (see header note)
"2 (BC_2, PLL_CFG(0), input, X), "&
"3 (BC_2, SYSCLK, input, X), "&
"4 (BC_2, PLL_CFG(1), input, X), "&
"5 (BC_2, PLL_CFG(2), input, X), "&
"6 (BC_2, PLL_CFG(3), input, X), "&
"7 (BC_6, TSIZ(0), bidir, 0, 10, 0, Z), "&
"8 (BC_6, TSIZ(1), bidir, 0, 10, 0, Z), "&
"9 (BC_6, TSIZ(2), bidir, 0, 10, 0, Z), "&
"10 (BC_2, *, control, 0), "&
"11 (BC_6, TBST_L, bidir, 0, 10, 0, Z), "&
"12 (BC_6, TT(0), bidir, 0, 10, 0, Z), "&
"13 (BC_6, TT(1), bidir, 0, 10, 0, Z), "&
"14 (BC_2, SRESET_L, input, X), "&
"15 (BC_2, INT_L, input, X), "&
"16 (BC_2, SMI_L, input, X), "&
--num cell port function safe ccell dsval rslt
"17 (BC_2, MCP_L, input, X), "&
"18 (BC_6, TT(2), bidir, 0, 20, 0, Z), "&
"19 (BC_6, TT(3), bidir, 0, 20, 0, Z), "&
"20 (BC_2, *, control, 0), "&
"21 (BC_6, TT(4), bidir, 0, 20, 0, Z), "&
"22 (BC_6, A(0), bidir, 0, 20, 0, Z), "&
"23 (BC_6, A(2), bidir, 0, 20, 0, Z), "&
"24 (BC_6, A(4), bidir, 0, 27, 0, Z), "&
"25 (BC_6, A(6), bidir, 0, 27, 0, Z), "&
"26 (BC_6, A(8), bidir, 0, 27, 0, Z), "&
"27 (BC_2, *, control, 0), "&
"28 (BC_6, A(10), bidir, 0, 27, 0, Z), "&
"29 (BC_6, A(12), bidir, 0, 27, 0, Z), "&
"30 (BC_6, A(14), bidir, 0, 27, 0, Z), "&
"31 (BC_6, A(16), bidir, 0, 34, 0, Z), "&
"32 (BC_6, A(18), bidir, 0, 34, 0, Z), "&
"33 (BC_6, A(20), bidir, 0, 34, 0, Z), "&
"34 (BC_2, *, control, 0), "&
"35 (BC_6, A(22), bidir, 0, 34, 0, Z), "&
"36 (BC_6, A(24), bidir, 0, 34, 0, Z), "&
--num cell port function safe ccell dsval rslt
"37 (BC_6, A(26), bidir, 0, 34, 0, Z), "&
"38 (BC_2, DRTRY_L, input, X), "&
"39 (BC_2, TA_L, input, X), "&
"40 (BC_2, TEA_L, input, X), "&
"41 (BC_2, DBDIS_L, input, X), "&
"42 (BC_6, A(28), bidir, 0, 46, 0, Z), "&
"43 (BC_6, XATS_L, bidir, 0, 45, 0, Z), "&
"44 (BC_6, TS_L, bidir, 0, 45, 0, Z), "&
"45 (BC_2, *, control, 0), "&
"46 (BC_2, *, control, 0), "&
"47 (BC_2, *, control, 0), "&
"48 (BC_6, DBB_L, bidir, 0, 47, 0, Z), "&
"49 (BC_6, A(30), bidir, 0, 46, 0, Z), "&
"50 (BC_6, DL(0), bidir, 0, 54, 0, Z), "&
"51 (BC_6, DL(1), bidir, 0, 54, 0, Z), "&
"52 (BC_6, DL(2), bidir, 0, 54, 0, Z), "&
"53 (BC_6, DL(3), bidir, 0, 54, 0, Z), "&
"54 (BC_2, *, control, 0), "&
"55 (BC_6, DL(4), bidir, 0, 54, 0, Z), "&
"56 (BC_6, DL(5), bidir, 0, 54, 0, Z), "&
--num cell port function safe ccell dsval rslt
"57 (BC_6, DL(6), bidir, 0, 61, 0, Z), "&
"58 (BC_6, DL(7), bidir, 0, 61, 0, Z), "&
"59 (BC_6, DL(8), bidir, 0, 61, 0, Z), "&
"60 (BC_6, DL(9), bidir, 0, 61, 0, Z), "&
"61 (BC_2, *, control, 0), "&
"62 (BC_6, DL(10), bidir, 0, 61, 0, Z), "&
"63 (BC_6, DL(11), bidir, 0, 61, 0, Z), "&
"64 (BC_6, DL(12), bidir, 0, 66, 0, Z), "&
"65 (BC_6, DL(13), bidir, 0, 66, 0, Z), "&
"66 (BC_2, *, control, 0), "&
"67 (BC_6, DL(14), bidir, 0, 66, 0, Z), "&
"68 (BC_6, DL(15), bidir, 0, 66, 0, Z), "&
"69 (BC_6, DL(16), bidir, 0, 66, 0, Z), "&
"70 (BC_6, DH(0), bidir, 0, 73, 0, Z), "&
"71 (BC_6, DH(1), bidir, 0, 73, 0, Z), "&
"72 (BC_6, DH(2), bidir, 0, 73, 0, Z), "&
"73 (BC_2, *, control, 0), "&
"74 (BC_6, DH(3), bidir, 0, 73, 0, Z), "&
"75 (BC_6, DH(4), bidir, 0, 73, 0, Z), "&
"76 (BC_6, DH(5), bidir, 0, 73, 0, Z), "&
--num cell port function safe ccell dsval rslt
"77 (BC_6, DL(17), bidir, 0, 80, 0, Z), "&
"78 (BC_6, DL(18), bidir, 0, 80, 0, Z), "&
"79 (BC_6, DL(19), bidir, 0, 80, 0, Z), "&
"80 (BC_2, *, control, 0), "&
"81 (BC_6, DL(20), bidir, 0, 80, 0, Z), "&
"82 (BC_6, DL(21), bidir, 0, 80, 0, Z), "&
"83 (BC_6, DL(22), bidir, 0, 80, 0, Z), "&
"84 (BC_6, DH(6), bidir, 0, 87, 0, Z), "&
"85 (BC_6, DH(7), bidir, 0, 87, 0, Z), "&
"86 (BC_6, DH(8), bidir, 0, 87, 0, Z), "&
"87 (BC_2, *, control, 0), "&
"88 (BC_6, DH(9), bidir, 0, 87, 0, Z), "&
"89 (BC_6, DH(10), bidir, 0, 87, 0, Z), "&
"90 (BC_6, DH(11), bidir, 0, 87, 0, Z), "&
"91 (BC_6, DH(12), bidir, 0, 95, 0, Z), "&
"92 (BC_6, DH(13), bidir, 0, 95, 0, Z), "&
"93 (BC_6, DH(14), bidir, 0, 95, 0, Z), "&
"94 (BC_6, DH(15), bidir, 0, 95, 0, Z), "&
"95 (BC_2, *, control, 0), "&
"96 (BC_6, DH(16), bidir, 0, 95, 0, Z), "&
--num cell port function safe ccell dsval rslt
"97 (BC_6, DH(17), bidir, 0, 95, 0, Z), "&
"98 (BC_6, DH(18), bidir, 0, 95, 0, Z), "&
"99 (BC_6, DH(19), bidir, 0, 103, 0, Z), "&
"100 (BC_6, DH(20), bidir, 0, 103, 0, Z), "&
"101 (BC_6, DH(21), bidir, 0, 103, 0, Z), "&
"102 (BC_6, DH(22), bidir, 0, 103, 0, Z), "&
"103 (BC_2, *, control, 0), "&
"104 (BC_6, DH(23), bidir, 0, 103, 0, Z), "&
"105 (BC_6, DH(24), bidir, 0, 103, 0, Z), "&
"106 (BC_6, DH(25), bidir, 0, 103, 0, Z), "&
"107 (BC_6, DH(26), bidir, 0, 110, 0, Z), "&
"108 (BC_6, DH(27), bidir, 0, 110, 0, Z), "&
"109 (BC_6, DH(28), bidir, 0, 110, 0, Z), "&
"110 (BC_2, *, control, 0), "&
"111 (BC_6, DH(29), bidir, 0, 110, 0, Z), "&
"112 (BC_6, DH(30), bidir, 0, 110, 0, Z), "&
"113 (BC_6, DH(31), bidir, 0, 110, 0, Z), "&
"114 (BC_6, DL(31), bidir, 0, 117, 0, Z), "&
"115 (BC_6, DL(30), bidir, 0, 117, 0, Z), "&
"116 (BC_6, DL(29), bidir, 0, 117, 0, Z), "&
--num cell port function safe ccell dsval rslt
"117 (BC_2, *, control, 0), "&
"118 (BC_6, DL(28), bidir, 0, 117, 0, Z), "&
"119 (BC_6, DL(27), bidir, 0, 117, 0, Z), "&
"120 (BC_6, DL(26), bidir, 0, 122, 0, Z), "&
"121 (BC_6, DL(25), bidir, 0, 122, 0, Z), "&
"122 (BC_2, *, control, 0), "&
"123 (BC_6, DL(24), bidir, 0, 122, 0, Z), "&
"124 (BC_6, DL(23), bidir, 0, 122, 0, Z), "&
"125 (BC_6, DP(7), bidir, 0, 126, 0, Z), "&
"126 (BC_2, *, control, 0), "&
"127 (BC_6, DP(6), bidir, 0, 126, 0, Z), "&
"128 (BC_6, DP(5), bidir, 0, 126, 0, Z), "&
"129 (BC_6, DP(4), bidir, 0, 126, 0, Z), "&
"130 (BC_6, DP(3), bidir, 0, 133, 0, Z), "&
"131 (BC_6, DP(2), bidir, 0, 133, 0, Z), "&
"132 (BC_6, DP(1), bidir, 0, 133, 0, Z), "&
"133 (BC_2, *, control, 0), "&
"134 (BC_6, DP(0), bidir, 0, 133, 0, Z), "&
"135 (BC_6, A(31), bidir, 0, 138, 0, Z), "&
"136 (BC_6, ABB_L, bidir, 0, 137, 0, Z), "&
--num cell port function safe ccell dsval rslt
"137 (BC_2, *, control, 0), "&
"138 (BC_2, *, control, 0), "&
"139 (BC_2, *, control, 0), "&
"140 (BC_6, ARTRY_L, bidir, 0, 139, 0, Z), "&
"141 (BC_2, QREQ_L, output2, X), "&
"142 (BC_6, A(29), bidir, 0, 138, 0, Z), "&
"143 (BC_2, AACK_L, input, X), "&
"144 (BC_2, BG_L, input, X), "&
"145 (BC_2, DBG_L, input, X), "&
"146 (BC_2, DBWO_L, input, X), "&
"147 (BC_6, A(27), bidir, 0, 150, 0, Z), "&
"148 (BC_6, A(25), bidir, 0, 150, 0, Z), "&
"149 (BC_6, A(23), bidir, 0, 150, 0, Z), "&
"150 (BC_2, *, control, 0), "&
"151 (BC_6, A(21), bidir, 0, 150, 0, Z), "&
"152 (BC_6, A(19), bidir, 0, 150, 0, Z), "&
"153 (BC_6, A(17), bidir, 0, 150, 0, Z), "&
"154 (BC_6, A(15), bidir, 0, 157, 0, Z), "&
"155 (BC_6, A(13), bidir, 0, 157, 0, Z), "&
"156 (BC_6, A(11), bidir, 0, 157, 0, Z), "&
--num cell port function safe ccell dsval rslt
"157 (BC_2, *, control, 0), "&
"158 (BC_6, A(9), bidir, 0, 157, 0, Z), "&
"159 (BC_6, A(7), bidir, 0, 157, 0, Z), "&
"160 (BC_6, A(5), bidir, 0, 157, 0, Z), "&
"161 (BC_6, A(3), bidir, 0, 164, 0, Z), "&
"162 (BC_6, A(1), bidir, 0, 164, 0, Z), "&
"163 (BC_6, GBL_L, bidir, 0, 164, 0, Z), "&
"164 (BC_2, *, control, 0), "&
"165 (BC_2, CI_L, output3, 0, 164, 0, Z), "&
"166 (BC_2, WT_L, output3, 0, 164, 0, Z), "&
"167 (BC_2, QACK_L, input, X), "&
"168 (BC_2, TBEN, input, X), "&
"169 (BC_2, TLBISYNC_L, input, X), "&
"170 (BC_2, RSRV_L, output2, X), "&
"171 (BC_6, AP(0), bidir, 0, 173, 0, Z), "&
"172 (BC_6, AP(1), bidir, 0, 173, 0, Z), "&
"173 (BC_2, *, control, 0), "&
"174 (BC_2, *, control, 0), "&
"175 (BC_6, AP(2), bidir, 0, 173, 0, Z), "&
"176 (BC_6, AP(3), bidir, 0, 173, 0, Z), "&
--num cell port function safe ccell dsval rslt
"177 (BC_2, CSE, output3, 0, 174, 0, Z), "&
"178 (BC_2, TC(0), output3, 0, 174, 0, Z), "&
"179 (BC_2, TC(1), output3, 0, 174, 0, Z), "&
"180 (BC_2, *, control, 0), "&
"181 (BC_2, *, control, 0), "&
"182 (BC_2, CLK_OUT, output3, 0, 180, 0, Z), "&
"183 (BC_2, *, control, 0), "&
"184 (BC_2, *, control, 0), "&
"185 (BC_2, BR_L, output2, X), "&
"186 (BC_2, APE_L, output3, 0, 181, 0, Z), "&
"187 (BC_2, DPE_L, output3, 0, 183, 0, Z), "&
"188 (BC_2, CHECKSTOP_L, output3, 0, 184, 0, Z) ";
-- tdi
end mpc603;