-------------------------------------------------------------------------------
--
-- (C) Copyright Cadence Design Systems, Inc.
--
-- BSDL generated by RTL Compiler v11.20-s006_1
-- Created on: Tue Jul 22 23:51:20 2014
--
-- This BSDL is suitable for Cadence Test 1149.1 BSV (it includes the necessary PORT_ALIAS statement for vectored port names).
--
-------------------------------------------------------------------------------
entity GENESIS is
-- Entity declaration
generic (PHYSICAL_PIN_MAP : string := "dummy");
port (
led0 : inout bit;
led1 : inout bit;
led2 : inout bit;
mdint_pwdn : inout bit;
reset_n : in bit;
-- cs_gpio_2 : inout bit; -- 64 pkg
col_gpio_1 : inout bit;
rx_err_gpio_0 : inout bit;
rx_dv_ctl : inout bit;
tx_en_ctl : inout bit;
-- rxd7 : inout bit;-- 64 pkg
-- rxd6 : inout bit;-- 64 pkg
-- rxd5 : inout bit;-- 64 pkg
-- rxd4 : inout bit;-- 64 pkg
rxd3 : inout bit;
rxd2 : inout bit;
rxd1 : inout bit;
rxd0 : inout bit;
rx_clk : inout bit;
gtx_clk : in bit;
-- tx_err : inout bit;-- 64 pkg
txd0 : inout bit;
txd1 : inout bit;
txd2 : inout bit;
txd3 : inout bit;
-- txd4 : inout bit;-- 64 pkg
-- txd5 : inout bit;-- 64 pkg
-- txd6 : inout bit;-- 64 pkg
-- txd7 : inout bit;-- 64 pkg
-- tx_clk : inout bit;-- 64 pkg
jtdi : in bit;
jtms : in bit;
jtdo : out bit;
jtck : in bit;
-- jtrst : in bit;-- 64 pkg
clk_o : inout bit;
mdio : inout bit;
mdc : in bit;
xi : linkage bit;
xo : linkage bit;
-- atp3 : linkage bit;-- 64 pkg
rbias : linkage bit;
tdmd : linkage bit;
tdpd : linkage bit;
tdmc : linkage bit;
tdpc : linkage bit;
-- atp2 : linkage bit;-- 64 pkg
-- atp1 : linkage bit;-- 64 pkg
tdmb : linkage bit;
tdpb : linkage bit;
tdma : linkage bit;
tdpa : linkage bit;
-- atp0 : linkage bit;-- 64 pkg
P_VDDIO : linkage bit_vector(0 to 2);
P_VDDA2P5 : linkage bit_vector(0 to 1);
P_VDDA_1P8V_CD : linkage bit;
P_VDDA_1P8V_AB : linkage bit;
P_VDD1P1 : linkage bit_vector(0 to 3)
);
use STD_1149_1_2001.all ;
use CDNDFT_1149_1_2001.all ;
attribute COMPONENT_CONFORMANCE of GENESIS: entity is "STD_1149_1_2001";
attribute PIN_MAP of GENESIS : entity is PHYSICAL_PIN_MAP;
constant dummy : PIN_MAP_STRING :=
"led0:47, " &
"led1:46, " &
"led2:45, " &
"mdint_pwdn:44, " &
"reset_n:43, " &
"col_gpio_1:40, " &
"rx_err_gpio_0:39, " &
"rx_dv_ctl:38, " &
"tx_en_ctl:37, " &
"rxd3:36, " &
"rxd2:35, " &
"rxd1:34, " &
"rxd0:33, " &
"rx_clk:32, " &
"gtx_clk:29, " &
"txd0:28, " &
"txd1:27, " &
"txd2:26, " &
"txd3:25, " &
"jtdi:23, " &
"jtms:22, " &
"jtdo:21, " &
"jtck:20, " &
"clk_o:18, " &
"mdio:17, " &
"mdc:16, " &
"xi:15, " &
"xo:14, " &
"rbias:12, " &
"tdmd:11, " &
"tdpd:10, " &
"tdmc:8, " &
"tdpc:7, " &
"tdmb:5, " &
"tdpb:4, " &
"tdma:2, " &
"tdpa:1, " &
"P_VDDIO:(41, " &
"30, " &
"19), " &
"P_VDDA2P5:(9, " &
"3), " &
"P_VDDA_1P8V_CD:13, " &
"P_VDDA_1P8V_AB:48, " &
"P_VDD1P1:(42, " &
"31, " &
"24, " &
"6)";
--Scan Port Identification
attribute TAP_SCAN_IN of jtdi: signal is true;
attribute TAP_SCAN_MODE of jtms: signal is true;
attribute TAP_SCAN_OUT of jtdo: signal is true;
attribute TAP_SCAN_CLOCK of jtck: signal is (20.0e6, BOTH);
--attribute TAP_SCAN_RESET of jtrst: signal is true;
attribute INSTRUCTION_LENGTH of GENESIS: entity is 3;
attribute INSTRUCTION_OPCODE of GENESIS: entity is
"BYPASS (111)," &
"EXTEST (001)," &
"SAMPLE (010)," &
"PRELOAD (010)," &
"TESTMODE_REG (100)" ;
attribute INSTRUCTION_CAPTURE of GENESIS: entity is "x01"; -- req'd by Std.
attribute INSTRUCTION_PRIVATE of GENESIS: entity is "TESTMODE_REG";
attribute REGISTER_ACCESS of GENESIS : entity is
"BOUNDARY (EXTEST,SAMPLE,PRELOAD)," &
"BYPASS (BYPASS)" ;
attribute BOUNDARY_LENGTH of GENESIS: entity is 63;
attribute BOUNDARY_REGISTER of GENESIS: entity is
"0 (BC_BIDIR, led0, BIDIR, X, 1, 1, Z)," &
"1 (BC_ENAB_NT, *, CONTROL, 1)," &
"2 (BC_BIDIR, led1, BIDIR, X, 3, 1, Z)," &
"3 (BC_ENAB_NT, *, CONTROL, 1)," &
"4 (BC_BIDIR, led2, BIDIR, X, 5, 1, Z)," &
"5 (BC_ENAB_NT, *, CONTROL, 1)," &
"6 (BC_BIDIR, mdint_pwdn, BIDIR, X, 7, 1, WEAK1)," &
"7 (BC_ENAB_NT, *, CONTROL, 1)," &
"8 (BC_IN, reset_n, INPUT, X)," &
"9 (BC_0, *, internal , X)," &
"10 (BC_0, *,internal , 0)," &
"11 (BC_BIDIR, col_gpio_1, BIDIR, X, 12, 1, Z)," &
"12 (BC_ENAB_NT, *, CONTROL, 1)," &
"13 (BC_BIDIR, rx_err_gpio_0, BIDIR, X, 14, 1, Z)," &
"14 (BC_ENAB_NT, *, CONTROL, 1)," &
"15 (BC_BIDIR, rx_dv_ctl, BIDIR, X, 16, 1, Z)," &
"16 (BC_ENAB_NT, *, CONTROL, 1)," &
"17 (BC_BIDIR, tx_en_ctl, BIDIR, X, 18, 1, WEAK0)," &
"18 (BC_ENAB_NT, *, CONTROL, 1)," &
"19 (BC_0, *, internal, X)," &
"20 (BC_0, *, internal, 0)," &
"21 (BC_0, *, internal, X)," &
"22 (BC_0, *, internal, 0)," &
"23 (BC_0, *, internal, X)," &
"24 (BC_0, *, internal, 0)," &
"25 (BC_0, *, internal, X)," &
"26 (BC_0, *, internal, 0)," &
"27 (BC_BIDIR, rxd3, BIDIR, X, 28, 1, Z)," &
"28 (BC_ENAB_NT, *, CONTROL, 1)," &
"29 (BC_BIDIR, rxd2, BIDIR, X, 30, 1, Z)," &
"30 (BC_ENAB_NT, *, CONTROL, 1)," &
"31 (BC_BIDIR, rxd1, BIDIR, X, 32, 1, Z)," &
"32 (BC_ENAB_NT, *, CONTROL, 1)," &
"33 (BC_BIDIR, rxd0, BIDIR, X, 34, 1, Z)," &
"34 (BC_ENAB_NT, *, CONTROL, 1)," &
"35 (BC_BIDIR, rx_clk, BIDIR, X, 36, 1, Z)," &
"36 (BC_ENAB_NT, *, CONTROL, 1)," &
"37 (BC_IN, gtx_clk, INPUT, X)," &
"38 (BC_0, *, internal, X)," &
"39 (BC_0, *, internal, 0)," &
"40 (BC_BIDIR, txd0, BIDIR, X, 41, 1, WEAK0)," &
"41 (BC_ENAB_NT, *, CONTROL, 1)," &
"42 (BC_BIDIR, txd1, BIDIR, X, 43, 1, WEAK0)," &
"43 (BC_ENAB_NT, *, CONTROL, 1)," &
"44 (BC_BIDIR, txd2, BIDIR, X, 45, 1, WEAK0)," &
"45 (BC_ENAB_NT, *, CONTROL, 1)," &
"46 (BC_BIDIR, txd3, BIDIR, X, 47, 1, WEAK0)," &
"47 (BC_ENAB_NT, *, CONTROL, 1)," &
"48 (BC_0, *, internal, X)," &
"49 (BC_0, *, internal, 0)," &
"50 (BC_0, *, internal, X)," &
"51 (BC_0, *, internal, 0)," &
"52 (BC_0, *, internal, X)," &
"53 (BC_0, *, internal, 0)," &
"54 (BC_0, *, internal, X)," &
"55 (BC_0, *, internal, 0)," &
"56 (BC_0, *, internal, X)," &
"57 (BC_0, *, internal, 0)," &
"58 (BC_BIDIR, clk_o, BIDIR, X, 59, 1, Z)," &
"59 (BC_ENAB_NT, *, CONTROL, 1)," &
"60 (BC_BIDIR, mdio, BIDIR, X, 61, 1, Z)," &
"61 (BC_ENAB_NT, *, CONTROL, 1)," &
"62 (BC_IN, mdc, INPUT, X)";
attribute BOUNDARY_SCAN_DESIGN_TYPE: BSDL_EXTENSION;
attribute BOUNDARY_SCAN_DESIGN_TYPE of GENESIS: entity is "IEEE_11491";
end GENESIS ;