BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: ispLSI2032V


-- *********************************************************************
-- *                                                                   *
-- * ispLSI2032V 44 pin PLCC BSDL Model                                *
-- * copyright 1996-1999, Lattice Semiconductor Corporation            *
-- * IEEE 1149.1b-1994                                                 *
-- * Standard Test Access Port and Boundary-Scan Architecture          *
-- * VHDL Description File                                             *
-- *                                                                   *
-- * Date:              Jul 15 1999                                    *
-- * File Version:      v2.0-00                                        *
-- *                                                                   *
-- * This BSDL file has been syntaxed checked with:                    *
-- * - Teradyne VICTORY                                                *
-- * - Assett Intertech                                                *
-- *                                                                   *
-- *********************************************************************
-- *                                                                   *
-- * E2CMOS, GAL, ispGAL, pDS, pLSI, Silicon Forest and UltraMOS are   *
-- * registered trademarks of Lattice Semiconductor Corporation        *
-- *                                                                   *
-- * Generic Array Logic, ISP, ispCODE, ispDOWNLOAD, ispGDS, ispLSI    *
-- * ispSTREAM, Latch-Lock, pDS+ and RFT are trademarks of Lattice     *
-- * Semiconductor Corporation.                                        *
-- *                                                                   *
-- *********************************************************************
-- *                                                                   *
-- *                           IMPORTANT                               *
-- *                                                                   *
-- * This device does not include a BSCAN register and does not        *
-- * directly support pin continuing testing.  The BSDL file is        *
-- * is provided to define the devices in a scan chain where the       *
-- * Instruction Register and Bypass isntruction must be known         *
-- *                                                                   *
-- *********************************************************************

   -- The Overall Structute of the Entity Description

   entity ispLSI2032V is

   -- Generic Parameter Statement

   generic (PHYSICAL_PIN_MAP : string := "PLCC_44");

   -- Logical Port Description Statement

   port ( TDI: in bit;                                   -- JTAG input pin
          TMS: in bit;                                   -- JTAG input pin
          TCK: in bit;                                   -- JTAG input pin
          TDO: out bit;                                  -- JTAG output pin
          ispEN: linkage bit;                            -- ispEN pin
          RESET: linkage bit;                            -- Active low RESET pin
          GOE: linkage bit;                              -- Global Output Enable
          Clk: linkage bit;                              -- Clock input pin
          BIp: linkage bit_vector (0 to 31);             -- Bi-Directional pins
          VCC: linkage bit_vector (0 to 1);              -- VCC pins
          GND: linkage bit_vector (0 to 1)               -- GND pins
          );

   -- Version Control

   use STD_1149_1_1994.all;                              -- 1149.1-1994 attributes

   -- Component Conformance Statement

   attribute COMPONENT_CONFORMANCE of ispLSI2032V : entity is
   "STD_1149_1_1993";

   -- Device Pacakge Pin Mapping

   attribute PIN_MAP of ispLSI2032V : entity is PHYSICAL_PIN_MAP;

   constant PLCC_44: PIN_MAP_STRING:=

   "TDI:14," &                                           -- JTAG (TDI) input pin
   "TMS:36," &                                           -- JTAG (TMS) input pin
   "TCK:33," &                                           -- JTAG (TCK) input pin
   "TDO:24," &                                           -- JTAG (TDO) output pin
   "RESET:35," &                                         -- RESET input pin
   "ispEN:13," &                                         -- ispEN control pin
   "GOE:2," &                                            -- Global OE pin
   "Clk:11," &                                           -- Clock pin
   "BIp:(   15,   16,   17,   18,   19,   20,   21,  " & -- I/O pins
   "        22,   25,   26,   27,   28,   29,   30,  " & -- I/O pins
   "        31,   32,   37,   38,   39,   40,   41,  " & -- I/O pins
   "        42,   43,   44,    3,    4,    5,    6,  " & -- I/O pins
   "         7,    8,    9,   10),                   " & -- I/O pins
   "VCC:(   12,   34),                               " & -- VCC pins
   "GND:(    1,   23)                                " ; -- GND pins

   -- Scan Port Identification

   attribute TAP_SCAN_CLOCK of TCK : Signal is (5.0e6, BOTH);
   attribute TAP_SCAN_IN of TDI : Signal is True;
   attribute TAP_SCAN_OUT of TDO : Signal is True;
   attribute TAP_SCAN_MODE of TMS : Signal is True;

   -- Instruction Register Description

   attribute INSTRUCTION_LENGTH of ispLSI2032V : entity is 5;
   attribute INSTRUCTION_OPCODE of ispLSI2032V : entity is

      "BYPASS      (11111), " &
      "SAMPLE      (11100), " &
      "EXTEST      (00000), " &
      "IDCODE      (10110), " &
      "USERCODE    (10111), " &
      "HIGHZ       (11000), " &
      "ADDSHFT     (00001), " &
      "DATASHFT    (00010), " &
      "UBE         (10000), " &
      "PRGMH       (00111), " &
      "PRGML       (01000), " &
      "VFYH        (10010), " &
      "VFYL        (10011), " &
      "PRGMSC      (01001), " &
      "PRIVATE     (00011,00100,00101,00110,01010,01011, " &
                   "01100,01110,01111,10001,10101,11001, " &
                   "11010,11011,11101,11110) " ;

   attribute INSTRUCTION_CAPTURE of ispLSI2032V : entity is "11001";
   attribute INSTRUCTION_PRIVATE of ispLSI2032V : entity is "PRIVATE";

   -- IDCODE Defintion

   attribute IDCODE_REGISTER of ispLSI2032V: entity is
   "0000" &                                       -- version 
   "0000001100000001" &                           -- part number (0301)
   "00000100001" &                                -- manufacturer's identity 
   "1" ;                                          -- required by 1149.1

   -- USERCODE Defintion

   attribute USERCODE_REGISTER of ispLSI2032V: entity is
   "11111111111111111111111111111111";

   -- Register Access Description

   attribute REGISTER_ACCESS of ispLSI2032V : entity is
      "BOUNDARY        (SAMPLE), " &
      "BYPASS          (BYPASS), " &
      "ADDREG[102]     (ADDSHFT), " &
      "DATAREG[40]     (DATASHFT), " &
      "UBEREG[1]       (UBE), " &
      "PRGHREG[1]      (PRGMH), " &
      "PRGLREG[1]      (PRGML), " &
      "VFYHREG[1]      (VFYH), " &
      "VFYLREG[1]      (VFYL), " &
      "SECREG[1]       (PRGMSC) " ;

   -- **********************************************************************
   -- Boundary Scan Register Description, Cell 0 is the closest to TDO      
   -- **********************************************************************

   attribute BOUNDARY_LENGTH of ispLSI2032V : entity is   1;
   attribute BOUNDARY_REGISTER of ispLSI2032V : entity is 

   -- num   cell    port        function  safe  [ccell  disval  rslt] 
    "   0  (BC_1,   *,          internal, x) ";

 attribute DESIGN_WARNING of ispLSI2032V : entity is
 "The ispLSI2032V 44 pin PLCC device includes a TAP controller to "&
 "perform ISP programming.  This device does not include Boundary Scan "&
 "Cells and does not support BSCAN test.  The BSDL file includes the "&
 "SAMPLE/PRELOAD and EXTEST instructions so this device may be included "&
 "in the SCAN chain, if these instructions are executed the Bypass "&
 "register is selected.";

end ispLSI2032V;