BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: ispLSI2064E


-- *********************************************************************
-- *                                                                   *
-- * ispLSI2064E 84 pin PLCC BSDL Model                                *
-- * copyright 1996-1999, Lattice Semiconductor Corporation            *
-- * IEEE 1149.1b-1994                                                 *
-- * Standard Test Access Port and Boundary-Scan Architecture          *
-- * VHDL Description File                                             *
-- *                                                                   *
-- * Date:              Jul 15 1999                                    *
-- * File Version:      v2.0-00                                        *
-- *                                                                   *
-- * This BSDL file has been syntaxed checked with:                    *
-- * - Teradyne VICTORY                                                *
-- * - Assett Intertech                                                *
-- *                                                                   *
-- *********************************************************************
-- *                                                                   *
-- * E2CMOS, GAL, ispGAL, pDS, pLSI, Silicon Forest and UltraMOS are   *
-- * registered trademarks of Lattice Semiconductor Corporation        *
-- *                                                                   *
-- * Generic Array Logic, ISP, ispCODE, ispDOWNLOAD, ispGDS, ispLSI    *
-- * ispSTREAM, Latch-Lock, pDS+ and RFT are trademarks of Lattice     *
-- * Semiconductor Corporation.                                        *
-- *                                                                   *
-- *********************************************************************
-- *                                                                   *
-- *                           IMPORTANT                               *
-- *                                                                   *
-- * This device does not include a BSCAN register and does not        *
-- * directly support pin continuing testing.  The BSDL file is        *
-- * is provided to define the devices in a scan chain where the       *
-- * Instruction Register and Bypass isntruction must be known         *
-- *                                                                   *
-- *********************************************************************

   -- The Overall Structute of the Entity Description

   entity ispLSI2064E is

   -- Generic Parameter Statement

   generic (PHYSICAL_PIN_MAP : string := "PLCC_84");

   -- Logical Port Description Statement

   port ( TDI: in bit;                                   -- JTAG input pin
          TMS: in bit;                                   -- JTAG input pin
          TCK: in bit;                                   -- JTAG input pin
          TDO: out bit;                                  -- JTAG output pin
          ispEN: linkage bit;                            -- ispEN pin
          RESET: linkage bit;                            -- Active low RESET pin
          GOE: linkage bit_vector (0 to 1);              -- Global Output Enable
          Clk: linkage bit_vector (0 to 2);              -- Clock input pins
          NoC: linkage bit_vector (0 to 2);              -- No connect pins
          BIp: linkage bit_vector (0 to 63);             -- Bi-Directional pins
          VCC: linkage bit_vector (0 to 1);              -- VCC pins
          GND: linkage bit_vector (0 to 3)               -- GND pins
          );

   -- Version Control

   use STD_1149_1_1994.all;                              -- 1149.1-1994 attributes

   -- Component Conformance Statement

   attribute COMPONENT_CONFORMANCE of ispLSI2064E : entity is
   "STD_1149_1_1993";

   -- Device Pacakge Pin Mapping

   attribute PIN_MAP of ispLSI2064E : entity is PHYSICAL_PIN_MAP;

   constant PLCC_84: PIN_MAP_STRING:=

   "TDI:25," &                                           -- JTAG (TDI) input pin
   "TMS:42," &                                           -- JTAG (TMS) input pin
   "TCK:61," &                                           -- JTAG (TCK) input pin
   "TDO:44," &                                           -- JTAG (TDO) output pin
   "RESET:24," &                                         -- RESET input pin
   "ispEN:23," &                                         -- ispEN control pin
   "GOE:(   67,   84),                               " & -- Global OE pins
   "Clk:(   20,   66,   63),                         " & -- Clock pins
   "NoC:(    2,   19,   62),                         " & -- No Connect pins
   "BIp:(   26,   27,   28,   29,   30,   31,   32,  " & -- I/O pins
   "        33,   34,   35,   36,   37,   38,   39,  " & -- I/O pins
   "        40,   41,   45,   46,   47,   48,   49,  " & -- I/O pins
   "        50,   51,   52,   53,   54,   55,   56,  " & -- I/O pins
   "        57,   58,   59,   60,   68,   69,   70,  " & -- I/O pins
   "        71,   72,   73,   74,   75,   76,   77,  " & -- I/O pins
   "        78,   79,   80,   81,   82,   83,    3,  " & -- I/O pins
   "         4,    5,    6,    7,    8,    9,   10,  " & -- I/O pins
   "        11,   12,   13,   14,   15,   16,   17,  " & -- I/O pins
   "        18),                                     " & -- I/O pins
   "VCC:(   21,   65),                               " & -- VCC pins
   "GND:(    1,   22,   43,   64)                    " ; -- GND pins

   -- Scan Port Identification

   attribute TAP_SCAN_CLOCK of TCK : Signal is (5.0e6, BOTH);
   attribute TAP_SCAN_IN of TDI : Signal is True;
   attribute TAP_SCAN_OUT of TDO : Signal is True;
   attribute TAP_SCAN_MODE of TMS : Signal is True;

   -- Instruction Register Description

   attribute INSTRUCTION_LENGTH of ispLSI2064E : entity is 5;
   attribute INSTRUCTION_OPCODE of ispLSI2064E : entity is

      "BYPASS      (11111), " &
      "SAMPLE      (11100), " &
      "EXTEST      (00000), " &
      "IDCODE      (10110), " &
      "USERCODE    (10111), " &
      "HIGHZ       (11000), " &
      "ADDSHFT     (00001), " &
      "DATASHFT    (00010), " &
      "UBE         (10000), " &
      "PRGM        (00111), " &
      "VFY         (10010), " &
      "PRGMSC      (01001), " &
      "PRIVATE     (00011,00100,00101,00110,01000,01010, " &
                   "01011,01100,01110,01111,10001,10011, " &
                   "10100,10101,11001,11010,11011,11101, " &
                   "11110)" ;

   attribute INSTRUCTION_CAPTURE of ispLSI2064E : entity is "11001";
   attribute INSTRUCTION_PRIVATE of ispLSI2064E : entity is "PRIVATE";

   -- IDCODE Defintion

   attribute IDCODE_REGISTER of ispLSI2064E: entity is
   "0000" &                                       -- version 
   "0000010100101101" &                           -- part number (052D)
   "00000100001" &                                -- manufacturer's identity 
   "1" ;                                          -- required by 1149.1

   -- USERCODE Defintion

   attribute USERCODE_REGISTER of ispLSI2064E: entity is
   "11111111111111111111111111111111";

   -- Register Access Description

   attribute REGISTER_ACCESS of ispLSI2064E : entity is
      "BOUNDARY        (SAMPLE), " &
      "BYPASS          (BYPASS), " &
      "ADDREG[118]     (ADDSHFT), " &
      "DATAREG[160]    (DATASHFT), " &
      "UBEREG[1]       (UBE), " &
      "PRGREG[118]     (PRGM), " &
      "VFYREG[160]     (VFY), " &
      "SECREG[1]       (PRGMSC) " ;

   -- **********************************************************************
   -- Boundary Scan Register Description, Cell 0 is the closest to TDO      
   -- **********************************************************************

   attribute BOUNDARY_LENGTH of ispLSI2064E : entity is   1;
   attribute BOUNDARY_REGISTER of ispLSI2064E : entity is 

   -- num   cell    port        function  safe  [ccell  disval  rslt] 
    "   0  (BC_1,   *,          internal, x) ";

 attribute DESIGN_WARNING of ispLSI2064E : entity is
 "The ispLSI2064E 84 pin PLCC device includes a TAP controller to "&
 "perform ISP programming.  This device does not include Boundary Scan "&
 "Cells and does not support BSCAN test.  The BSDL file includes the "&
 "SAMPLE/PRELOAD and EXTEST instructions so this device may be included "&
 "in the SCAN chain, if these instructions are executed the Bypass "&
 "register is selected.";

end ispLSI2064E;