------------------------------------------------------------------------
-- A T M E L A R M M I C R O C O N T R O L L E R S --
------------------------------------------------------------------------
-- BSDL file
--
-- File Name: AT91SAM7XC256_TQ100.BSD
-- File Revision: 2.1
-- Date: Wed Oct 26 2005
-- Created by: Atmel Corporation
-- File Status: Released
--
-- Device: AT91SAM7XC256
-- Package: R_LQ100_A
--
-- Visit http://www.atmel.com for a updated list of BSDL files.
--
------------------------------------------------------------------------
-- Syntax and Semantics are checked against the IEEE 1149.1 standard. --
-- The logical functioning of the standard Boundary-Scan instructions --
-- and of the associated bypass, idcode and boundary-scan register --
-- described in this BSDL file has been verified against its related --
-- silicon by JTAG Technologies B.V. --
------------------------------------------------------------------------
------------------------------------------------------------------------
-- IMPORTANT NOTICE --
-- --
-- Copyright 2005 Atmel Corporation. All Rights Reserved. --
-- --
-- Atmel assumes no responsibility or liability arising out --
-- this application or use of any information described herein --
-- except as expressly agreed to in writing by Atmel Corporation. --
-- --
-- ------------------------------------------------------------------ --
-- This BSDL File has been verified on severals BSDL Syntax --
-- Checker/Compilers --
-- --
-- --
-- AGILENT 3070 BSDL COMPILER Wed Oct 26 10:14:17 MDT 2005 --
-- BSDL File AT91SAM7XC256_TQ100.bsd, package package R_LQ100_A --
-- successfully. 0 ERRORS, 1 WARNING, OBJECT PRODUCED --
-- --
------------------------------------------------------------------------
entity AT91SAM7XC256 is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "R_LQ100_A");
-- This section declares all the ports in the design.
port (
erase : in bit;
icetck : in bit;
icetdi : in bit;
icetms : in bit;
jtagsel : in bit;
nrst : in bit;
test : in bit;
pa0 : inout bit;
pa1 : inout bit;
pa10 : inout bit;
pa11 : inout bit;
pa12 : inout bit;
pa13 : inout bit;
pa14 : inout bit;
pa15 : inout bit;
pa16 : inout bit;
pa17 : inout bit;
pa18 : inout bit;
pa19 : inout bit;
pa2 : inout bit;
pa20 : inout bit;
pa21 : inout bit;
pa22 : inout bit;
pa23 : inout bit;
pa24 : inout bit;
pa25 : inout bit;
pa26 : inout bit;
pa27 : inout bit;
pa28 : inout bit;
pa29 : inout bit;
pa3 : inout bit;
pa30 : inout bit;
pa4 : inout bit;
pa5 : inout bit;
pa6 : inout bit;
pa7 : inout bit;
pa8 : inout bit;
pa9 : inout bit;
pb0 : inout bit;
pb1 : inout bit;
pb10 : inout bit;
pb11 : inout bit;
pb12 : inout bit;
pb13 : inout bit;
pb14 : inout bit;
pb15 : inout bit;
pb16 : inout bit;
pb17 : inout bit;
pb18 : inout bit;
pb19 : inout bit;
pb2 : inout bit;
pb20 : inout bit;
pb21 : inout bit;
pb22 : inout bit;
pb23 : inout bit;
pb24 : inout bit;
pb25 : inout bit;
pb26 : inout bit;
pb27 : inout bit;
pb28 : inout bit;
pb29 : inout bit;
pb3 : inout bit;
pb30 : inout bit;
pb4 : inout bit;
pb5 : inout bit;
pb6 : inout bit;
pb7 : inout bit;
pb8 : inout bit;
pb9 : inout bit;
icetdo : out bit
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of AT91SAM7XC256: entity is
"STD_1149_1_1993";
attribute PIN_MAP of AT91SAM7XC256: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant R_LQ100_A: PIN_MAP_STRING :=
"erase : 92," &
"icetck : 79," &
"icetdi : 51," &
"icetms : 78," &
"jtagsel : 77," &
"nrst : 57," &
"test : 58," &
"pa0 : 81," &
"pa1 : 82," &
"pa10 : 18," &
"pa11 : 19," &
"pa12 : 20," &
"pa13 : 21," &
"pa14 : 22," &
"pa15 : 23," &
"pa16 : 24," &
"pa17 : 25," &
"pa18 : 26," &
"pa19 : 46," &
"pa2 : 86," &
"pa20 : 47," &
"pa21 : 49," &
"pa22 : 50," &
"pa23 : 55," &
"pa24 : 56," &
"pa25 : 59," &
"pa26 : 60," &
"pa27 : 73," &
"pa28 : 74," &
"pa29 : 75," &
"pa3 : 85," &
"pa30 : 80," &
"pa4 : 88," &
"pa5 : 89," &
"pa6 : 90," &
"pa7 : 91," &
"pa8 : 13," &
"pa9 : 14," &
"pb0 : 40," &
"pb1 : 41," &
"pb10 : 44," &
"pb11 : 45," &
"pb12 : 39," &
"pb13 : 30," &
"pb14 : 29," &
"pb15 : 35," &
"pb16 : 53," &
"pb17 : 36," &
"pb18 : 63," &
"pb19 : 64," &
"pb2 : 42," &
"pb20 : 65," &
"pb21 : 66," &
"pb22 : 67," &
"pb23 : 69," &
"pb24 : 70," &
"pb25 : 71," &
"pb26 : 72," &
"pb27 : 9," &
"pb28 : 10," &
"pb29 : 11," &
"pb3 : 43," &
"pb30 : 12," &
"pb4 : 54," &
"pb5 : 34," &
"pb6 : 31," &
"pb7 : 38," &
"pb8 : 28," &
"pb9 : 27," &
"icetdo : 76";
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of icetck: signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of icetdi: signal is true;
attribute TAP_SCAN_MODE of icetms: signal is true;
attribute TAP_SCAN_OUT of icetdo: signal is true;
attribute TAP_SCAN_RESET of nrst : signal is true;
-- Specifies the compliance enable patterns for the design.
-- It lists a set of design ports and the values that they
-- should be set to, in order to enable compliance to IEEE
-- Std 1149.1
attribute COMPLIANCE_PATTERNS of AT91SAM7XC256: entity is
"(jtagsel, test) (10)";
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of AT91SAM7XC256: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of AT91SAM7XC256: entity is
"BYPASS (111)," &
"EXTEST (000, 011)," &
"SAMPLE (001)," &
"HIGHZ (100, 110)," &
"IDCODE (010)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of AT91SAM7XC256: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of AT91SAM7XC256: entity is
"0000" & -- 4-bit version number
"0101101100010000" & -- 16-bit part number
"00000011111" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of AT91SAM7XC256: entity is
"BYPASS (BYPASS, HIGHZ)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of AT91SAM7XC256: entity is 187;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of AT91SAM7XC256: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"186 (BC_1, pa30, input, X), " &
"185 (BC_1, pa30, output3, X, 184, 1, Z), " &
"184 (BC_1, *, controlr, 1), " &
"183 (BC_1, pa0, input, X), " &
"182 (BC_1, pa0, output3, X, 181, 1, Z), " &
"181 (BC_1, *, controlr, 1), " &
"180 (BC_1, pa1, input, X), " &
"179 (BC_1, pa1, output3, X, 178, 1, Z), " &
"178 (BC_1, *, controlr, 1), " &
"177 (BC_1, pa3, input, X), " &
"176 (BC_1, pa3, output3, X, 175, 1, Z), " &
"175 (BC_1, *, controlr, 1), " &
"174 (BC_1, pa2, input, X), " &
"173 (BC_1, pa2, output3, X, 172, 1, Z), " &
"172 (BC_1, *, controlr, 1), " &
"171 (BC_1, pa4, input, X), " &
"170 (BC_1, pa4, output3, X, 169, 1, Z), " &
"169 (BC_1, *, controlr, 1), " &
"168 (BC_1, pa5, input, X), " &
"167 (BC_1, pa5, output3, X, 166, 1, Z), " &
"166 (BC_1, *, controlr, 1), " &
"165 (BC_1, pa6, input, X), " &
"164 (BC_1, pa6, output3, X, 163, 1, Z), " &
"163 (BC_1, *, controlr, 1), " &
"162 (BC_1, pa7, input, X), " &
"161 (BC_1, pa7, output3, X, 160, 1, Z), " &
"160 (BC_1, *, controlr, 1), " &
"159 (BC_1, erase, input, X), " &
"158 (BC_1, pb27, input, X), " &
"157 (BC_1, pb27, output3, X, 156, 1, Z), " &
"156 (BC_1, *, controlr, 1), " &
"155 (BC_1, pb28, input, X), " &
"154 (BC_1, pb28, output3, X, 153, 1, Z), " &
"153 (BC_1, *, controlr, 1), " &
"152 (BC_1, pb29, input, X), " &
"151 (BC_1, pb29, output3, X, 150, 1, Z), " &
"150 (BC_1, *, controlr, 1), " &
"149 (BC_1, pb30, input, X), " &
"148 (BC_1, pb30, output3, X, 147, 1, Z), " &
"147 (BC_1, *, controlr, 1), " &
"146 (BC_1, pa8, input, X), " &
"145 (BC_1, pa8, output3, X, 144, 1, Z), " &
"144 (BC_1, *, controlr, 1), " &
"143 (BC_1, pa9, input, X), " &
"142 (BC_1, pa9, output3, X, 141, 1, Z), " &
"141 (BC_1, *, controlr, 1), " &
"140 (BC_1, pa10, input, X), " &
"139 (BC_1, pa10, output3, X, 138, 1, Z), " &
"138 (BC_1, *, controlr, 1), " &
"137 (BC_1, pa11, input, X), " &
"136 (BC_1, pa11, output3, X, 135, 1, Z), " &
"135 (BC_1, *, controlr, 1), " &
"134 (BC_1, pa12, input, X), " &
"133 (BC_1, pa12, output3, X, 132, 1, Z), " &
"132 (BC_1, *, controlr, 1), " &
"131 (BC_1, pa13, input, X), " &
"130 (BC_1, pa13, output3, X, 129, 1, Z), " &
"129 (BC_1, *, controlr, 1), " &
"128 (BC_1, pa14, input, X), " &
"127 (BC_1, pa14, output3, X, 126, 1, Z), " &
"126 (BC_1, *, controlr, 1), " &
"125 (BC_1, pa15, input, X), " &
"124 (BC_1, pa15, output3, X, 123, 1, Z), " &
"123 (BC_1, *, controlr, 1), " &
"122 (BC_1, pa16, input, X), " &
"121 (BC_1, pa16, output3, X, 120, 1, Z), " &
"120 (BC_1, *, controlr, 1), " &
"119 (BC_1, pa17, input, X), " &
"118 (BC_1, pa17, output3, X, 117, 1, Z), " &
"117 (BC_1, *, controlr, 1), " &
"116 (BC_1, pa18, input, X), " &
"115 (BC_1, pa18, output3, X, 114, 1, Z), " &
"114 (BC_1, *, controlr, 1), " &
"113 (BC_1, pb9, input, X), " &
"112 (BC_1, pb9, output3, X, 111, 1, Z), " &
"111 (BC_1, *, controlr, 1), " &
"110 (BC_1, pb8, input, X), " &
"109 (BC_1, pb8, output3, X, 108, 1, Z), " &
"108 (BC_1, *, controlr, 1), " &
"107 (BC_1, pb14, input, X), " &
"106 (BC_1, pb14, output3, X, 105, 1, Z), " &
"105 (BC_1, *, controlr, 1), " &
"104 (BC_1, pb13, input, X), " &
"103 (BC_1, pb13, output3, X, 102, 1, Z), " &
"102 (BC_1, *, controlr, 1), " &
"101 (BC_1, pb6, input, X), " &
"100 (BC_1, pb6, output3, X, 99, 1, Z), " &
"99 (BC_1, *, controlr, 1), " &
"98 (BC_1, pb5, input, X), " &
"97 (BC_1, pb5, output3, X, 96, 1, Z), " &
"96 (BC_1, *, controlr, 1), " &
"95 (BC_1, pb15, input, X), " &
"94 (BC_1, pb15, output3, X, 93, 1, Z), " &
"93 (BC_1, *, controlr, 1), " &
"92 (BC_1, pb17, input, X), " &
"91 (BC_1, pb17, output3, X, 90, 1, Z), " &
"90 (BC_1, *, controlr, 1), " &
"89 (BC_1, pb7, input, X), " &
"88 (BC_1, pb7, output3, X, 87, 1, Z), " &
"87 (BC_1, *, controlr, 1), " &
"86 (BC_1, pb12, input, X), " &
"85 (BC_1, pb12, output3, X, 84, 1, Z), " &
"84 (BC_1, *, controlr, 1), " &
"83 (BC_1, pb0, input, X), " &
"82 (BC_1, pb0, output3, X, 81, 1, Z), " &
"81 (BC_1, *, controlr, 1), " &
"80 (BC_1, pb1, input, X), " &
"79 (BC_1, pb1, output3, X, 78, 1, Z), " &
"78 (BC_1, *, controlr, 1), " &
"77 (BC_1, pb2, input, X), " &
"76 (BC_1, pb2, output3, X, 75, 1, Z), " &
"75 (BC_1, *, controlr, 1), " &
"74 (BC_1, pb3, input, X), " &
"73 (BC_1, pb3, output3, X, 72, 1, Z), " &
"72 (BC_1, *, controlr, 1), " &
"71 (BC_1, pb10, input, X), " &
"70 (BC_1, pb10, output3, X, 69, 1, Z), " &
"69 (BC_1, *, controlr, 1), " &
"68 (BC_1, pb11, input, X), " &
"67 (BC_1, pb11, output3, X, 66, 1, Z), " &
"66 (BC_1, *, controlr, 1), " &
"65 (BC_1, pa19, input, X), " &
"64 (BC_1, pa19, output3, X, 63, 1, Z), " &
"63 (BC_1, *, controlr, 1), " &
"62 (BC_1, pa20, input, X), " &
"61 (BC_1, pa20, output3, X, 60, 1, Z), " &
"60 (BC_1, *, controlr, 1), " &
"59 (BC_1, pa21, input, X), " &
"58 (BC_1, pa21, output3, X, 57, 1, Z), " &
"57 (BC_1, *, controlr, 1), " &
"56 (BC_1, pa22, input, X), " &
"55 (BC_1, pa22, output3, X, 54, 1, Z), " &
"54 (BC_1, *, controlr, 1), " &
"53 (BC_1, pb16, input, X), " &
"52 (BC_1, pb16, output3, X, 51, 1, Z), " &
"51 (BC_1, *, controlr, 1), " &
"50 (BC_1, pb4, input, X), " &
"49 (BC_1, pb4, output3, X, 48, 1, Z), " &
"48 (BC_1, *, controlr, 1), " &
"47 (BC_1, pa23, input, X), " &
"46 (BC_1, pa23, output3, X, 45, 1, Z), " &
"45 (BC_1, *, controlr, 1), " &
"44 (BC_1, pa24, input, X), " &
"43 (BC_1, pa24, output3, X, 42, 1, Z), " &
"42 (BC_1, *, controlr, 1), " &
"41 (BC_1, pa25, input, X), " &
"40 (BC_1, pa25, output3, X, 39, 1, Z), " &
"39 (BC_1, *, controlr, 1), " &
"38 (BC_1, pa26, input, X), " &
"37 (BC_1, pa26, output3, X, 36, 1, Z), " &
"36 (BC_1, *, controlr, 1), " &
"35 (BC_1, pb18, input, X), " &
"34 (BC_1, pb18, output3, X, 33, 1, Z), " &
"33 (BC_1, *, controlr, 1), " &
"32 (BC_1, pb19, input, X), " &
"31 (BC_1, pb19, output3, X, 30, 1, Z), " &
"30 (BC_1, *, controlr, 1), " &
"29 (BC_1, pb20, input, X), " &
"28 (BC_1, pb20, output3, X, 27, 1, Z), " &
"27 (BC_1, *, controlr, 1), " &
"26 (BC_1, pb21, input, X), " &
"25 (BC_1, pb21, output3, X, 24, 1, Z), " &
"24 (BC_1, *, controlr, 1), " &
"23 (BC_1, pb22, input, X), " &
"22 (BC_1, pb22, output3, X, 21, 1, Z), " &
"21 (BC_1, *, controlr, 1), " &
"20 (BC_1, pb23, input, X), " &
"19 (BC_1, pb23, output3, X, 18, 1, Z), " &
"18 (BC_1, *, controlr, 1), " &
"17 (BC_1, pb24, input, X), " &
"16 (BC_1, pb24, output3, X, 15, 1, Z), " &
"15 (BC_1, *, controlr, 1), " &
"14 (BC_1, pb25, input, X), " &
"13 (BC_1, pb25, output3, X, 12, 1, Z), " &
"12 (BC_1, *, controlr, 1), " &
"11 (BC_1, pb26, input, X), " &
"10 (BC_1, pb26, output3, X, 9, 1, Z), " &
"9 (BC_1, *, controlr, 1), " &
"8 (BC_1, pa27, input, X), " &
"7 (BC_1, pa27, output3, X, 6, 1, Z), " &
"6 (BC_1, *, controlr, 1), " &
"5 (BC_1, pa28, input, X), " &
"4 (BC_1, pa28, output3, X, 3, 1, Z), " &
"3 (BC_1, *, controlr, 1), " &
"2 (BC_1, pa29, input, X), " &
"1 (BC_1, pa29, output3, X, 0, 1, Z), " &
"0 (BC_1, *, controlr, 1) ";
end AT91SAM7XC256;