This BSDL contains syntax errors!
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--TI TMS320VC5421 16-Bit 144-pin Fixed-Point DSP with Boundary Scan --
----------------------------------------------------------------------
-- Supported Devices: TMS320VC5421 144-pin Revision 1.0 and higher --
----------------------------------------------------------------------
-- --
-- This file contains the boundary scan description --
-- of CPU A of the 5421 only. --
-- --
----------------------------------------------------------------------
-- Created by : Texas Instruments Incorporated --
-- Documentation : TMS320VC54x Users Guide --
-- BSDL Revision : 1.0 - Original --
-- 1.1 - Control Cells for cells 33,34 corrected --
-- 1.2 - Reverse chain order --
-- --
-- BSDL status : Preliminary --
-- Date created : 01/25/2000 --
-- Last modified : 07/24/2000 --
----------------------------------------------------------------------
-- --
-- IMPORTANT NOTICE
-- Texas Instruments Incorporated (TI) reserves the right to make
-- changes to its products or to discontinue any semiconductor
-- product or service without notice, and advises its customers to
-- obtain the latest version of the relevant information to
-- verify, before placing orders, that the information being
-- relied on is current.
-- TI warrants performance of its semiconductor products and
-- related software to the specifications applicable at the time
-- of sale in accordance with TI's standard warranty. Testing and
-- other quality control techniques are utilized to the extent TI
-- deems necessary to support this warranty. Specific testing of
-- all parameters of each device is not necessarily performed,
-- except those mandated by government requirements.
--
-- Certain applications using semiconductor devices may involve
-- potential risks of death, personal injury, or severe property
-- or environmental damage ("Critical Applications").
-- TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
-- AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN
-- LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
-- CRITICAL APPLICATIONS.
-- Inclusion of TI products in such applications is understood
-- to be fully at the risk of the customer. Use of TI products
-- in such applications requires the written approval of an
-- appropriate TI officer. Questions concerning potential risk
-- applications should be directed to TI through a local SC sales
-- office.
-- In order to minimize risks associated with the customer's
-- applications, adequate design and operating safeguards should
-- be provided by the
-- customer to minimize inherent or procedural hazards.
-- TI assumes no liability for applications assistance, customer
-- product design, software performance, or infringement of
-- patents or services described herein. Nor does TI warrant or
-- represent that any license, either express or implied, is
-- granted under any patent right, copyright, mask work right, or
-- other intellectual property right of TI covering or relating
-- to any combination, machine, or process in which such
-- semiconductor products or services might be or are used.
-- Copyright (c) 2000, Texas Instruments Incorporated
-------------------------------------------------------------------
entity TMS320VC5421_cpu_A is
generic (PHYSICAL_PIN_MAP : string := "PGE");
port (HA : inout bit_vector(0 to 17);
HD : inout bit_vector(0 to 15);
A_BCLKR0 : inout bit;
A_BCLKR1 : inout bit;
A_BCLKR2 : inout bit;
A_BCLKX0 : inout bit;
A_BCLKX1 : inout bit;
A_BCLKX2 : inout bit;
A_BDR0 : in bit;
A_BDR1 : in bit;
A_BDR2 : in bit;
A_BDX0 : out bit;
A_BDX1 : out bit;
A_BDX2 : out bit;
A_BFSR0 : inout bit;
A_BFSR1 : inout bit;
A_BFSR2 : inout bit;
A_BFSX0 : inout bit;
A_BFSX1 : inout bit;
A_BFSX2 : inout bit;
A_CLKOUT : out bit;
A_GPIO0 : inout bit;
A_GPIO1 : inout bit;
A_GPIO2 : inout bit;
A_GPIO3 : inout bit;
A_INT0 : in bit;
A_INT1 : in bit;
A_NMI : in bit;
A_RS : in bit;
A_XF : out bit;
XIO : in bit;
SELA_B : inout bit;
HCS : inout bit;
HDS1 : inout bit;
HDS2 : inout bit;
HMODE : in bit;
HPIRS : in bit;
HRDY : inout bit;
HRNW : inout bit;
TMS : in bit;
TCK : in bit;
TDI : in bit;
TDO : out bit;
TRST : in bit;
EMU0 : in bit;
EMU1 : in bit;
CLKIN : in bit;
HOLDN : in bit;
HOLDAN : out bit;
TEST : linkage bit;
CVDD : linkage bit_vector(1 to 4);
DVDD : linkage bit_vector(1 to 3);
VSS : linkage bit_vector(1 to 9);
AVDD : linkage bit;
VSSA : linkage bit);
use STD_1149_1_1994.all; -- Get standard attributes and definitions
use TI_BIDIR.all; -- Get C54X BIDIR cell attributes
----------------------------------------------------------------------
-- This package type TI_BIDIR must be available to your toolset. --
-- In most cases this text should be placed in a separate file --
-- named 'TI_BIDIR' that can be referenced via the previous --
-- 'use TI_BIDIR.all' statement. --
--
-- package TI_BIDIR is
-- use STD_1149_1_1990.all;
-- constant BC_BIDIR : CELL_INFO;
-- end TI_BIDIR;
--
-- package body TI_BIDIR is
-- constant BC_BIDIR : CELL_INFO :=
-- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PI),
-- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI),
-- (BIDIR_IN, INTEST, PI), (BIDIR_OUT, INTEST, PI));
-- end TI_BIDIR;
----------------------------------------------------------------------
-- attribute BOUNDARY_CELLS of TMS320VC5421_cpu_A : entity is
-- "BC_1, BC_2, BC_BIDIR";
attribute COMPONENT_CONFORMANCE of TMS320VC5421_cpu_A: entity is "STD_1149_1_1993";
attribute PIN_MAP of TMS320VC5421_cpu_A : entity is PHYSICAL_PIN_MAP;
constant GGU : PIN_MAP_STRING :=
" HA:(C02,C10,N10,M10,B11,D10,A12,A13, "&
" B01,D04,N13,M13,K10,K11,B12,B13,C12,C13), "&
" HD:(A02,D03,A10,B10,B03,C03,A03,A01, "&
" N11,M11,L11,N12,L04,K04,M03,N02), "&
" A_BFSR2 : A04, " &
" CLKIN : A06, " &
" AVDD : A07, " &
" A_BDX2 : B04, " &
" A_BFSX2 : C04, " &
" A_BCLKR2 : C05, " &
" HRDY : C06, " &
" VSSA : C07, " &
" A_NMI : D01, " &
" A_INT1 : D02, " &
" A_BDR2 : D05, " &
" A_BCLKX2 : D06, " &
" HOLDN : D07, " &
" A_RS : E01, " &
" A_GPIO1 : E02, " &
" A_GPIO2 : E03, " &
" A_GPIO3 : E04, " &
" A_GPIO0 : F04, " &
" A_BDR1 : G01, " &
" A_BFSR1 : G02, " &
" A_BCLKR1 : G03, " &
" A_BFSX1 : G04, " &
" A_BDX1 : H03, " &
" A_BCLKX1 : H04, " &
" TEST : H10, " &
" A_XF : J01, " &
" A_CLKOUT : J02, " &
" HOLDAN : J03, " &
" TCK : J04, " &
" XIO : J13, " &
" TMS : K01, " &
" TDI : K02, " &
" TRST : K03, " &
" A_BCLKR0 : K05, " &
" A_BDX0 : K06, " &
" HRNW : K09, " &
" HPIRS : K12, " &
" HMODE : K13, " &
" EMU1 : L01, " &
" A_INT0 : L03, " &
" A_BFSX0 : L05, " &
" A_BCLKX0 : L06, " &
" SELA_B : L10, " &
" EMU0 : M01, " &
" TDO : M02, " &
" A_BFSR0 : M04, " &
" HCS : M06, " &
" HDS1 : M07, " &
" A_BDR0 : N04, " &
" HDS2 : N06, " &
" VSS: (B02,B05,B07,B09,C11,F02,F03,F13,G13), "&
" CVDD:(A05,A09,F01,F12), "&
" DVDD:(A11,B06,C01)" ;
-- *********************************************************
constant PGE : PIN_MAP_STRING :=
" HA:(3,114,65,66,111,113,110,109, "&
" 2,5,73,74,77,78,108,107,105,104), "&
" HD:(143,6,116,115,141,142,140,1, "&
" 68,69,70,71,42,41,39,38), "&
" A_BFSR2 :137, " &
" CLKIN :129, " &
" AVDD :126, " &
" A_BDX2 :138, " &
" A_BFSX2 :139, " &
" A_BCLKR2 :135, " &
" HRDY :131, " &
" VSSA :127, " &
" A_NMI :8, " &
" A_INT1 :7, " &
" A_BDR2 :136, " &
" A_BCLKX2 :132, " &
" HOLDN :128, " &
" A_RS :12, " &
" A_GPIO1 :11, " &
" A_GPIO2 :10, " &
" A_GPIO3 :9, " &
" A_GPIO0 :13, " &
" A_BDR1 :18, " &
" A_BFSR1 :17, " &
" A_BCLKR1 :19, " &
" A_BFSX1 :20, " &
" A_BDX1 :23, " &
" A_BCLKX1 :24, " &
" TEST :85, " &
" A_XF :25, " &
" A_CLKOUT :26, " &
" HOLDAN :27, " &
" TCK :28, " &
" XIO :84, " &
" TMS :29, " &
" TDI :30, " &
" TRST :31, " &
" A_BCLKR0 :45, " &
" A_BDX0 :49, " &
" HRNW :64, " &
" HPIRS :79, " &
" HMODE :80, " &
" EMU1 :32, " &
" A_INT0 :34, " &
" A_BFSX0 :46, " &
" A_BCLKX0 :50, " &
" SELA_B :67, " &
" EMU0 :35, " &
" TDO :36, " &
" A_BFSR0 :43, " &
" HCS :51, " &
" HDS1 :53, " &
" A_BDR0 :44, " &
" HDS2 :52, " &
" VSS: (14,15,22,37,40,47,57,62,72), "&
" CVDD:(16,21,48,61), "&
" DVDD:(4,33,56)";
-- *********************************************************
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRST : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (25.00e6, BOTH);
attribute COMPLIANCE_PATTERNS of TMS320VC5421_cpu_A : entity is "(EMU1,EMU0)(11)";
attribute INSTRUCTION_LENGTH of TMS320VC5421_cpu_A : entity is 8;
attribute INSTRUCTION_OPCODE of TMS320VC5421_cpu_A : entity is
"EXTEST (00000000), " &
"BYPASS (11111111), " &
"HIGHZ (00000110), " &
"SAMPLE (00000010) " ;
attribute INSTRUCTION_CAPTURE of TMS320VC5421_cpu_A : entity is "XXXXXX01";
attribute REGISTER_ACCESS of TMS320VC5421_cpu_A : entity is
"BOUNDARY (EXTEST, SAMPLE)," &
"BYPASS (BYPASS, HIGHZ) " ;
attribute BOUNDARY_LENGTH of TMS320VC5421_cpu_A: entity is 99;
attribute BOUNDARY_REGISTER of TMS320VC5421_cpu_A: entity is
----------------------------------------------------------------
-- CELL CELL PIN CELL CNTRL
-- # NAME ,NAME ,TYPE , ,CELL
----------------------------------------------------------------
"0 (BC_1 ,A_BDX2 ,OUTPUT3 ,X ,5 ,1 ,Z), " &
"1 (BC_BIDIR ,A_BFSX2 ,BIDIR ,X ,6 ,1 ,Z), " &
"2 (BC_BIDIR ,A_BFSR2 ,BIDIR ,X ,7 ,1 ,Z), " &
"3 (BC_BIDIR ,A_BCLKX2 ,BIDIR ,X ,8 ,1 ,Z), " &
"4 (BC_BIDIR ,A_BCLKR2 ,BIDIR ,X ,9 ,1 ,Z), " &
"5 (BC_1 ,* ,CONTROL ,1 ), " &
"6 (BC_1 ,* ,CONTROL ,1 ), " &
"7 (BC_1 ,* ,CONTROL ,1 ), " &
"8 (BC_1 ,* ,CONTROL ,1 ), " &
"9 (BC_1 ,* ,CONTROL ,1 ), " &
"10 (BC_2 ,A_BDR2 ,INPUT ,X ), " &
"11 (BC_1 ,A_BDX1 ,OUTPUT3 ,X ,16 ,1 ,Z), " &
"12 (BC_BIDIR ,A_BFSX1 ,BIDIR ,X ,17 ,1 ,Z), " &
"13 (BC_BIDIR ,A_BFSR1 ,BIDIR ,X ,18 ,1 ,Z), " &
"14 (BC_BIDIR ,A_BCLKX1 ,BIDIR ,X ,19 ,1 ,Z), " &
"15 (BC_BIDIR ,A_BCLKR1 ,BIDIR ,X ,20 ,1 ,Z), " &
"16 (BC_1 ,* ,CONTROL ,1 ), " &
"17 (BC_1 ,* ,CONTROL ,1 ), " &
"18 (BC_1 ,* ,CONTROL ,1 ), " &
"19 (BC_1 ,* ,CONTROL ,1 ), " &
"20 (BC_1 ,* ,CONTROL ,1 ), " &
"21 (BC_2 ,A_BDR1 ,INPUT ,X ), " &
"22 (BC_1 ,A_BDX0 ,OUTPUT3 ,X ,27 ,1 ,Z), " &
"23 (BC_BIDIR ,A_BFSX0 ,BIDIR ,X ,28 ,1 ,Z), " &
"24 (BC_BIDIR ,A_BFSR0 ,BIDIR ,X ,29 ,1 ,Z), " &
"25 (BC_BIDIR ,A_BCLKX0 ,BIDIR ,X ,30 ,1 ,Z), " &
"26 (BC_BIDIR ,A_BCLKR0 ,BIDIR ,X ,31 ,1 ,Z), " &
"27 (BC_1 ,* ,CONTROL ,1 ), " &
"28 (BC_1 ,* ,CONTROL ,1 ), " &
"29 (BC_1 ,* ,CONTROL ,1 ), " &
"30 (BC_1 ,* ,CONTROL ,1 ), " &
"31 (BC_1 ,* ,CONTROL ,1 ), " &
"32 (BC_2 ,A_BDR0 ,INPUT ,X ), " &
"33 (BC_1 ,A_XF ,OUTPUT3 ,X ,43 ,1 ,Z), " &
"34 (BC_1 ,A_CLKOUT ,OUTPUT3 ,X ,43 ,1 ,Z), " &
"35 (BC_BIDIR ,A_GPIO0 ,BIDIR ,X ,39 ,1 ,Z), " &
"36 (BC_BIDIR ,A_GPIO1 ,BIDIR ,X ,40 ,1 ,Z), " &
"37 (BC_BIDIR ,A_GPIO2 ,BIDIR ,X ,41 ,1 ,Z), " &
"38 (BC_BIDIR ,A_GPIO3 ,BIDIR ,X ,42 ,1 ,Z), " &
"39 (BC_1 ,* ,CONTROL ,1 ), " &
"40 (BC_1 ,* ,CONTROL ,1 ), " &
"41 (BC_1 ,* ,CONTROL ,1 ), " &
"42 (BC_1 ,* ,CONTROL ,1 ), " &
"43 (BC_1 ,* ,CONTROL ,1 ), " &
"44 (BC_2 ,A_INT1 ,INPUT ,X ), " &
"45 (BC_2 ,A_INT0 ,INPUT ,X ), " &
"46 (BC_2 ,A_NMI ,INPUT ,X ), " &
"47 (BC_2 ,A_RS ,INPUT ,X ), " &
"48 (BC_BIDIR ,HD(0) ,BIDIR ,X ,91 ,1 ,Z), " &
"49 (BC_BIDIR ,HD(1) ,BIDIR ,X ,91 ,1 ,Z), " &
"50 (BC_BIDIR ,HD(2) ,BIDIR ,X ,91 ,1 ,Z), " &
"51 (BC_BIDIR ,HD(3) ,BIDIR ,X ,91 ,1 ,Z), " &
"52 (BC_BIDIR ,HD(4) ,BIDIR ,X ,91 ,1 ,Z), " &
"53 (BC_BIDIR ,HD(5) ,BIDIR ,X ,91 ,1 ,Z), " &
"54 (BC_BIDIR ,HD(6) ,BIDIR ,X ,91 ,1 ,Z), " &
"55 (BC_BIDIR ,HD(7) ,BIDIR ,X ,91 ,1 ,Z), " &
"56 (BC_BIDIR ,HD(8) ,BIDIR ,X ,91 ,1 ,Z), " &
"57 (BC_BIDIR ,HD(9) ,BIDIR ,X ,91 ,1 ,Z), " &
"58 (BC_BIDIR ,HD(10) ,BIDIR ,X ,91 ,1 ,Z), " &
"59 (BC_BIDIR ,HD(11) ,BIDIR ,X ,91 ,1 ,Z), " &
"60 (BC_BIDIR ,HD(12) ,BIDIR ,X ,91 ,1 ,Z), " &
"61 (BC_BIDIR ,HD(13) ,BIDIR ,X ,91 ,1 ,Z), " &
"62 (BC_BIDIR ,HD(14) ,BIDIR ,X ,91 ,1 ,Z), " &
"63 (BC_BIDIR ,HD(15) ,BIDIR ,X ,91 ,1 ,Z), " &
"64 (BC_BIDIR ,HA(0) ,BIDIR ,X ,90 ,1 ,Z), " &
"65 (BC_BIDIR ,HA(1) ,BIDIR ,X ,89 ,1 ,Z), " &
"66 (BC_BIDIR ,HA(2) ,BIDIR ,X ,93 ,1 ,Z), " &
"67 (BC_BIDIR ,HA(3) ,BIDIR ,X ,93 ,1 ,Z), " &
"68 (BC_BIDIR ,HA(4) ,BIDIR ,X ,93 ,1 ,Z), " &
"69 (BC_BIDIR ,HA(5) ,BIDIR ,X ,93 ,1 ,Z), " &
"70 (BC_BIDIR ,HA(6) ,BIDIR ,X ,93 ,1 ,Z), " &
"71 (BC_BIDIR ,HA(7) ,BIDIR ,X ,93 ,1 ,Z), " &
"72 (BC_BIDIR ,HA(8) ,BIDIR ,X ,93 ,1 ,Z), " &
"73 (BC_BIDIR ,HA(9) ,BIDIR ,X ,93 ,1 ,Z), " &
"74 (BC_BIDIR ,HA(10) ,BIDIR ,X ,93 ,1 ,Z), " &
"75 (BC_BIDIR ,HA(11) ,BIDIR ,X ,93 ,1 ,Z), " &
"76 (BC_BIDIR ,HA(12) ,BIDIR ,X ,93 ,1 ,Z), " &
"77 (BC_BIDIR ,HA(13) ,BIDIR ,X ,93 ,1 ,Z), " &
"78 (BC_BIDIR ,HA(14) ,BIDIR ,X ,93 ,1 ,Z), " &
"79 (BC_BIDIR ,HA(15) ,BIDIR ,X ,93 ,1 ,Z), " &
"80 (BC_BIDIR ,HA(16) ,BIDIR ,X ,93 ,1 ,Z), " &
"81 (BC_BIDIR ,HA(17) ,BIDIR ,X ,93 ,1 ,Z), " &
"82 (BC_BIDIR ,HDS1 ,BIDIR ,X ,93 ,1 ,Z), " &
"83 (BC_BIDIR ,HDS2 ,BIDIR ,X ,93 ,1 ,Z), " &
"84 (BC_BIDIR ,HCS ,BIDIR ,X ,93 ,1 ,Z), " &
"85 (BC_BIDIR ,HRNW ,BIDIR ,X ,93 ,1 ,Z), " &
"86 (BC_BIDIR ,HRDY ,BIDIR ,X ,92 ,1 ,Z), " &
"87 (BC_BIDIR ,SELA_B ,BIDIR ,X ,93 ,1 ,Z), " &
"88 (BC_1 ,HOLDAN ,OUTPUT3 ,X ,43 ,1 ,Z), " &
"89 (BC_1 ,* ,CONTROL ,1 ), " &
"90 (BC_1 ,* ,CONTROL ,1 ), " &
"91 (BC_1 ,* ,CONTROL ,1 ), " &
"92 (BC_1 ,* ,CONTROL ,1 ), " &
"93 (BC_1 ,* ,CONTROL ,1 ), " &
"94 (BC_2 ,HPIRS ,INPUT ,X ), " &
"95 (BC_2 ,HMODE ,INPUT ,X ), " &
"96 (BC_2 ,XIO ,INPUT ,X ), " &
"97 (BC_2 ,HOLDN ,INPUT ,X ), " &
"98 (BC_2 ,CLKIN ,INPUT ,X ) " ;
end TMS320VC5421_cpu_A;