-- *********************************************************************** -- BSDL file for design IDT82P2281 -- Created by Synopsys Version 1999.10 (Sep 02, 1999) -- Designer: H. Pu -- Company: Integrated Devices Technolgy, Inc. -- Date: Thu Sep 4 11:17:16 2003 -- *********************************************************************** entity IDT82P2281 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "TQFP80"); -- This section declares all the ports in the design. port ( CSB : in bit; DSB_RDB : in bit; MPM : in bit; OSCI : in bit; REF_IN_1544 : in bit; REF_IN_2048 : in bit; RESETB : in bit; RWB_WRB : in bit; SPIEN : in bit; TCK : in bit; TDI : in bit; THZ : in bit; TMS : in bit; TRSTB : in bit; TSD : in bit; TSIG : in bit; A : in bit_vector (0 to 7); CLK_SEL : in bit_vector (0 to 2); GPIO : inout bit; RSCK : inout bit; RSFS : inout bit; TSCK : inout bit; TSFS : inout bit; D : inout bit_vector (0 to 7); INTB : out bit; RSD : out bit; RSIG : out bit; TDO : out bit; CLK_GEN : buffer bit; RefA_OUT : buffer bit; TEST_SO : buffer bit; GNDAB : linkage bit; GNDAP : linkage bit; GNDAR : linkage bit; GNDAT : linkage bit; GNDAX : linkage bit; GNDDC0 : linkage bit; GNDDC1 : linkage bit; GNDDC2 : linkage bit; GNDDC3 : linkage bit; GNDDIO0 : linkage bit; GNDDIO1 : linkage bit; GNDDIO2 : linkage bit; VDDAB : linkage bit; VDDAP : linkage bit; VDDAR : linkage bit; VDDAT : linkage bit; VDDAX : linkage bit; VDDDC0 : linkage bit; VDDDC1 : linkage bit; VDDDC2 : linkage bit; VDDDC3 : linkage bit; VDDDIO0 : linkage bit; VDDDIO1 : linkage bit; VDDDIO2 : linkage bit; NC : linkage bit_vector (1 to 9) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of IDT82P2281: entity is "STD_1149_1_1993"; attribute PIN_MAP of IDT82P2281: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant TQFP80: PIN_MAP_STRING := "CSB : P38," & "DSB_RDB : P36," & "MPM : P22," & "OSCI : P75," & "REF_IN_1544 : P63," & "REF_IN_2048 : P62," & "RESETB : P64," & "RWB_WRB : P37," & "SPIEN : P23," & "TCK : P78," & "TDI : P79," & "THZ : P2," & "TMS : P80," & "TRSTB : P77," & "TSD : P55," & "TSIG : P54," & "A : (P41, P42, P43, P44, P45, P46, P49, P51)," & "CLK_SEL : (P65, P66, P67)," & "GPIO : P1," & "RSCK : P60," & "RSFS : P57," & "TSCK : P56," & "TSFS : P53," & "D : (P24, P25, P26, P27, P28, P29, P31, P33)," & "INTB : P39," & "RSD : P59," & "RSIG : P58," & "TDO : P76," & "CLK_GEN : P61," & "RefA_OUT : P70," & "TEST_SO : P72," & "GNDAB : P7," & "GNDAP : P5," & "GNDAR : P19," & "GNDAT : P14," & "GNDAX : P13," & "GNDDC0 : P68," & "GNDDC1 : P35," & "GNDDC2 : P47," & "GNDDC3 : P4," & "GNDDIO0 : P69," & "GNDDIO1 : P34," & "GNDDIO2 : P48," & "VDDAB : P8," & "VDDAP : P6," & "VDDAR : P16," & "VDDAT : P15," & "VDDAX : P10," & "VDDDC0 : P71," & "VDDDC1 : P32," & "VDDDC2 : P50," & "VDDDC3 : P3," & "VDDDIO0 : P73," & "VDDDIO1 : P30," & "VDDDIO2 : P52," & "NC : (P9, P11, P12, P17, P18, P20, P21, P40, P74)"; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRSTB: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of IDT82P2281: entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of IDT82P2281: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (010)," & "CLAMP (011)," & "HIGHZ (100)," & "USER1 (110)," & "IDCODE (001)," & "USER2 (101)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of IDT82P2281: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of IDT82P2281: entity is "0000" & -- 4-bit version number "0000010010111011" & -- 16-bit part number "00000110011" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of IDT82P2281: entity is "BYPASS (BYPASS, CLAMP, HIGHZ, USER1)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)," & "UTDR1[20] (USER2)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of IDT82P2281: entity is 77; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of IDT82P2281: entity is -- -- num cell port function safe [ccell disval rslt] -- "76 (BC_4, OSCI, observe_only, X), " & "75 (BC_1, TEST_SO, output2, X), " & "74 (BC_1, RefA_OUT, output2, X), " & "73 (BC_4, CLK_SEL(2), observe_only, X), " & "72 (BC_4, CLK_SEL(1), observe_only, X), " & "71 (BC_4, CLK_SEL(0), observe_only, X), " & "70 (BC_4, RESETB, observe_only, X), " & "69 (BC_4, REF_IN_1544, observe_only, X), " & "68 (BC_4, REF_IN_2048, observe_only, X), " & "67 (BC_1, CLK_GEN, output2, X), " & "66 (BC_1, *, controlr, 1), " & "65 (BC_4, RSCK, observe_only, X), " & "64 (BC_1, RSCK, output3, X, 66, 1, Z)," & "63 (BC_1, *, controlr, 1), " & "62 (BC_1, RSD, output3, X, 63, 1, Z), " & "61 (BC_1, RSIG, output3, X, 63, 1, Z), " & "60 (BC_4, RSFS, observe_only, X), " & "59 (BC_1, RSFS, output3, X, 66, 1, Z)," & "58 (BC_1, *, controlr, 1), " & "57 (BC_4, TSCK, observe_only, X), " & "56 (BC_1, TSCK, output3, X, 58, 1, Z)," & "55 (BC_4, TSD, observe_only, X), " & "54 (BC_4, TSIG, observe_only, X), " & "53 (BC_4, TSFS, observe_only, X), " & "52 (BC_1, TSFS, output3, X, 58, 1, Z)," & "51 (BC_0, *, internal, X), " & "50 (BC_0, *, internal, X), " & "49 (BC_0, *, internal, X), " & "48 (BC_0, *, internal, X), " & "47 (BC_0, *, internal, X), " & "46 (BC_0, *, internal, X), " & "45 (BC_0, *, internal, X), " & "44 (BC_0, *, internal, X), " & "43 (BC_0, *, internal, X), " & "42 (BC_0, *, internal, X), " & "41 (BC_0, *, internal, X), " & "40 (BC_0, *, internal, X), " & "39 (BC_0, *, internal, X), " & "38 (BC_0, *, internal, X), " & "37 (BC_0, *, internal, X), " & "36 (BC_0, *, internal, X), " & "35 (BC_4, A(7), observe_only, X), " & "34 (BC_4, A(6), observe_only, X), " & "33 (BC_4, A(5), observe_only, X), " & "32 (BC_4, A(4), observe_only, X), " & "31 (BC_4, A(3), observe_only, X), " & "30 (BC_4, A(2), observe_only, X), " & "29 (BC_4, A(1), observe_only, X), " & "28 (BC_4, A(0), observe_only, X), " & "27 (BC_1, *, control, 1), " & "26 (BC_1, INTB, output3, X, 27, 1, Z), " & "25 (BC_4, CSB, observe_only, X), " & "24 (BC_4, RWB_WRB, observe_only, X), " & "23 (BC_4, DSB_RDB, observe_only, X), " & "22 (BC_1, *, control, 1), " & "21 (BC_4, D(7), observe_only, X), " & "20 (BC_1, D(7), output3, X, 22, 1, Z), " & "19 (BC_4, D(6), observe_only, X), " & "18 (BC_1, D(6), output3, X, 22, 1, Z), " & "17 (BC_4, D(5), observe_only, X), " & "16 (BC_1, D(5), output3, X, 22, 1, Z), " & "15 (BC_4, D(4), observe_only, X), " & "14 (BC_1, D(4), output3, X, 22, 1, Z), " & "13 (BC_4, D(3), observe_only, X), " & "12 (BC_1, D(3), output3, X, 22, 1, Z), " & "11 (BC_4, D(2), observe_only, X), " & "10 (BC_1, D(2), output3, X, 22, 1, Z), " & "9 (BC_4, D(1), observe_only, X), " & "8 (BC_1, D(1), output3, X, 22, 1, Z), " & "7 (BC_4, D(0), observe_only, X), " & "6 (BC_1, D(0), output3, X, 22, 1, Z), " & "5 (BC_4, SPIEN, observe_only, X), " & "4 (BC_4, MPM, observe_only, X), " & "3 (BC_4, THZ, observe_only, X), " & "2 (BC_1, *, control, 1), " & "1 (BC_4, GPIO, observe_only, X), " & "0 (BC_1, GPIO, output3, X, 2, 1, Z)"; end IDT82P2281;