-- ***************************************************************************** -- BSDL file for design S028_package_4ch -- Created by Synopsys Version 2003.06-SP1-3 (Dec 03, 2003) -- Designer: -- Company: -- Date: Tue Apr 18 14:15:45 2006 -- ***************************************************************************** entity S028_package_4ch is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "BB204"); -- This section declares all the ports in the design. port ( A0 : in bit; A1 : in bit; A2 : in bit; A3 : in bit; A4 : in bit; A5 : in bit; A6 : in bit; A7 : in bit; BIST_MODE : in bit; CSB : in bit; DSB_RDB : in bit; IDDQ_MODE : in bit; MPM : in bit; RSCCK : in bit; RSCFS : in bit; RSCK1 : in bit; RSCK2 : in bit; RSCK3 : in bit; RSCK4 : in bit; IC1 : in bit; IC4 : in bit; IC7 : in bit; IC10 : in bit; RSD1 : in bit; RSD2 : in bit; RSD3 : in bit; RSD4 : in bit; IC0 : in bit; IC3 : in bit; IC6 : in bit; IC9 : in bit; RSF1 : in bit; RSF2 : in bit; RSF3 : in bit; RSF4 : in bit; IC2 : in bit; IC5 : in bit; IC8 : in bit; IC11 : in bit; RSTB : in bit; R_WB_WRB : in bit; SCAN_MODE : in bit; SYSCLK : in bit; TCK : in bit; TDI : in bit; TEST_MODE1 : in bit; TEST_MODE2 : in bit; TEST_MODE3 : in bit; TEST_SE : in bit; TMS : in bit; TRSTB : in bit; TSCCK : in bit; TSCFS : in bit; TSCK1 : in bit; TSCK2 : in bit; TSCK3 : in bit; TSCK4 : in bit; IC23 : in bit; IC22 : in bit; IC21 : in bit; IC20 : in bit; TSF1 : in bit; TSF2 : in bit; TSF3 : in bit; TSF4 : in bit; IC15 : in bit; IC14 : in bit; IC13 : in bit; IC12 : in bit; UART_CTSB : in bit; UART_RD : in bit; URA0 : in bit; URA1 : in bit; URA2 : in bit; URA3 : in bit; URA4 : in bit; URCLK : in bit; URENB : in bit; UTA0 : in bit; UTA1 : in bit; UTA2 : in bit; UTA3 : in bit; UTA4 : in bit; UTCLK : in bit; UTD0 : in bit; UTD1 : in bit; UTD2 : in bit; UTD3 : in bit; UTD4 : in bit; UTD5 : in bit; UTD6 : in bit; UTD7 : in bit; UTENB : in bit; UTSOC : in bit; D0 : inout bit; D1 : inout bit; D2 : inout bit; D3 : inout bit; D4 : inout bit; D5 : inout bit; D6 : inout bit; D7 : inout bit; EM_D0 : inout bit; EM_D1 : inout bit; EM_D2 : inout bit; EM_D3 : inout bit; EM_D4 : inout bit; EM_D5 : inout bit; EM_D6 : inout bit; EM_D7 : inout bit; INTB : out bit; TDO : out bit; URCLAV : out bit; URD0 : out bit; URD1 : out bit; URD2 : out bit; URD3 : out bit; URD4 : out bit; URD5 : out bit; URD6 : out bit; URD7 : out bit; URSOC : out bit; UTCLAV : out bit; BIST_DONE : buffer bit; BIST_ERROR : buffer bit; EM_A0 : buffer bit; EM_A1 : buffer bit; EM_A10 : buffer bit; EM_A11 : buffer bit; EM_A12 : buffer bit; EM_A13 : buffer bit; EM_A14 : buffer bit; EM_A15 : buffer bit; EM_A16 : buffer bit; EM_A17 : buffer bit; EM_A18 : buffer bit; EM_A2 : buffer bit; EM_A3 : buffer bit; EM_A4 : buffer bit; EM_A5 : buffer bit; EM_A6 : buffer bit; EM_A7 : buffer bit; EM_A8 : buffer bit; EM_A9 : buffer bit; EM_CSB : buffer bit; EM_OEB : buffer bit; EM_WEB : buffer bit; TSD1 : buffer bit; TSD2 : buffer bit; TSD3 : buffer bit; TSD4 : buffer bit; IC19 : buffer bit; IC18 : buffer bit; IC17 : buffer bit; IC16 : buffer bit; UART_RTSB : buffer bit; UART_TD : buffer bit; GND : linkage bit_vector (1 to 28); NC : linkage bit_vector (1 to 3); VDD : linkage bit_vector (1 to 20) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of S028_package_4ch: entity is "STD_1149_1_1993"; attribute PIN_MAP of S028_package_4ch: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information is -- extracted from the port-to-pin map file that was read in using the -- "read_pin_map" command. constant BB204: PIN_MAP_STRING := "A0 : P16," & "A1 : N12," & "A2 : N13," & "A3 : N14," & "A4 : N15," & "A5 : N16," & "A6 : M13," & "A7 : M14," & "BIST_MODE : A2," & "CSB : L13," & "DSB_RDB : M15," & "IDDQ_MODE : D3," & "MPM : P15," & "RSCCK : N3," & "RSCFS : N2," & "RSCK1 : E1," & "RSCK2 : F1," & "RSCK3 : G1," & "RSCK4 : H1," & "IC1 : J3," & "IC4 : K3," & "IC7 : L3," & "IC10 : M3," & "RSD1 : E2," & "RSD2 : F2," & "RSD3 : G2," & "RSD4 : H2," & "IC0 : J2," & "IC3 : K2," & "IC6 : L2," & "IC9 : M2," & "RSF1 : F3," & "RSF2 : G3," & "RSF3 : H3," & "RSF4 : J1," & "IC2 : K1," & "IC5 : L1," & "IC8 : M1," & "IC11 : N1," & "RSTB : R11," & "R_WB_WRB : M16," & "SCAN_MODE : P11," & "SYSCLK : E4," & "TCK : C2," & "TDI : B2," & "TEST_MODE1 : C3," & "TEST_MODE2 : B3," & "TEST_MODE3 : A3," & "TEST_SE : T12," & "TMS : B1," & "TRSTB : C1," & "TSCCK : P1," & "TSCFS : P2," & "TSCK1 : P10," & "TSCK2 : P9," & "TSCK3 : T8," & "TSCK4 : T7," & "IC23 : T6," & "IC22 : T5," & "IC21 : T4," & "IC20 : T3," & "TSF1 : T11," & "TSF2 : T10," & "TSF3 : T9," & "TSF4 : P8," & "IC15 : P7," & "IC14 : P6," & "IC13 : P5," & "IC12 : P4," & "UART_CTSB : L15," & "UART_RD : L16," & "URA0 : D14," & "URA1 : D13," & "URA2 : C16," & "URA3 : C15," & "URA4 : C14," & "URCLK : D16," & "URENB : D15," & "UTA0 : E15," & "UTA1 : E16," & "UTA2 : F13," & "UTA3 : F14," & "UTA4 : F15," & "UTCLK : E14," & "UTD0 : J14," & "UTD1 : J15," & "UTD2 : J16," & "UTD3 : H16," & "UTD4 : H15," & "UTD5 : H14," & "UTD6 : G16," & "UTD7 : G15," & "UTENB : G14," & "UTSOC : F16," & "D0 : T14," & "D1 : T15," & "D2 : R13," & "D3 : R14," & "D4 : R15," & "D5 : R16," & "D6 : P13," & "D7 : P14," & "EM_D0 : A5," & "EM_D1 : B5," & "EM_D2 : C5," & "EM_D3 : D5," & "EM_D4 : A4," & "EM_D5 : B4," & "EM_D6 : C4," & "EM_D7 : D4," & "INTB : R12," & "TDO : D2," & "URCLAV : B16," & "URD0 : C12," & "URD1 : D12," & "URD2 : A13," & "URD3 : B13," & "URD4 : C13," & "URD5 : A14," & "URD6 : B14," & "URD7 : A15," & "URSOC : B15," & "UTCLAV : E13," & "BIST_DONE : K16," & "BIST_ERROR : K15," & "EM_A0 : B12," & "EM_A1 : A12," & "EM_A10 : B9," & "EM_A11 : A9," & "EM_A12 : A8," & "EM_A13 : B8," & "EM_A14 : C8," & "EM_A15 : A7," & "EM_A16 : B7," & "EM_A17 : C7," & "EM_A18 : A6," & "EM_A2 : D11," & "EM_A3 : C11," & "EM_A4 : B11," & "EM_A5 : A11," & "EM_A6 : C10," & "EM_A7 : B10," & "EM_A8 : A10," & "EM_A9 : C9," & "EM_CSB : C6," & "EM_OEB : B6," & "EM_WEB : D6," & "TSD1 : R10," & "TSD2 : R9," & "TSD3 : R8," & "TSD4 : R7," & "IC19 : R6," & "IC18 : R5," & "IC17 : R4," & "IC16 : R3," & "UART_RTSB : K14," & "UART_TD : L14," & "GND : (A1, T1, H4, J4, G7, H7, J7, K7, D8, G8, H8, J8, K8, " & "N8, D9, G9, H9, J9, K9, N9, G10, H10, J10, K10, H13, J13, A16, T16)" & "," & "NC : (D1, R2, T13)," & "VDD : (R1, T2, E3, P3, P12, F4, G4, K4, L4, M4, N4, N5, N6, " & "D7, N7, D10, N10, N11, G13, K13)"; -- This section specifies the TAP ports. For the TAP TCK port, the parameters in -- the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRSTB: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of S028_package_4ch: entity is 3; -- Specifies the boundary-scan instructions implemented in the design and their -- opcodes. attribute INSTRUCTION_OPCODE of S028_package_4ch: entity is "BYPASS (111, 011, 110)," & "EXTEST (000)," & "SAMPLE (010)," & "CLAMP (100)," & "HIGHZ (101)," & "IDCODE (001)"; -- Specifies the bit pattern that is loaded into the instruction register when -- the TAP controller passes through the Capture-IR state. The standard mandates -- that the two LSBs must be "01". The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of S028_package_4ch: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID register during -- the IDCODE instruction when the TAP controller passes through the Capture-DR -- state. attribute IDCODE_REGISTER of S028_package_4ch: entity is "0001" & -- 4-bit version number "0000010010111000" & -- 16-bit part number "00000110011" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI and TDO for -- each implemented instruction. attribute REGISTER_ACCESS of S028_package_4ch: entity is "BYPASS (BYPASS, CLAMP, HIGHZ)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of S028_package_4ch: entity is 224; -- The following list specifies the characteristics of each cell in the boundary -- scan register from TDI to TDO. The following is a description of the label -- fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not have a port -- name. -- function: Is the function of the cell as defined by the standard. Is one -- of input, output2, output3, bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be loaded with -- for safe operation when the software might otherwise choose a -- random value. -- ccell : The control cell number. Specifies the control cell that -- drives the output enable for this port. -- disval : Specifies the value that is loaded into the control cell to -- disable the output enable for the corresponding port. -- rslt : Resulting state. Shows the state of the driver when it is -- disabled. attribute BOUNDARY_REGISTER of S028_package_4ch: entity is -- -- num cell port function safe [ccell disval rslt] -- "223 (BC_4, BIST_MODE, observe_only, X), " & "222 (BC_4, IDDQ_MODE, observe_only, X), " & "221 (BC_4, TEST_MODE1, observe_only, X), " & "220 (BC_4, TEST_MODE2, observe_only, X), " & "219 (BC_4, TEST_MODE3, observe_only, X), " & "218 (BC_4, SYSCLK, observe_only, X), " & "217 (BC_1, *, control, 1), " & "216 (BC_4, EM_D7, observe_only, X), " & "215 (BC_1, EM_D7, output3, X, 217, 1, Z), " & "214 (BC_4, EM_D6, observe_only, X), " & "213 (BC_1, EM_D6, output3, X, 217, 1, Z), " & "212 (BC_4, EM_D5, observe_only, X), " & "211 (BC_1, EM_D5, output3, X, 217, 1, Z), " & "210 (BC_4, EM_D4, observe_only, X), " & "209 (BC_1, EM_D4, output3, X, 217, 1, Z), " & "208 (BC_4, EM_D3, observe_only, X), " & "207 (BC_1, EM_D3, output3, X, 217, 1, Z), " & "206 (BC_4, EM_D2, observe_only, X), " & "205 (BC_1, EM_D2, output3, X, 217, 1, Z), " & "204 (BC_4, EM_D1, observe_only, X), " & "203 (BC_1, EM_D1, output3, X, 217, 1, Z), " & "202 (BC_4, EM_D0, observe_only, X), " & "201 (BC_1, EM_D0, output3, X, 217, 1, Z), " & "200 (BC_1, EM_WEB, output2, X), " & "199 (BC_1, EM_CSB, output2, X), " & "198 (BC_1, EM_OEB, output2, X), " & "197 (BC_0, *, internal, X), " & "196 (BC_1, EM_A18, output2, X), " & "195 (BC_1, EM_A17, output2, X), " & "194 (BC_1, EM_A16, output2, X), " & "193 (BC_1, EM_A15, output2, X), " & "192 (BC_1, EM_A14, output2, X), " & "191 (BC_1, EM_A13, output2, X), " & "190 (BC_1, EM_A12, output2, X), " & "189 (BC_1, EM_A11, output2, X), " & "188 (BC_1, EM_A10, output2, X), " & "187 (BC_1, EM_A9, output2, X), " & "186 (BC_1, EM_A8, output2, X), " & "185 (BC_1, EM_A7, output2, X), " & "184 (BC_1, EM_A6, output2, X), " & "183 (BC_1, EM_A5, output2, X), " & "182 (BC_1, EM_A4, output2, X), " & "181 (BC_1, EM_A3, output2, X), " & "180 (BC_1, EM_A2, output2, X), " & "179 (BC_1, EM_A1, output2, X), " & "178 (BC_1, EM_A0, output2, X), " & "177 (BC_1, *, control, 1), " & "176 (BC_1, URD0, output3, X, 177, 1, Z), " & "175 (BC_1, URD1, output3, X, 177, 1, Z), " & "174 (BC_1, URD2, output3, X, 177, 1, Z), " & "173 (BC_1, URD3, output3, X, 177, 1, Z), " & "172 (BC_1, URD4, output3, X, 177, 1, Z), " & "171 (BC_1, URD5, output3, X, 177, 1, Z), " & "170 (BC_1, URD6, output3, X, 177, 1, Z), " & "169 (BC_1, URD7, output3, X, 177, 1, Z), " & "168 (BC_1, *, control, 1), " & "167 (BC_1, URSOC, output3, X, 168, 1, Z), " & "166 (BC_1, *, control, 1), " & "165 (BC_1, URCLAV, output3, X, 166, 1, Z), " & "164 (BC_4, URA4, observe_only, X), " & "163 (BC_4, URA3, observe_only, X), " & "162 (BC_4, URA2, observe_only, X), " & "161 (BC_4, URA1, observe_only, X), " & "160 (BC_4, URA0, observe_only, X), " & "159 (BC_4, URENB, observe_only, X), " & "158 (BC_4, URCLK, observe_only, X), " & "157 (BC_1, *, control, 1), " & "156 (BC_1, UTCLAV, output3, X, 157, 1, Z), " & "155 (BC_4, UTCLK, observe_only, X), " & "154 (BC_4, UTA0, observe_only, X), " & "153 (BC_4, UTA1, observe_only, X), " & "152 (BC_4, UTA2, observe_only, X), " & "151 (BC_4, UTA3, observe_only, X), " & "150 (BC_4, UTA4, observe_only, X), " & "149 (BC_4, UTSOC, observe_only, X), " & "148 (BC_4, UTENB, observe_only, X), " & "147 (BC_4, UTD7, observe_only, X), " & "146 (BC_4, UTD6, observe_only, X), " & "145 (BC_4, UTD5, observe_only, X), " & "144 (BC_4, UTD4, observe_only, X), " & "143 (BC_4, UTD3, observe_only, X), " & "142 (BC_4, UTD2, observe_only, X), " & "141 (BC_4, UTD1, observe_only, X), " & "140 (BC_4, UTD0, observe_only, X), " & "139 (BC_1, BIST_DONE, output2, X), " & "138 (BC_1, BIST_ERROR, output2, X), " & "137 (BC_1, UART_RTSB, output2, X), " & "136 (BC_4, UART_RD, observe_only, X), " & "135 (BC_4, UART_CTSB, observe_only, X), " & "134 (BC_1, UART_TD, output2, X), " & "133 (BC_4, CSB, observe_only, X), " & "132 (BC_4, R_WB_WRB, observe_only, X), " & "131 (BC_4, DSB_RDB, observe_only, X), " & "130 (BC_4, A7, observe_only, X), " & "129 (BC_4, A6, observe_only, X), " & "128 (BC_4, A5, observe_only, X), " & "127 (BC_4, A4, observe_only, X), " & "126 (BC_4, A3, observe_only, X), " & "125 (BC_4, A2, observe_only, X), " & "124 (BC_4, A1, observe_only, X), " & "123 (BC_4, A0, observe_only, X), " & "122 (BC_4, MPM, observe_only, X), " & "121 (BC_1, *, control, 1), " & "120 (BC_4, D7, observe_only, X), " & "119 (BC_1, D7, output3, X, 121, 1, Z), " & "118 (BC_4, D6, observe_only, X), " & "117 (BC_1, D6, output3, X, 121, 1, Z), " & "116 (BC_4, D5, observe_only, X), " & "115 (BC_1, D5, output3, X, 121, 1, Z), " & "114 (BC_4, D4, observe_only, X), " & "113 (BC_1, D4, output3, X, 121, 1, Z), " & "112 (BC_4, D3, observe_only, X), " & "111 (BC_1, D3, output3, X, 121, 1, Z), " & "110 (BC_4, D2, observe_only, X), " & "109 (BC_1, D2, output3, X, 121, 1, Z), " & "108 (BC_4, D1, observe_only, X), " & "107 (BC_1, D1, output3, X, 121, 1, Z), " & "106 (BC_4, D0, observe_only, X), " & "105 (BC_1, D0, output3, X, 121, 1, Z), " & "104 (BC_1, *, control, 1), " & "103 (BC_1, INTB, output3, X, 104, 1, Z), " & "102 (BC_4, TEST_SE, observe_only, X), " & "101 (BC_4, SCAN_MODE, observe_only, X), " & "100 (BC_4, RSTB, observe_only, X), " & "99 (BC_4, TSF1, observe_only, X), " & "98 (BC_4, TSCK1, observe_only, X), " & "97 (BC_1, TSD1, output2, X), " & "96 (BC_0, *, internal, X), " & "95 (BC_0, *, internal, X), " & "94 (BC_0, *, internal, X), " & "93 (BC_4, TSF2, observe_only, X), " & "92 (BC_4, TSCK2, observe_only, X), " & "91 (BC_1, TSD2, output2, X), " & "90 (BC_0, *, internal, X), " & "89 (BC_0, *, internal, X), " & "88 (BC_0, *, internal, X), " & "87 (BC_4, TSF3, observe_only, X), " & "86 (BC_4, TSCK3, observe_only, X), " & "85 (BC_1, TSD3, output2, X), " & "84 (BC_0, *, internal, X), " & "83 (BC_0, *, internal, X), " & "82 (BC_0, *, internal, X), " & "81 (BC_4, TSF4, observe_only, X), " & "80 (BC_4, TSCK4, observe_only, X), " & "79 (BC_1, TSD4, output2, X), " & "78 (BC_0, *, internal, X), " & "77 (BC_0, *, internal, X), " & "76 (BC_0, *, internal, X), " & "75 (BC_4, IC15, observe_only, X), " & "74 (BC_4, IC23, observe_only, X), " & "73 (BC_1, IC19, output2, X), " & "72 (BC_0, *, internal, X), " & "71 (BC_0, *, internal, X), " & "70 (BC_0, *, internal, X), " & "69 (BC_4, IC14, observe_only, X), " & "68 (BC_4, IC22, observe_only, X), " & "67 (BC_1, IC18, output2, X), " & "66 (BC_0, *, internal, X), " & "65 (BC_0, *, internal, X), " & "64 (BC_0, *, internal, X), " & "63 (BC_4, IC13, observe_only, X), " & "62 (BC_4, IC21, observe_only, X), " & "61 (BC_1, IC17, output2, X), " & "60 (BC_0, *, internal, X), " & "59 (BC_0, *, internal, X), " & "58 (BC_0, *, internal, X), " & "57 (BC_4, IC12, observe_only, X), " & "56 (BC_4, IC20, observe_only, X), " & "55 (BC_1, IC16, output2, X), " & "54 (BC_0, *, internal, X), " & "53 (BC_0, *, internal, X), " & "52 (BC_0, *, internal, X), " & "51 (BC_4, TSCFS, observe_only, X), " & "50 (BC_4, TSCCK, observe_only, X), " & "49 (BC_4, RSCCK, observe_only, X), " & "48 (BC_4, RSCFS, observe_only, X), " & "47 (BC_0, *, internal, X), " & "46 (BC_0, *, internal, X), " & "45 (BC_0, *, internal, X), " & "44 (BC_4, IC11, observe_only, X), " & "43 (BC_4, IC10, observe_only, X), " & "42 (BC_4, IC9, observe_only, X), " & "41 (BC_0, *, internal, X), " & "40 (BC_0, *, internal, X), " & "39 (BC_0, *, internal, X), " & "38 (BC_4, IC8, observe_only, X), " & "37 (BC_4, IC7, observe_only, X), " & "36 (BC_4, IC6, observe_only, X), " & "35 (BC_0, *, internal, X), " & "34 (BC_0, *, internal, X), " & "33 (BC_0, *, internal, X), " & "32 (BC_4, IC5, observe_only, X), " & "31 (BC_4, IC4, observe_only, X), " & "30 (BC_4, IC3, observe_only, X), " & "29 (BC_0, *, internal, X), " & "28 (BC_0, *, internal, X), " & "27 (BC_0, *, internal, X), " & "26 (BC_4, IC2, observe_only, X), " & "25 (BC_4, IC1, observe_only, X), " & "24 (BC_4, IC0, observe_only, X), " & "23 (BC_0, *, internal, X), " & "22 (BC_0, *, internal, X), " & "21 (BC_0, *, internal, X), " & "20 (BC_4, RSF4, observe_only, X), " & "19 (BC_4, RSCK4, observe_only, X), " & "18 (BC_4, RSD4, observe_only, X), " & "17 (BC_0, *, internal, X), " & "16 (BC_0, *, internal, X), " & "15 (BC_0, *, internal, X), " & "14 (BC_4, RSF3, observe_only, X), " & "13 (BC_4, RSCK3, observe_only, X), " & "12 (BC_4, RSD3, observe_only, X), " & "11 (BC_0, *, internal, X), " & "10 (BC_0, *, internal, X), " & "9 (BC_0, *, internal, X), " & "8 (BC_4, RSF2, observe_only, X), " & "7 (BC_4, RSCK2, observe_only, X), " & "6 (BC_4, RSD2, observe_only, X), " & "5 (BC_0, *, internal, X), " & "4 (BC_0, *, internal, X), " & "3 (BC_0, *, internal, X), " & "2 (BC_4, RSF1, observe_only, X), " & "1 (BC_4, RSCK1, observe_only, X), " & "0 (BC_4, RSD1, observe_only, X) "; end S028_package_4ch;