-- *********************************************************************** -- BSDL file for design IDT82V2058 -- Company: IDT_NEWAVE -- Date: Tue Jul 17 19:06:13 2001 -- *********************************************************************** entity IDT82V2058 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "IDT82V2058BB"); -- This section declares all the ports in the design. port ( A0 : in bit; A1 : in bit; A2 : in bit; A3 : in bit; A4 : in bit; SCLK_ALE_ASB : in bit; CLKE : in bit; CSB : in bit; SDI_WRB_DSB : in bit; MCLK : in bit; MODE2 : in bit; MODE0 : in bit; MODE1 : in bit; OE : in bit; RDB_RWB : in bit; TCK : in bit; TCLK0 : in bit; TCLK1 : in bit; TCLK2 : in bit; TCLK3 : in bit; TCLK4 : in bit; TCLK5 : in bit; TCLK6 : in bit; TCLK7 : in bit; TDI : in bit; TMS : in bit; TDN0 : in bit; TDN1 : in bit; TDN2 : in bit; TDN3 : in bit; TDN4 : in bit; TDN5 : in bit; TDN6 : in bit; TDN7 : in bit; TDP0 : in bit; TDP1 : in bit; TDP2 : in bit; TDP3 : in bit; TDP4 : in bit; TDP5 : in bit; TDP6 : in bit; TDP7 : in bit; TRSTB : in bit; LOOP0_D0 : inout bit; LOOP1_D1 : inout bit; LOOP2_D2 : inout bit; LOOP3_D3 : inout bit; LOOP4_D4 : inout bit; LOOP5_D5 : inout bit; LOOP6_D6 : inout bit; LOOP7_D7 : inout bit; SDO_RDY_ACKB : out bit; RCLK0 : out bit; RCLK1 : out bit; RCLK2 : out bit; RCLK3 : out bit; RCLK4 : out bit; RCLK5 : out bit; RCLK6 : out bit; RCLK7 : out bit; RDN0 : out bit; RDN1 : out bit; RDN2 : out bit; RDN3 : out bit; RDN4 : out bit; RDN5 : out bit; RDN6 : out bit; RDN7 : out bit; RDP0 : out bit; RDP1 : out bit; RDP2 : out bit; RDP3 : out bit; RDP4 : out bit; RDP5 : out bit; RDP6 : out bit; RDP7 : out bit; TDO : out bit; INTB : buffer bit; LOS0 : buffer bit; LOS1 : buffer bit; LOS2 : buffer bit; LOS3 : buffer bit; LOS4 : buffer bit; LOS5 : buffer bit; LOS6 : buffer bit; LOS7 : buffer bit; IC0 : linkage bit; IC1 : linkage bit; GNDD : linkage bit; GNDA : linkage bit; GNDIO : linkage bit_vector (0 to 1); GNDTA : linkage bit_vector (0 to 7); GNDTB : linkage bit_vector (0 to 7); RRING : linkage bit_vector (0 to 7); RTIP : linkage bit_vector (0 to 7); TRING : linkage bit_vector (0 to 7); TTIP : linkage bit_vector (0 to 7); VDDD : linkage bit; VDDA : linkage bit; VDDIO : linkage bit_vector (0 to 1); VDDTA : linkage bit_vector (0 to 7); VDDTB : linkage bit_vector (0 to 7) ); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of IDT82V2058: entity is "STD_1149_1_1993"; attribute PIN_MAP of IDT82V2058: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information -- is extracted from the port-to-pin map file that was read in using -- the "read_pin_map" command. constant IDT82V2058BB: PIN_MAP_STRING := "A0 : G3," & "A1 : F1," & "A2 : F2," & "A3 : F3," & "A4 : F4," & "SCLK_ALE_ASB : J12," & "CLKE : E13," & "CSB : J11," & "SDI_WRB_DSB : J14," & "MCLK : E1," & "MODE2 : E2," & "MODE0 : H12," & "MODE1 : K2," & "OE : E14," & "RDB_RWB : J13," & "TCK : F14," & "TCLK0 : N1," & "TCLK1 : L1," & "TCLK2 : L14," & "TCLK3 : N14," & "TCLK4 : B14," & "TCLK5 : D14," & "TCLK6 : D1," & "TCLK7 : B1," & "TDI : F12," & "TMS : F11," & "TDN0 : N3," & "TDN1 : L3," & "TDN2 : L12," & "TDN3 : N12," & "TDN4 : B12," & "TDN5 : D12," & "TDN6 : D3," & "TDN7 : B3," & "TDP0 : N2," & "TDP1 : L2," & "TDP2 : L13," & "TDP3 : N13," & "TDP4 : B13," & "TDP5 : D13," & "TDP6 : D2," & "TDP7 : B2," & "TRSTB : G12," & "LOOP0_D0 : G2," & "LOOP1_D1 : H3," & "LOOP2_D2 : H2," & "LOOP3_D3 : J4," & "LOOP4_D4 : J3," & "LOOP5_D5 : J2," & "LOOP6_D6 : J1," & "LOOP7_D7 : K1," & "SDO_RDY_ACKB : K14," & "RCLK0 : P1," & "RCLK1 : M1," & "RCLK2 : M14," & "RCLK3 : P14," & "RCLK4 : A14," & "RCLK5 : C14," & "RCLK6 : C1," & "RCLK7 : A1," & "RDN0 : P3," & "RDN1 : M3," & "RDN2 : M12," & "RDN3 : P12," & "RDN4 : A12," & "RDN5 : C12," & "RDN6 : C3," & "RDN7 : A3," & "RDP0 : P2," & "RDP1 : M2," & "RDP2 : M13," & "RDP3 : P13," & "RDP4 : A13," & "RDP5 : C13," & "RDP6 : C2," & "RDP7 : A2," & "TDO : F13," & "INTB : K13," & "LOS0 : K4," & "LOS1 : K3," & "LOS2 : K12," & "LOS3 : K11," & "LOS4 : E11," & "LOS5 : E12," & "LOS6 : E3," & "LOS7 : E4," & "IC1 : H13," & "IC0 : G13," & "GNDD : H4," & "GNDA : H11," & "GNDIO : (G4, G11)," & "GNDTA : (N6, L6, L9, N9, A9, C9, C6, A6)," & "GNDTB : (P6, M6, M9, P9, B9, D9, D6, B6)," & "RRING : (N7, L7, L8, N8, B8, D8, D7, B7)," & "RTIP : (P7, M7, M8, P8, A8, C8, C7, A7)," & "TRING : (P5, M5, M10, P10, A10, C10, C5, A5)," & "TTIP : (N5, L5, L10, N10, B10, D10, D5, B5)," & "VDDD : H1," & "VDDA : H14," & "VDDIO : (G1, G14)," & "VDDTA : (N4, L4, L11, N11, A11, C11, C4, A4)," & "VDDTB : (P4, M4, M11, P11, B11, D11, D4, B4)"; -- This section specifies the TAP ports. -- For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_RESET of TRSTB: signal is true; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of IDT82V2058: entity is 3; -- Specifies the boundary-scan instructions implemented in the -- design and their opcodes. attribute INSTRUCTION_OPCODE of IDT82V2058: entity is "BYPASS (111)," & "EXTEST (000)," & "SAMPLE (100)," & "IDCODE (110)," & "USER1 (010)"; -- Specifies the bit pattern that is loaded into the instruction -- register when the TAP controller passes through the Capture-IR -- state. The standard mandates that the two LSBs must be "01". -- The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of IDT82V2058: entity is "001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID -- register during the IDCODE instruction when the TAP controller -- passes through the Capture-DR state. attribute IDCODE_REGISTER of IDT82V2058: entity is "0011" & -- 4-bit version number "0010000001001000" & -- 16-bit part number "00000110011" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI -- and TDO for each implemented instruction. attribute REGISTER_ACCESS of IDT82V2058: entity is "BYPASS (BYPASS)," & "BOUNDARY (EXTEST, SAMPLE)," & "DEVICE_ID (IDCODE)," & "UTDR1[5] (USER1)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of IDT82V2058: entity is 99; -- The following list specifies the characteristics of each cell -- in the boundary scan register from TDI to TDO. -- The following is a description of the label fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not -- have a port name. -- function: Is the function of the cell as defined by the -- standard. Is one of input, output2, output3, -- bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be -- loaded with for safe operation when the software -- might otherwise choose a random value. -- ccell : The control cell number. Specifies the control -- cell that drives the output enable for this port. -- disval : Specifies the value that is loaded into the -- control cell to disable the output enable for -- the corresponding port. -- rslt : Resulting state. Shows the state of the driver -- when it is disabled. attribute BOUNDARY_REGISTER of IDT82V2058: entity is -- -- num cell port function safe [ccell disval rslt] -- "98 (BC_4, A0, observe_only, X), " & "97 (BC_4, A1, observe_only, X), " & "96 (BC_4, A2, observe_only, X), " & "95 (BC_4, A3, observe_only, X), " & "94 (BC_4, A4, observe_only, X), " & "93 (BC_4, MODE2, observe_only, X), " & "92 (BC_4, MCLK, observe_only, X), " & "91 (BC_4, TCLK6, observe_only, X), " & "90 (BC_4, TDP6, observe_only, X), " & "89 (BC_4, TDN6, observe_only, X), " & "88 (BC_1, RCLK6, output3, X, 87, 1, Z), " & "87 (BC_1, *, control, 1), " & "86 (BC_1, RDP6, output3, X, 87, 1, Z), " & "85 (BC_1, RDN6, output3, X, 87, 1, Z), " & "84 (BC_1, LOS6, output2, X), " & "83 (BC_4, TCLK7, observe_only, X), " & "82 (BC_4, TDP7, observe_only, X), " & "81 (BC_4, TDN7, observe_only, X), " & "80 (BC_1, RCLK7, output3, X, 79, 1, Z), " & "79 (BC_1, *, control, 1), " & "78 (BC_1, RDP7, output3, X, 79, 1, Z), " & "77 (BC_1, RDN7, output3, X, 79, 1, Z), " & "76 (BC_1, LOS7, output2, X), " & "75 (BC_4, CLKE, observe_only, X), " & "74 (BC_4, OE, observe_only, X), " & "73 (BC_1, LOS4, output2, X), " & "72 (BC_1, *, control, 1), " & "71 (BC_1, RDN4, output3, X, 72, 1, Z), " & "70 (BC_1, RDP4, output3, X, 72, 1, Z), " & "69 (BC_1, RCLK4, output3, X, 72, 1, Z), " & "68 (BC_4, TDN4, observe_only, X), " & "67 (BC_4, TDP4, observe_only, X), " & "66 (BC_4, TCLK4, observe_only, X), " & "65 (BC_1, LOS5, output2, X), " & "64 (BC_1, *, control, 1), " & "63 (BC_1, RDN5, output3, X, 64, 1, Z), " & "62 (BC_1, RDP5, output3, X, 64, 1, Z), " & "61 (BC_1, RCLK5, output3, X, 64, 1, Z), " & "60 (BC_4, TDN5, observe_only, X), " & "59 (BC_4, TDP5, observe_only, X), " & "58 (BC_4, TCLK5, observe_only, X), " & "57 (BC_4, MODE0, observe_only, X), " & "56 (BC_4, CSB, observe_only, X), " & "55 (BC_4, SCLK_ALE_ASB,observe_only, X), " & "54 (BC_4, RDB_RWB, observe_only, X), " & "53 (BC_4, SDI_WRB_DSB, observe_only, X), " & "52 (BC_1, *, control, 1), " & "51 (BC_1, SDO_RDY_ACKB,output3, X, 52, 1, Z), " & "50 (BC_1, INTB, output2, X), " & "49 (BC_4, TCLK2, observe_only, X), " & "48 (BC_4, TDP2, observe_only, X), " & "47 (BC_4, TDN2, observe_only, X), " & "46 (BC_1, RCLK2, output3, X, 45, 1, Z), " & "45 (BC_1, *, control, 1), " & "44 (BC_1, RDP2, output3, X, 45, 1, Z), " & "43 (BC_1, RDN2, output3, X, 45, 1, Z), " & "42 (BC_1, LOS2, output2, X), " & "41 (BC_4, TCLK3, observe_only, X), " & "40 (BC_4, TDP3, observe_only, X), " & "39 (BC_4, TDN3, observe_only, X), " & "38 (BC_1, RCLK3, output3, X, 37, 1, Z), " & "37 (BC_1, *, control, 1), " & "36 (BC_1, RDP3, output3, X, 37, 1, Z), " & "35 (BC_1, RDN3, output3, X, 37, 1, Z), " & "34 (BC_1, LOS3, output2, X), " & "33 (BC_4, MODE1, observe_only, X), " & "32 (BC_1, LOS0, output2, X), " & "31 (BC_1, *, control, 1), " & "30 (BC_1, RDN0, output3, X, 31, 1, Z), " & "29 (BC_1, RDP0, output3, X, 31, 1, Z), " & "28 (BC_1, RCLK0, output3, X, 31, 1, Z), " & "27 (BC_4, TDN0, observe_only, X), " & "26 (BC_4, TDP0, observe_only, X), " & "25 (BC_4, TCLK0, observe_only, X), " & "24 (BC_1, LOS1, output2, X), " & "23 (BC_1, *, control, 1), " & "22 (BC_1, RDN1, output3, X, 23, 1, Z), " & "21 (BC_1, RDP1, output3, X, 23, 1, Z), " & "20 (BC_1, RCLK1, output3, X, 23, 1, Z), " & "19 (BC_4, TDN1, observe_only, X), " & "18 (BC_4, TDP1, observe_only, X), " & "17 (BC_4, TCLK1, observe_only, X), " & "16 (BC_1, *, control, 1), " & "15 (BC_4, LOOP7_D7, observe_only, X), " & "14 (BC_1, LOOP7_D7, output3, X, 16, 1, Z), " & "13 (BC_4, LOOP6_D6, observe_only, X), " & "12 (BC_1, LOOP6_D6, output3, X, 16, 1, Z), " & "11 (BC_4, LOOP5_D5, observe_only, X), " & "10 (BC_1, LOOP5_D5, output3, X, 16, 1, Z), " & "9 (BC_4, LOOP4_D4, observe_only, X), " & "8 (BC_1, LOOP4_D4, output3, X, 16, 1, Z), " & "7 (BC_4, LOOP3_D3, observe_only, X), " & "6 (BC_1, LOOP3_D3, output3, X, 16, 1, Z), " & "5 (BC_4, LOOP2_D2, observe_only, X), " & "4 (BC_1, LOOP2_D2, output3, X, 16, 1, Z), " & "3 (BC_4, LOOP1_D1, observe_only, X), " & "2 (BC_1, LOOP1_D1, output3, X, 16, 1, Z), " & "1 (BC_4, LOOP0_D0, observe_only, X), " & "0 (BC_1, LOOP0_D0, output3, X, 16, 1, Z) "; end IDT82V2058;