-- Generated by boundaryScanGenerate 6.0a.SP2-Build20071205.019 on 01/08/09 08:55:41
-- BSDL Version 2001
entity chip is
generic (PHYSICAL_PIN_MAP : string := "DEFAULT_PACKAGE_NAME");
port (
-- Port List
GPIO0 : inout bit;
GPIO1 : inout bit;
GPIO2 : inout bit;
GPIO3 : inout bit;
GPIO4 : inout bit;
GPIO5 : inout bit;
GPIO6 : inout bit;
TXP : out bit;
TXM : out bit;
RXP : in bit;
RXM : in bit;
NCLKREQ : out bit;
NPERST : in bit;
GPIO7 : inout bit;
GPIO8 : inout bit;
GPIO9 : inout bit;
GPIO10 : inout bit;
GPIO11 : inout bit;
GPIO12 : inout bit;
GPIO13 : inout bit;
GPIO14 : inout bit;
GPIO15 : inout bit;
RESETB : in bit;
TRST : in bit;
TCK : in bit;
TMS : in bit;
TDI : in bit;
TDO : out bit;
EECK : inout bit;
EECS : inout bit;
EEDI : out bit;
EEDO : in bit;
TX0 : out bit;
RTS0 : out bit;
RX0 : in bit;
CTS0 : inout bit;
DTR0 : out bit;
DSR0 : in bit;
CD0 : in bit;
RI0 : in bit;
TX1 : out bit;
RTS1 : out bit;
RX1 : in bit;
CTS1 : inout bit;
DTR1 : out bit;
DSR1 : in bit;
CD1 : in bit;
RI1 : in bit;
TEST3 : in bit;
TEST4 : in bit;
TEST5 : inout bit;
TEST1 : in bit;
TEST2 : in bit;
EN485 : in bit;
ENIR : in bit;
TMRCK : in bit);
use STD_1149_1_2001.all;
use STD_1149_6_2003.all;
use LVS_BSCAN_CELLS.all;
attribute COMPONENT_CONFORMANCE of chip: entity is "STD_1149_1_2001";
--Pin mappings
attribute PIN_MAP of chip: entity is PHYSICAL_PIN_MAP;
constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING :=
"GPIO0 : A2 , " &
"GPIO1 : C3 , " &
"GPIO2 : B2 , " &
"GPIO3 : B1 , " &
"GPIO4 : C2 , " &
"GPIO5 : D3 , " &
"GPIO6 : C1 , " &
"TXP : G1 , " &
"TXM : G2 , " &
"RXP : E1 , " &
"RXM : E2 , " &
"NCLKREQ : J1 , " &
"NPERST : J2 , " &
"GPIO7 : K1 , " &
"GPIO8 : K2 , " &
"GPIO9 : J3 , " &
"GPIO10 : L2 , " &
"GPIO11 : K3 , " &
"GPIO12 : L3 , " &
"GPIO13 : J4 , " &
"GPIO14 : K4 , " &
"GPIO15 : L5 , " &
"RESETB : J5 , " &
"TRST : L6 , " &
"TCK : K6 , " &
"TMS : J6 , " &
"TDI : L7 , " &
"TDO : K7 , " &
"EECK : J7 , " &
"EECS : K8 , " &
"EEDI : J8 , " &
"EEDO : L9 , " &
"TX0 : K9 , " &
"RTS0 : L10 , " &
"RX0 : J9 , " &
"CTS0 : K10 , " &
"DTR0 : K11 , " &
"DSR0 : J10 , " &
"CD0 : J11 , " &
"RI0 : H9 , " &
"TX1 : H10 , " &
"RTS1 : G9 , " &
"RX1 : G10 , " &
"CTS1 : G11 , " &
"DTR1 : F11 , " &
"DSR1 : F10 , " &
"CD1 : F9 , " &
"RI1 : E11 , " &
"TEST3 : D10 , " &
"TEST4 : E10 , " &
"TEST5 : E9 , " &
"TEST1 : B7 , " &
"TEST2 : A7 , " &
"EN485 : C6 , " &
"ENIR : B6 , " &
"TMRCK : A6 " ;
attribute PORT_GROUPING of chip : entity is
"Differential_Voltage ( (TXP, TXM), " &
"(RXP, RXM)) " ;
attribute TAP_SCAN_RESET of TRST : signal is true;
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (1.0000000000000000000e+07, BOTH);
attribute INSTRUCTION_LENGTH of chip: entity is 25;
attribute INSTRUCTION_OPCODE of chip: entity is
"IDCODE (1111111111111111111111110)," &
"BYPASS (0000000000000000000000000, 1111111111111111111111111)," &
"EXTEST (1111111111111111111101000)," &
"EXTEST_PULSE (1111111101111111111101000)," &
"EXTEST_TRAIN (1111111011111111111101000)," &
"SAMPLE (1111111111111111111111000)," &
"PRELOAD (1111111111111111111111000)," &
"HIGHZ (1111111111111111111001111)," &
"CLAMP (1111111111111111111101111) " ;
attribute INSTRUCTION_CAPTURE of chip: entity is "xxxxxxxxxxxxxxxxxxxxxxx01";
attribute IDCODE_REGISTER of chip: entity is
"0011" & -- version
"0000001101010010" & -- part number
"00001011110" & -- manufacturer's identity
"1"; -- required by 1149.1
attribute REGISTER_ACCESS of chip: entity is
"BOUNDARY ( EXTEST_PULSE, EXTEST_TRAIN )," &
"BOUNDARY ( SAMPLE, PRELOAD )," &
"BYPASS ( HIGHZ, CLAMP, BYPASS ) " ;
--Boundary scan definition
attribute BOUNDARY_LENGTH of chip: entity is 132;
attribute BOUNDARY_REGISTER of chip: entity is
-- num cell port function safe [ccell disval rslt]
" 131 (BC_2 , * , control , 1 ) ,"&
" 130 (BC_0 , * , internal , X),"&
" 129 (BC_0 , * , internal , X ),"&
" 128 (BC_0 , * , internal , X ) ,"&
" 127 (BC_0 , * , internal , X ) ,"&
" 126 (BC_0 , * , internal , X ) ,"&
" 125 (BC_0 , * , internal , X ) ,"&
" 124 (BC_2 , * , control , 1 ) ,"&
" 123 (LV_BC_7 , GPIO0 , bidir , X , 124 , 1 , Z ),"&
" 122 (BC_2 , * , control , 1 ) ,"&
" 121 (LV_BC_7 , GPIO1 , bidir , X , 122 , 1 , Z ),"&
" 120 (BC_2 , * , control , 1 ) ,"&
" 119 (LV_BC_7 , GPIO2 , bidir , X , 120 , 1 , Z ),"&
" 118 (BC_2 , * , control , 1 ) ,"&
" 117 (LV_BC_7 , GPIO3 , bidir , X , 118 , 1 , Z ),"&
" 116 (BC_2 , * , control , 1 ) ,"&
" 115 (LV_BC_7 , GPIO4 , bidir , X , 116 , 1 , Z ),"&
" 114 (BC_2 , * , control , 1 ) ,"&
" 113 (LV_BC_7 , GPIO5 , bidir , X , 114 , 1 , Z ),"&
" 112 (BC_2 , * , control , 1 ) ,"&
" 111 (LV_BC_7 , GPIO6 , bidir , X , 112 , 1 , Z ),"&
" 110 (BC_1 , * , control , 0 ) ,"&
" 109 (AC_1 , TXP , output3 , X , 110 , 0 , Z ),"&
" 108 (BC_4 , RXP , observe_only , X ) ,"&
" 107 (BC_4 , RXM , observe_only , X ) ,"&
" 106 (BC_2 , NCLKREQ , output3 , X , 131 , 1 , Z ),"&
" 105 (BC_2 , NPERST , input , X ) ,"&
" 104 (BC_2 , * , control , 1 ) ,"&
" 103 (LV_BC_7 , GPIO7 , bidir , X , 104 , 1 , Z ),"&
" 102 (BC_2 , * , control , 1 ) ,"&
" 101 (LV_BC_7 , GPIO8 , bidir , X , 102 , 1 , Z ),"&
" 100 (BC_2 , * , control , 1 ) ,"&
" 99 (LV_BC_7 , GPIO9 , bidir , X , 100 , 1 , Z ),"&
" 98 (BC_2 , * , control , 1 ) ,"&
" 97 (LV_BC_7 , GPIO10 , bidir , X , 98 , 1 , Z ),"&
" 96 (BC_2 , * , control , 1 ) ,"&
" 95 (LV_BC_7 , GPIO11 , bidir , X , 96 , 1 , Z ),"&
" 94 (BC_2 , * , control , 1 ) ,"&
" 93 (LV_BC_7 , GPIO12 , bidir , X , 94 , 1 , Z ),"&
" 92 (BC_2 , * , control , 1 ) ,"&
" 91 (LV_BC_7 , GPIO13 , bidir , X , 92 , 1 , Z ),"&
" 90 (BC_2 , * , control , 1 ) ,"&
" 89 (LV_BC_7 , GPIO14 , bidir , X , 90 , 1 , Z ),"&
" 88 (BC_2 , * , control , 1 ) ,"&
" 87 (LV_BC_7 , GPIO15 , bidir , X , 88 , 1 , Z ),"&
" 86 (BC_2 , RESETB , input , X ) ,"&
" 85 (BC_0 , * , internal , X ) ,"&
" 84 (BC_0 , * , internal , X ),"&
" 83 (BC_0 , * , internal , X ),"&
" 82 (BC_2 , * , control , 1 ) ,"&
" 81 (BC_0 , * , internal , X ),"&
" 80 (BC_0 , * , internal , X ),"&
" 79 (BC_0 , * , internal , X ) ,"&
" 78 (BC_0 , * , internal , X ) ,"&
" 77 (BC_0 , * , internal , X ),"&
" 76 (BC_0 , * , internal , X ),"&
" 75 (BC_0 , * , internal , X ) ,"&
" 74 (BC_0 , * , internal , X ) ,"&
" 73 (BC_0 , * , internal , X ),"&
" 72 (BC_0 , * , internal , X ),"&
" 71 (BC_0 , * , internal , X ) ,"&
" 70 (BC_0 , * , internal , X ) ,"&
" 69 (BC_0 , * , internal , X ) ,"&
" 68 (BC_0 , * , internal , X ),"&
" 67 (BC_0 , * , internal , X ),"&
" 66 (BC_0 , * , internal , X ) ,"&
" 65 (BC_0 , * , internal , X ),"&
" 64 (BC_0 , * , internal , X ),"&
" 63 (BC_0 , * , internal , X ) ,"&
" 62 (BC_0 , * , internal , X ) ,"&
" 61 (BC_0 , * , internal , X ) ,"&
" 60 (BC_2 , * , control , 1 ) ,"&
" 59 (LV_BC_7 , EECK , bidir , X , 60 , 1 , Z ),"&
" 58 (LV_BC_7 , EECS , bidir , X , 60 , 1 , Z ),"&
" 57 (BC_2 , EEDI , output3 , X , 60 , 1 , Z ),"&
" 56 (BC_2 , EEDO , input , X ) ,"&
" 55 (BC_2 , TX0 , output3 , X , 131 , 1 , Z ),"&
" 54 (BC_2 , * , control , 1 ) ,"&
" 53 (BC_2 , RTS0 , output3 , X , 54 , 1 , Z ),"&
" 52 (BC_2 , RX0 , input , X ) ,"&
" 51 (LV_BC_7 , CTS0 , bidir , X , 82 , 1 , Z ),"&
" 50 (BC_2 , DTR0 , output3 , X , 54 , 1 , Z ),"&
" 49 (BC_2 , DSR0 , input , X ) ,"&
" 48 (BC_2 , CD0 , input , X ) ,"&
" 47 (BC_2 , RI0 , input , X ) ,"&
" 46 (BC_2 , TX1 , output3 , X , 54 , 1 , Z ),"&
" 45 (BC_2 , RTS1 , output3 , X , 54 , 1 , Z ),"&
" 44 (BC_2 , RX1 , input , X ) ,"&
" 43 (LV_BC_7 , CTS1 , bidir , X , 82 , 1 , Z ),"&
" 42 (BC_2 , DTR1 , output3 , X , 54 , 1 , Z ),"&
" 41 (BC_2 , DSR1 , input , X ) ,"&
" 40 (BC_2 , CD1 , input , X ) ,"&
" 39 (BC_2 , RI1 , input , X ) ,"&
" 38 (BC_2 , TEST3 , input , X ) ,"&
" 37 (BC_4 , TEST4 , observe_only , X ) ,"&
" 36 (BC_2 , * , control , 1 ) ,"&
" 35 (LV_BC_7 , TEST5 , bidir , X , 36 , 1 , Z ),"&
" 34 (BC_0 , * , internal , X ),"&
" 33 (BC_0 , * , internal , X ) ,"&
" 32 (BC_0 , * , internal , X ),"&
" 31 (BC_0 , * , internal , X ),"&
" 30 (BC_0 , * , internal , X ),"&
" 29 (BC_0 , * , internal , X ),"&
" 28 (BC_0 , * , internal , X ),"&
" 27 (BC_0 , * , internal , X ),"&
" 26 (BC_0 , * , internal , X ),"&
" 25 (BC_0 , * , internal , X ),"&
" 24 (BC_0 , * , internal , X ) ,"&
" 23 (BC_0 , * , internal , X ),"&
" 22 (BC_4 , TEST1 , observe_only , X ) ,"&
" 21 (BC_4 , TEST2 , observe_only , X ) ,"&
" 20 (BC_2 , EN485 , input , X ) ,"&
" 19 (BC_2 , ENIR , input , X ) ,"&
" 18 (BC_2 , TMRCK , input , X ) ,"&
" 17 (BC_0 , * , internal , X ),"&
" 16 (BC_0 , * , internal , X ) ,"&
" 15 (BC_0 , * , internal , X ),"&
" 14 (BC_0 , * , internal , X ),"&
" 13 (BC_0 , * , internal , X ),"&
" 12 (BC_0 , * , internal , X ) ,"&
" 11 (BC_0 , * , internal , X ) ,"&
" 10 (BC_0 , * , internal , X ) ,"&
" 9 (BC_0 , * , internal , X ),"&
" 8 (BC_0 , * , internal , X ) ,"&
" 7 (BC_0 , * , internal , X ),"&
" 6 (BC_0 , * , internal , X ),"&
" 5 (BC_0 , * , internal , X ),"&
" 4 (BC_0 , * , internal , X ) ,"&
" 3 (BC_0 , * , internal , X ) ,"&
" 2 (BC_0 , * , internal , X ) ,"&
" 1 (BC_0 , * , internal , X ),"&
" 0 (BC_0 , * , internal , X ) ";
attribute AIO_COMPONENT_CONFORMANCE of chip: entity is "STD_1149_6_2003";
attribute AIO_EXTEST_Train_Execution of chip: entity is
"train 4, maximum_time 0.001" ;
attribute AIO_Pin_Behavior of chip: entity is
"TXP ;"&
"RXP[108] : LP_Time=2.30e-07 HP_Time=7.00e-06";
end chip;