--***********************************************************************************************
--*
--* File Name: MT44K16M36.BSDL
--* Revision: 1.1
--* Date: July 11, 2012
--* Model: BSDL
--* Simulator: Agilent Technologies
--*
--* Dependencies: None
--*
--* Author: Troy Quick
--* Email: tquick@micron.com
--* Phone: (208)363-2553
--* Company: Micron Technology, Inc.
--* Model: MT44K16M36 (16M x 36 RLDRAM III)
--*
--* Description: Micron 16M x 36 BSDL model
--*
--* Limitation: IEEE 1149.1 Serial Boundary Scan (JTAG)
--*
--* Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO
--* WARRANTY WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS
--* ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--* A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--*
--* Copyright (C) 1998 Micron Semiconductor Products, Inc.
--* All rights reserved
--*
--* Rev Author Date Changes
--* ---------------------------------------------------------------------------
--* 1.0 BCG 12/14/10 New Model
--* 1.1 TLQ 07/11/12 Replaced MT6L with MT44K. The MT6L part number was decided to not match with our current DRAM part numbering scheme.
--*
--*********************************************************************************************/
entity MT44K16M36 is
generic (PHYSICAL_PIN_MAP : string := "uBGA");
port (
A: in bit_vector(0 to 18);
B: in bit_vector(0 to 3);
DQ: inout bit_vector(0 to 35);
QK: buffer bit_vector(0 to 3);
QK_n: buffer bit_vector(0 to 3);
QVLD: buffer bit_vector(0 to 1);
DK: in bit_vector(0 to 1);
DK_n: in bit_vector(0 to 1);
DM: in bit_vector(0 to 1);
CK: in bit;
CK_n: in bit;
WE_n: in bit;
REF_n: in bit;
CS_n: in bit;
ZQ: in bit;
TMS: in bit;
MF: in bit;
TDI: in bit;
TCK: in bit;
RESET_n: in bit;
TDO: out bit;
VEXT: linkage bit_vector(0 to 3);
VREF: linkage bit_vector(0 to 1);
Vdd: linkage bit_vector(0 to 13);
Vss: linkage bit_vector(0 to 16);
VssQ: linkage bit_vector(0 to 19);
VddQ: linkage bit_vector(0 to 21);
NF: linkage bit_vector(0 to 1));
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of MT44K16M36 : entity is
"STD_1149_1_2001";
attribute PIN_MAP of MT44K16M36 : entity is PHYSICAL_PIN_MAP;
constant uBGA : PIN_MAP_STRING:=
" A: (E2,F5,F4,F9,F10,F12,G3,F1,G11,F13, " &
" H13,D1,H11,D13,H3,G2,H4,H10,G12), " & --Address
" B: (G9,G5,H8,H6), " & --Bank Address
" DQ: (D11,E10,C8,C10,C12,B9,B11,A8,A10,J10,K11,K13, " &
" L8,L10,L12,M9,M11,N8,D3,E4,C6,C4,C2,B5, " &
" B3,A6,A4,J4,K3,K1,L6,L4,L2,M5,M3,N6), " & --DQs
" QK: (D9,K9,D5,K5), " & --Output Data Clocks
" QK_n: (E8,J8,E6,J6), " & --Output Data Clocks
" QVLD: (J12,J2), " & --Data Valid
" DK: (D7,K7), " & --Input Data Clocks
" DK_n: (C7,L7), " & --Input Data Clocks
" DM: (B7,M7), " & --Input Data Mask
" CK: H7, " & --Pos Clock
" CK_n: G7, " & --Neg Clock
" WE_n: F6, " & --Command control
" REF_n: F8, " & --Command control
" CS_n: E12, " & --Neg Chip Select
" ZQ: F7, " & --Impedance control
" TMS: N12, " & --Test Mode Select
" MF: E7, " & --Mirror Function
" TDI: N10, " & --Test Data-In
" TCK: N2, " & --Test Clock
" RESET_n: A13, " & --Reset Control
" TDO: N4, " & --Test Data-Out
" VEXT: (B1,B13,M1,M13), " & --Power Supply
" VREF: (A7,N7), " & --Input Ref Voltage
" VDD: (A3,A11,C1,C13,F3,F11,H2, " & --Power Supply
" H5,H9,H12,L1,L13,N3,N11), " &
" VSS: (A2,A12,B2,B12,E1,E13,G1,G4, " & --GND
" G6,G8,G10,G13,J7,M2,M12,N1,N13), " &
" VSSQ: (B4,B10,C5,C9,D2,D6,D8,D12,E3, " & --Isolated Output Buffer Supply, GND
" E11,J3,J11,K2,K6,K8,K12,L5,L9,M4,M10), " &
" VDDQ: (A5,A9,B6,B8,C3,C11,D4,D10,E5,E9,J1,J5, " & --Isolated Output Buffer Supply
" J9,J13,K4,K10,L3,L11,M6,M8,N5,N9), " &
" NF: (F2,H1) " ; --No Function
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH);
attribute INSTRUCTION_LENGTH of MT44K16M36 : entity is 8;
attribute INSTRUCTION_OPCODE of MT44K16M36 : entity is
"EXTEST (00000000), " &
"SAMPLEZ (00000011), " &
"SAMPLE (00000101), " &
"PRELOAD (00000101), " &
"CLAMP (00000111), " &
"IDCODE (00100001), " &
"BYPASS (11111111) " ;
attribute INSTRUCTION_CAPTURE of MT44K16M36 : entity is
"00100001";
attribute IDCODE_REGISTER of MT44K16M36 : entity is
"0001" & --Die Rev & Width
"0010000010100111" & --Device ID
"00000101100" & --MICRON JEDEC ID
"1" ; --ID REGISTER PRESENCE INDICATOR
attribute REGISTER_ACCESS of MT44K16M36 : entity is
"BOUNDARY (EXTEST,SAMPLE)," &
"BYPASS (SAMPLEZ,CLAMP,BYPASS)";
attribute BOUNDARY_LENGTH of MT44K16M36 : entity is 121;
attribute BOUNDARY_REGISTER of MT44K16M36 : entity is
"0 (BC_2, *, control, 0), " &
"1 (BC_7, DQ(17), bidir, X, 0, 0, Z), " &
"2 (BC_2, *, control, 0), " &
"3 (BC_7, DQ(16), bidir, X, 2, 0, Z), " &
"4 (BC_2, *, control, 0), " &
"5 (BC_7, DQ(15), bidir, X, 4, 0, Z), " &
"6 (BC_2, *, control, 0), " &
"7 (BC_7, DQ(14), bidir, X, 6, 0, Z), " &
"8 (BC_2, *, control, 0), " &
"9 (BC_7, DQ(13), bidir, X, 8, 0, Z), " &
"10 (BC_2, *, control, 0), " &
"11 (BC_7, DQ(12), bidir, X, 10, 0, Z), " &
"12 (BC_2, *, control, 0), " &
"13 (BC_7, DQ(11), bidir, X, 12, 0, Z), " &
"14 (BC_2, *, control, 0), " &
"15 (BC_7, DQ(10), bidir, X, 14, 0, Z), " &
"16 (BC_2, *, control, 0), " &
"17 (BC_7, DQ(9), bidir, X, 16, 0, Z), " &
"18 (BC_1, QK_n(1), output2, X), " &
"19 (BC_1, QK(1), output2, X), " &
"20 (BC_1, QVLD(0), output2, X), " &
"21 (BC_2, *, control, 0), " &
"22 (BC_7, DQ(8), bidir, X, 21, 0, Z), " &
"23 (BC_2, *, control, 0), " &
"24 (BC_7, DQ(7), bidir, X, 23, 0, Z), " &
"25 (BC_2, *, control, 0), " &
"26 (BC_7, DQ(6), bidir, X, 25, 0, Z), " &
"27 (BC_2, *, control, 0), " &
"28 (BC_7, DQ(5), bidir, X, 27, 0, Z), " &
"29 (BC_2, *, control, 0), " &
"30 (BC_7, DQ(4), bidir, X, 29, 0, Z), " &
"31 (BC_2, *, control, 0), " &
"32 (BC_7, DQ(3), bidir, X, 31, 0, Z), " &
"33 (BC_2, *, control, 0), " &
"34 (BC_7, DQ(2), bidir, X, 33, 0, Z), " &
"35 (BC_2, *, control, 0), " &
"36 (BC_7, DQ(1), bidir, X, 35, 0, Z), " &
"37 (BC_2, *, control, 0), " &
"38 (BC_7, DQ(0), bidir, X, 37, 0, Z), " &
"39 (BC_1, QK_n(0), output2, X), " &
"40 (BC_1, QK(0), output2, X), " &
"41 (BC_1, DK_n(1), input, X), " &
"42 (BC_1, DK(1), input, X), " &
"43 (BC_4, *, internal, X), " &
"44 (BC_1, A(16), input, X), " &
"45 (BC_1, A(15), input, X), " &
"46 (BC_1, A(6), input, X), " &
"47 (BC_1, A(7), input, X), " &
"48 (BC_1, A(1), input, X), " &
"49 (BC_1, A(2), input, X), " &
"50 (BC_4, *, internal, X), " &
"51 (BC_1, A(11), input, X), " &
"52 (BC_1, ZQ, input, X), " &
"53 (BC_1, DK(0), input, X), " &
"54 (BC_1, DK_n(0), input, X), " &
"55 (BC_1, RESET_n, input, X), " &
"56 (BC_1, DM(0), input, X), " &
"57 (BC_1, MF, input, X), " &
"58 (BC_1, A(13), input, X), " &
"59 (BC_1, A(5), input, X), " &
"60 (BC_1, A(4), input, X), " &
"61 (BC_1, A(3), input, X), " &
"62 (BC_1, A(0), input, X), " &
"63 (BC_1, CS_n, input, X), " &
"64 (BC_1, WE_n, input, X), " &
"65 (BC_1, REF_n, input, X), " &
"66 (BC_4, CK_n, input, X), " &
"67 (BC_4, CK, input, X), " &
"68 (BC_1, B(1), input, X), " &
"69 (BC_1, B(0), input, X), " &
"70 (BC_1, B(3), input, X), " &
"71 (BC_1, B(2), input, X), " &
"72 (BC_1, A(9), input, X), " &
"73 (BC_1, A(8), input, X), " &
"74 (BC_1, A(18), input, X), " &
"75 (BC_1, A(17), input, X), " &
"76 (BC_1, A(14), input, X), " &
"77 (BC_1, A(12), input, X), " &
"78 (BC_1, A(10), input, X), " &
"79 (BC_1, DM(1), input, X), " &
"80 (BC_2, *, control, 0), " &
"81 (BC_7, DQ(35), bidir, X, 80, 0, Z), " &
"82 (BC_2, *, control, 0), " &
"83 (BC_7, DQ(34), bidir, X, 82, 0, Z), " &
"84 (BC_2, *, control, 0), " &
"85 (BC_7, DQ(33), bidir, X, 84, 0, Z), " &
"86 (BC_2, *, control, 0), " &
"87 (BC_7, DQ(32), bidir, X, 86, 0, Z), " &
"88 (BC_2, *, control, 0), " &
"89 (BC_7, DQ(31), bidir, X, 88, 0, Z), " &
"90 (BC_2, *, control, 0), " &
"91 (BC_7, DQ(30), bidir, X, 90, 0, Z), " &
"92 (BC_2, *, control, 0), " &
"93 (BC_7, DQ(29), bidir, X, 92, 0, Z), " &
"94 (BC_2, *, control, 0), " &
"95 (BC_7, DQ(28), bidir, X, 94, 0, Z), " &
"96 (BC_2, *, control, 0), " &
"97 (BC_7, DQ(27), bidir, X, 96, 0, Z), " &
"98 (BC_1, QK_n(3), output2, X), " &
"99 (BC_1, QK(3), output2, X), " &
"100 (BC_1, QVLD(1), output2, X), " &
"101 (BC_2, *, control, 0), " &
"102 (BC_7, DQ(26), bidir, X, 101, 0, Z), " &
"103 (BC_2, *, control, 0), " &
"104 (BC_7, DQ(25), bidir, X, 103, 0, Z), " &
"105 (BC_2, *, control, 0), " &
"106 (BC_7, DQ(24), bidir, X, 105, 0, Z), " &
"107 (BC_2, *, control, 0), " &
"108 (BC_7, DQ(23), bidir, X, 107, 0, Z), " &
"109 (BC_2, *, control, 0), " &
"110 (BC_7, DQ(22), bidir, X, 109, 0, Z), " &
"111 (BC_2, *, control, 0), " &
"112 (BC_7, DQ(21), bidir, X, 111, 0, Z), " &
"113 (BC_2, *, control, 0), " &
"114 (BC_7, DQ(20), bidir, X, 113, 0, Z), " &
"115 (BC_2, *, control, 0), " &
"116 (BC_7, DQ(19), bidir, X, 115, 0, Z), " &
"117 (BC_2, *, control, 0), " &
"118 (BC_7, DQ(18), bidir, X, 117, 0, Z), " &
"119 (BC_1, QK_n(2), output2, X), " &
"120 (BC_1, QK(2), output2, X) " ;
end MT44K16M36;
