-- ********************************************************************
-- *
-- * Module : te18chip_jtag
-- * Created: Thu Oct 9 12:32:48 2008
-- * By : BSCAN2BSDL
-- * bscan2bsdl te18chip_jtag
-- * (c) 1991-2001, SynTest Technologies, Inc.
-- *
-- ********************************************************************
entity te18chip_jtag is
--
-- Generic Parameter
--
generic (PHYSICAL_PIN_MAP : string := "BGA");
--
-- Logical Port Description
--
port (
TTIP_0: out bit;
TRING_0: out bit;
TTIP_1: out bit;
TRING_1: out bit;
TTIP_2: out bit;
TRING_2: out bit;
TTIP_3: out bit;
TRING_3: out bit;
TTIP_4: out bit;
TRING_4: out bit;
TTIP_5: out bit;
TRING_5: out bit;
TTIP_6: out bit;
TRING_6: out bit;
TTIP_7: out bit;
TRING_7: out bit;
TXON_PAD: in bit;
reset_l_oe: in bit;
oscclk_t1: inout bit;
oscclk_e1: inout bit;
txserclk_7: inout bit;
txser_7: in bit;
txmsync_7: inout bit;
rxserclk_7: inout bit;
rxlos_7: out bit;
txsync_7: inout bit;
rxcrcsync_7: out bit;
rxsync_7: inout bit;
rxchn_7_4: out bit;
rxser_7: out bit;
txserclk_6: inout bit;
rxcasync_7: out bit;
txmsync_6: inout bit;
txsync_6: inout bit;
txser_6: in bit;
rxcasync_6: out bit;
rxcrcsync_6: out bit;
rxsync_6: inout bit;
rxchn_6_4: out bit;
rxserclk_6: inout bit;
rxlos_6: out bit;
rxser_6: out bit;
txserclk_5: inout bit;
txser_5: in bit;
txsync_5: inout bit;
txmsync_5: inout bit;
rxchn_5_4: out bit;
rxser_5: out bit;
rxsync_5: inout bit;
rxcasync_5: out bit;
rxserclk_5: inout bit;
rxlos_5: out bit;
rxcrcsync_5: out bit;
txmsync_4: inout bit;
txsync_4: inout bit;
txserclk_4: inout bit;
txser_4: in bit;
rxcasync_4: out bit;
rxchn_4_4: out bit;
rxser_4: out bit;
rxsync_4: inout bit;
rxcrcsync_4: out bit;
preq_l_1: out bit;
rxserclk_4: inout bit;
rxlos_4: out bit;
pack_l_0: in bit;
preq_l_0: out bit;
ptype_0: in bit;
pack_l_1: in bit;
pclk: in bit;
pdata_0: inout bit;
pdata_1: inout bit;
prd_l: in bit;
ptype_1: in bit;
pdack_l: out bit;
paddr_0: in bit;
paddr_1: in bit;
paddr_2: in bit;
paddr_3: in bit;
paddr_4: in bit;
paddr_5: in bit;
paddr_6: in bit;
paddr_7: in bit;
paddr_0_8: in bit;
pdata_2: inout bit;
pdata_3: inout bit;
pas_l: in bit;
paddr_1_9: in bit;
paddr_2_10: in bit;
ptype_2: in bit;
pint_l: out bit;
paddr_3_11: in bit;
pdata_4: inout bit;
paddr_4_12: in bit;
pdata_5: inout bit;
pdata_6: inout bit;
paddr_5_13: in bit;
paddr_6_14: in bit;
pdata_7: inout bit;
pwr_l: in bit;
pcs_l: in bit;
txmsync_3: inout bit;
txser_3: in bit;
rxchn_3_4: out bit;
txserclk_3: inout bit;
txsync_3: inout bit;
rxserclk_3: inout bit;
rxlos_3: out bit;
rxcasync_3: out bit;
rxcrcsync_3: out bit;
rxsync_3: inout bit;
rxser_3: out bit;
txser_2: in bit;
txmsync_2: inout bit;
rxchn_2_4: out bit;
txserclk_2: inout bit;
txsync_2: inout bit;
rxser_2: out bit;
rxcrcsync_2: out bit;
rxcasync_2: out bit;
rxserclk_2: inout bit;
rxlos_2: out bit;
txserclk_1: inout bit;
rxsync_2: inout bit;
txser_1: in bit;
rxchn_1_4: out bit;
txmsync_1: inout bit;
txsync_1: inout bit;
rxlos_1: out bit;
rxcasync_1: out bit;
rxsync_1: inout bit;
rxser_1: out bit;
rxserclk_1: inout bit;
rxcrcsync_1: out bit;
txserclk_0: inout bit;
txser_0: in bit;
rxchn_0_4: out bit;
txmsync_0: inout bit;
rxcasync_0: out bit;
txsync_0: inout bit;
rxsync_0: inout bit;
rxcrcsync_0: out bit;
tck: in bit;
rxserclk_0: inout bit;
rxlos_0: out bit;
trst: in bit;
rxser_0: out bit;
tdi: in bit;
tms: in bit;
tdo: out bit;
atestmode: in bit;
mclkin: in bit;
RXTSEL_PAD: in bit
);
--
-- Use Statements
--
use STD_1149_1_1994.all; -- Get Std 1149.1-1994 attributes and definitions
attribute COMPONENT_CONFORMANCE of te18chip_jtag : entity is "STD_1149_1_1993";
--
-- Package Pin Mapping
--
attribute PIN_MAP of te18chip_jtag : entity is PHYSICAL_PIN_MAP;
constant BGA:PIN_MAP_STRING:=
"TTIP_0 : C3," &
"TRING_0 : D3," &
"TTIP_1 : E3," &
"TRING_1 : E4," &
"TTIP_2 : G3," &
"TRING_2 : G4," &
"TTIP_3 : H3," &
"TRING_3 : H4," &
"TTIP_4 : J3," &
"TRING_4 : J4," &
"TTIP_5 : L3," &
"TRING_5 : L4," &
"TTIP_6 : M3," &
"TRING_6 : M4," &
"TTIP_7 : P3," &
"TRING_7 : P4," &
"TXON_PAD : T4," &
"reset_l_oe : R4," &
"oscclk_t1 : T5," &
"oscclk_e1 : R5," &
"txserclk_7 : P6," &
"txser_7 : P5," &
"txmsync_7 : N6," &
"rxserclk_7 : R6," &
"rxlos_7 : P7," &
"txsync_7 : T6," &
"rxcrcsync_7 : N7," &
"rxsync_7 : R7," &
"rxchn_7_4 : M7," &
"rxser_7 : P8," &
"txserclk_6 : T7," &
"rxcasync_7 : M8," &
"txmsync_6 : R8," &
"txsync_6 : N8," &
"txser_6 : T8," &
"rxcasync_6 : N9," &
"rxcrcsync_6 : R9," &
"rxsync_6 : T9," &
"rxchn_6_4 : P9," &
"rxserclk_6 : M10," &
"rxlos_6 : R10," &
"rxser_6 : T10," &
"txserclk_5 : N10," &
"txser_5 : P10," &
"txsync_5 : M11," &
"txmsync_5 : R11," &
"rxchn_5_4 : T11," &
"rxser_5 : P11," &
"rxsync_5 : N11," &
"rxcasync_5 : R12," &
"rxserclk_5 : T12," &
"rxlos_5 : P12," &
"rxcrcsync_5 : R13," &
"txmsync_4 : P13," &
"txsync_4 : T13," &
"txserclk_4 : T14," &
"txser_4 : N12," &
"rxcasync_4 : R14," &
"rxchn_4_4 : T15," &
"rxser_4 : P15," &
"rxsync_4 : N13," &
"rxcrcsync_4 : R15," &
"preq_l_1 : R16," &
"rxserclk_4 : P14," &
"rxlos_4 : P16," &
"pack_l_0 : N15," &
"preq_l_0 : N16," &
"ptype_0 : M13," &
"pack_l_1 : M15," &
"pclk : M16," &
"pdata_0 : M14," &
"pdata_1 : L12," &
"prd_l : L15," &
"ptype_1 : M12," &
"pdack_l : L16," &
"paddr_0 : L13," &
"paddr_1 : L14," &
"paddr_2 : K15," &
"paddr_3 : L11," &
"paddr_4 : K13," &
"paddr_5 : K16," &
"paddr_6 : K14," &
"paddr_7 : J15," &
"paddr_0_8 : J14," &
"pdata_2 : K12," &
"pdata_3 : J12," &
"pas_l : J16," &
"paddr_1_9 : J13," &
"paddr_2_10 : H14," &
"ptype_2 : H12," &
"pint_l : H15," &
"paddr_3_11 : H16," &
"pdata_4 : H13," &
"paddr_4_12 : G16," &
"pdata_5 : G14," &
"pdata_6 : G12," &
"paddr_5_13 : F16," &
"paddr_6_14 : G11," &
"pdata_7 : G13," &
"pwr_l : F13," &
"pcs_l : F14," &
"txmsync_3 : E14," &
"txser_3 : F15," &
"rxchn_3_4 : F12," &
"txserclk_3 : E16," &
"txsync_3 : E15," &
"rxserclk_3 : D15," &
"rxlos_3 : D16," &
"rxcasync_3 : E13," &
"rxcrcsync_3 : E12," &
"rxsync_3 : C16," &
"rxser_3 : B16," &
"txser_2 : D14," &
"txmsync_2 : C15," &
"rxchn_2_4 : A15," &
"txserclk_2 : B15," &
"txsync_2 : A14," &
"rxser_2 : B14," &
"rxcrcsync_2 : C14," &
"rxcasync_2 : D13," &
"rxserclk_2 : C13," &
"rxlos_2 : F11," &
"txserclk_1 : B13," &
"rxsync_2 : A13," &
"txser_1 : C12," &
"rxchn_1_4 : D12," &
"txmsync_1 : A12," &
"txsync_1 : B12," &
"rxlos_1 : C11," &
"rxcasync_1 : D11," &
"rxsync_1 : A11," &
"rxser_1 : B11," &
"rxserclk_1 : A10," &
"rxcrcsync_1 : C10," &
"txserclk_0 : D10," &
"txser_0 : E10," &
"rxchn_0_4 : B10," &
"txmsync_0 : D9," &
"rxcasync_0 : A9," &
"txsync_0 : C9," &
"rxsync_0 : B9," &
"rxcrcsync_0 : A8," &
"tck : D8," &
"rxserclk_0 : B8," &
"rxlos_0 : A7," &
"trst : D7," &
"rxser_0 : B7," &
"tdi : C8," &
"tms : A6," &
"tdo : B6," &
"atestmode : C7," &
"mclkin : E6," &
"RXTSEL_PAD : A5";
--
-- Scan Port Identification
--
attribute TAP_SCAN_IN of tdi : signal is true;
attribute TAP_SCAN_MODE of tms : signal is true;
attribute TAP_SCAN_OUT of tdo : signal is true;
attribute TAP_SCAN_RESET of trst : signal is true;
attribute TAP_SCAN_CLOCK of tck : signal is (25.0e6,BOTH);
--
-- TAP Instruction Description
--
attribute INSTRUCTION_LENGTH of te18chip_jtag : entity is 4;
attribute INSTRUCTION_OPCODE of te18chip_jtag : entity is
"BYPASS (1111)," &
"EXTEST (0000)," &
"IDCODE (0001)," &
"SAMPLE (0011)," &
"HIGHZ (1101)," &
"SYNTEST_ATPG (1010)," &
"BIST_MODE (0110)";
attribute INSTRUCTION_CAPTURE of te18chip_jtag : entity is "0001";
attribute IDCODE_REGISTER of te18chip_jtag : entity is
"0001" & -- 4-bit version
"0000000000111100" & -- 16-bit part number
"00001011110" & -- 11-bit manufacturer
"1"; -- mandatory LSB
attribute REGISTER_ACCESS of te18chip_jtag : entity is
-- these are given by standard
-- "BOUNDARY(EXTEST,SAMPLE,INTEST)";
-- "BYPASS(BYPASS)";
"BYPASS (BYPASS)," &
"BOUNDARY (EXTEST)," &
"DEVICE_ID (IDCODE)," &
"BOUNDARY (SAMPLE)," &
"BYPASS (HIGHZ)," &
"BYPASS (SYNTEST_ATPG)," &
"BIST[45] (BIST_MODE)";
--
-- Boundary Register Description for 1149.1 Boundary_Scan_Cell
--
attribute BOUNDARY_LENGTH of te18chip_jtag : entity is 175;
attribute BOUNDARY_REGISTER of te18chip_jtag : entity is
-- num cell port function safe [ccell disval rslt]
"0 (BC_1 ,atestmode ,input ,X)," &
"1 (BC_1 ,mclkin ,input ,X)," &
"2 (BC_1 ,RXTSEL_PAD ,input ,X)," &
"3 (BC_1 ,TXON_PAD ,input ,X)," &
"4 (BC_1 ,reset_l_oe ,input ,X)," &
"5 (BC_7 ,oscclk_t1 ,bidir ,X ,6 ,0 ,PULL0)," &
"6 (BC_1 ,* ,control ,0)," &
"7 (BC_7 ,oscclk_e1 ,bidir ,X ,6 ,0 ,PULL0)," &
"8 (BC_7 ,txserclk_7 ,bidir ,X ,9 ,0 ,PULL1)," &
"9 (BC_1 ,* ,control ,0)," &
"10 (BC_1 ,txser_7 ,input ,X)," &
"11 (BC_7 ,txmsync_7 ,bidir ,X ,12 ,0 ,PULL0)," &
"12 (BC_1 ,* ,control ,0)," &
"13 (BC_7 ,rxserclk_7 ,bidir ,X ,14 ,0 ,PULL1)," &
"14 (BC_1 ,* ,control ,0)," &
"15 (BC_1 ,rxlos_7 ,output3 ,X ,16 ,0 ,Z)," &
"16 (BC_1 ,* ,control ,0)," &
"17 (BC_7 ,txsync_7 ,bidir ,X ,12 ,0 ,PULL0)," &
"18 (BC_1 ,rxcrcsync_7 ,output3 ,X ,19 ,0 ,Z)," &
"19 (BC_1 ,* ,control ,0)," &
"20 (BC_7 ,rxsync_7 ,bidir ,X ,21 ,0 ,PULL0)," &
"21 (BC_1 ,* ,control ,0)," &
"22 (BC_1 ,rxchn_7_4 ,output3 ,X ,19 ,0 ,Z)," &
"23 (BC_1 ,rxser_7 ,output3 ,X ,19 ,0 ,Z)," &
"24 (BC_7 ,txserclk_6 ,bidir ,X ,25 ,0 ,PULL1)," &
"25 (BC_1 ,* ,control ,0)," &
"26 (BC_1 ,rxcasync_7 ,output3 ,X ,19 ,0 ,Z)," &
"27 (BC_7 ,txmsync_6 ,bidir ,X ,28 ,0 ,PULL0)," &
"28 (BC_1 ,* ,control ,0)," &
"29 (BC_7 ,txsync_6 ,bidir ,X ,28 ,0 ,PULL0)," &
"30 (BC_1 ,txser_6 ,input ,X)," &
"31 (BC_1 ,rxcasync_6 ,output3 ,X ,19 ,0 ,Z)," &
"32 (BC_1 ,rxcrcsync_6 ,output3 ,X ,19 ,0 ,Z)," &
"33 (BC_7 ,rxsync_6 ,bidir ,X ,34 ,0 ,PULL0)," &
"34 (BC_1 ,* ,control ,0)," &
"35 (BC_1 ,rxchn_6_4 ,output3 ,X ,19 ,0 ,Z)," &
"36 (BC_7 ,rxserclk_6 ,bidir ,X ,37 ,0 ,PULL1)," &
"37 (BC_1 ,* ,control ,0)," &
"38 (BC_1 ,rxlos_6 ,output3 ,X ,39 ,0 ,Z)," &
"39 (BC_1 ,* ,control ,0)," &
"40 (BC_1 ,rxser_6 ,output3 ,X ,19 ,0 ,Z)," &
"41 (BC_7 ,txserclk_5 ,bidir ,X ,42 ,0 ,PULL1)," &
"42 (BC_1 ,* ,control ,0)," &
"43 (BC_1 ,txser_5 ,input ,X)," &
"44 (BC_7 ,txsync_5 ,bidir ,X ,45 ,0 ,PULL0)," &
"45 (BC_1 ,* ,control ,0)," &
"46 (BC_7 ,txmsync_5 ,bidir ,X ,45 ,0 ,PULL0)," &
"47 (BC_1 ,rxchn_5_4 ,output3 ,X ,19 ,0 ,Z)," &
"48 (BC_1 ,rxser_5 ,output3 ,X ,19 ,0 ,Z)," &
"49 (BC_7 ,rxsync_5 ,bidir ,X ,50 ,0 ,PULL0)," &
"50 (BC_1 ,* ,control ,0)," &
"51 (BC_1 ,rxcasync_5 ,output3 ,X ,19 ,0 ,Z)," &
"52 (BC_7 ,rxserclk_5 ,bidir ,X ,53 ,0 ,PULL1)," &
"53 (BC_1 ,* ,control ,0)," &
"54 (BC_1 ,rxlos_5 ,output3 ,X ,55 ,0 ,Z)," &
"55 (BC_1 ,* ,control ,0)," &
"56 (BC_1 ,rxcrcsync_5 ,output3 ,X ,19 ,0 ,Z)," &
"57 (BC_7 ,txmsync_4 ,bidir ,X ,58 ,0 ,PULL0)," &
"58 (BC_1 ,* ,control ,0)," &
"59 (BC_7 ,txsync_4 ,bidir ,X ,58 ,0 ,PULL0)," &
"60 (BC_7 ,txserclk_4 ,bidir ,X ,61 ,0 ,PULL1)," &
"61 (BC_1 ,* ,control ,0)," &
"62 (BC_1 ,txser_4 ,input ,X)," &
"63 (BC_1 ,rxcasync_4 ,output3 ,X ,19 ,0 ,Z)," &
"64 (BC_1 ,rxchn_4_4 ,output3 ,X ,19 ,0 ,Z)," &
"65 (BC_1 ,rxser_4 ,output3 ,X ,19 ,0 ,Z)," &
"66 (BC_7 ,rxsync_4 ,bidir ,X ,67 ,0 ,PULL0)," &
"67 (BC_1 ,* ,control ,0)," &
"68 (BC_1 ,rxcrcsync_4 ,output3 ,X ,19 ,0 ,Z)," &
"69 (BC_1 ,preq_l_1 ,output3 ,X ,19 ,0 ,Z)," &
"70 (BC_7 ,rxserclk_4 ,bidir ,X ,71 ,0 ,PULL1)," &
"71 (BC_1 ,* ,control ,0)," &
"72 (BC_1 ,rxlos_4 ,output3 ,X ,73 ,0 ,Z)," &
"73 (BC_1 ,* ,control ,0)," &
"74 (BC_1 ,pack_l_0 ,input ,X)," &
"75 (BC_1 ,preq_l_0 ,output3 ,X ,19 ,0 ,Z)," &
"76 (BC_1 ,ptype_0 ,input ,X)," &
"77 (BC_1 ,pack_l_1 ,input ,X)," &
"78 (BC_1 ,pclk ,input ,X)," &
"79 (BC_7 ,pdata_0 ,bidir ,X ,80 ,0 ,Z)," &
"80 (BC_1 ,* ,control ,0)," &
"81 (BC_7 ,pdata_1 ,bidir ,X ,80 ,0 ,Z)," &
"82 (BC_1 ,prd_l ,input ,X)," &
"83 (BC_1 ,ptype_1 ,input ,X)," &
"84 (BC_1 ,pdack_l ,output3 ,X ,19 ,0 ,Z)," &
"85 (BC_1 ,paddr_0 ,input ,X)," &
"86 (BC_1 ,paddr_1 ,input ,X)," &
"87 (BC_1 ,paddr_2 ,input ,X)," &
"88 (BC_1 ,paddr_3 ,input ,X)," &
"89 (BC_1 ,paddr_4 ,input ,X)," &
"90 (BC_1 ,paddr_5 ,input ,X)," &
"91 (BC_1 ,paddr_6 ,input ,X)," &
"92 (BC_1 ,paddr_7 ,input ,X)," &
"93 (BC_1 ,paddr_0_8 ,input ,X)," &
"94 (BC_7 ,pdata_2 ,bidir ,X ,80 ,0 ,Z)," &
"95 (BC_7 ,pdata_3 ,bidir ,X ,80 ,0 ,Z)," &
"96 (BC_1 ,pas_l ,input ,X)," &
"97 (BC_1 ,paddr_1_9 ,input ,X)," &
"98 (BC_1 ,paddr_2_10 ,input ,X)," &
"99 (BC_1 ,ptype_2 ,input ,X)," &
"100 (BC_1 ,pint_l ,output3 ,X ,19 ,0 ,Z)," &
"101 (BC_1 ,paddr_3_11 ,input ,X)," &
"102 (BC_7 ,pdata_4 ,bidir ,X ,80 ,0 ,Z)," &
"103 (BC_1 ,paddr_4_12 ,input ,X)," &
"104 (BC_7 ,pdata_5 ,bidir ,X ,80 ,0 ,Z)," &
"105 (BC_7 ,pdata_6 ,bidir ,X ,80 ,0 ,Z)," &
"106 (BC_1 ,paddr_5_13 ,input ,X)," &
"107 (BC_1 ,paddr_6_14 ,input ,X)," &
"108 (BC_7 ,pdata_7 ,bidir ,X ,80 ,0 ,Z)," &
"109 (BC_1 ,pwr_l ,input ,X)," &
"110 (BC_1 ,pcs_l ,input ,X)," &
"111 (BC_7 ,txmsync_3 ,bidir ,X ,112 ,0 ,PULL0)," &
"112 (BC_1 ,* ,control ,0)," &
"113 (BC_1 ,txser_3 ,input ,X)," &
"114 (BC_1 ,rxchn_3_4 ,output3 ,X ,19 ,0 ,Z)," &
"115 (BC_7 ,txserclk_3 ,bidir ,X ,116 ,0 ,PULL1)," &
"116 (BC_1 ,* ,control ,0)," &
"117 (BC_7 ,txsync_3 ,bidir ,X ,112 ,0 ,PULL0)," &
"118 (BC_7 ,rxserclk_3 ,bidir ,X ,119 ,0 ,PULL1)," &
"119 (BC_1 ,* ,control ,0)," &
"120 (BC_1 ,rxlos_3 ,output3 ,X ,121 ,0 ,Z)," &
"121 (BC_1 ,* ,control ,0)," &
"122 (BC_1 ,rxcasync_3 ,output3 ,X ,19 ,0 ,Z)," &
"123 (BC_1 ,rxcrcsync_3 ,output3 ,X ,19 ,0 ,Z)," &
"124 (BC_7 ,rxsync_3 ,bidir ,X ,125 ,0 ,PULL0)," &
"125 (BC_1 ,* ,control ,0)," &
"126 (BC_1 ,rxser_3 ,output3 ,X ,19 ,0 ,Z)," &
"127 (BC_1 ,txser_2 ,input ,X)," &
"128 (BC_7 ,txmsync_2 ,bidir ,X ,129 ,0 ,PULL0)," &
"129 (BC_1 ,* ,control ,0)," &
"130 (BC_1 ,rxchn_2_4 ,output3 ,X ,19 ,0 ,Z)," &
"131 (BC_7 ,txserclk_2 ,bidir ,X ,132 ,0 ,PULL1)," &
"132 (BC_1 ,* ,control ,0)," &
"133 (BC_7 ,txsync_2 ,bidir ,X ,129 ,0 ,PULL0)," &
"134 (BC_1 ,rxser_2 ,output3 ,X ,19 ,0 ,Z)," &
"135 (BC_1 ,rxcrcsync_2 ,output3 ,X ,19 ,0 ,Z)," &
"136 (BC_1 ,rxcasync_2 ,output3 ,X ,19 ,0 ,Z)," &
"137 (BC_7 ,rxserclk_2 ,bidir ,X ,138 ,0 ,PULL1)," &
"138 (BC_1 ,* ,control ,0)," &
"139 (BC_1 ,rxlos_2 ,output3 ,X ,140 ,0 ,Z)," &
"140 (BC_1 ,* ,control ,0)," &
"141 (BC_7 ,txserclk_1 ,bidir ,X ,142 ,0 ,PULL1)," &
"142 (BC_1 ,* ,control ,0)," &
"143 (BC_7 ,rxsync_2 ,bidir ,X ,144 ,0 ,PULL0)," &
"144 (BC_1 ,* ,control ,0)," &
"145 (BC_1 ,txser_1 ,input ,X)," &
"146 (BC_1 ,rxchn_1_4 ,output3 ,X ,19 ,0 ,Z)," &
"147 (BC_7 ,txmsync_1 ,bidir ,X ,148 ,0 ,PULL0)," &
"148 (BC_1 ,* ,control ,0)," &
"149 (BC_7 ,txsync_1 ,bidir ,X ,148 ,0 ,PULL0)," &
"150 (BC_1 ,rxlos_1 ,output3 ,X ,151 ,0 ,Z)," &
"151 (BC_1 ,* ,control ,0)," &
"152 (BC_1 ,rxcasync_1 ,output3 ,X ,19 ,0 ,Z)," &
"153 (BC_7 ,rxsync_1 ,bidir ,X ,154 ,0 ,PULL0)," &
"154 (BC_1 ,* ,control ,0)," &
"155 (BC_1 ,rxser_1 ,output3 ,X ,19 ,0 ,Z)," &
"156 (BC_7 ,rxserclk_1 ,bidir ,X ,157 ,0 ,PULL1)," &
"157 (BC_1 ,* ,control ,0)," &
"158 (BC_1 ,rxcrcsync_1 ,output3 ,X ,19 ,0 ,Z)," &
"159 (BC_7 ,txserclk_0 ,bidir ,X ,160 ,0 ,PULL1)," &
"160 (BC_1 ,* ,control ,0)," &
"161 (BC_1 ,txser_0 ,input ,X)," &
"162 (BC_1 ,rxchn_0_4 ,output3 ,X ,19 ,0 ,Z)," &
"163 (BC_7 ,txmsync_0 ,bidir ,X ,164 ,0 ,PULL0)," &
"164 (BC_1 ,* ,control ,0)," &
"165 (BC_1 ,rxcasync_0 ,output3 ,X ,19 ,0 ,Z)," &
"166 (BC_7 ,txsync_0 ,bidir ,X ,164 ,0 ,PULL0)," &
"167 (BC_7 ,rxsync_0 ,bidir ,X ,168 ,0 ,PULL0)," &
"168 (BC_1 ,* ,control ,0)," &
"169 (BC_1 ,rxcrcsync_0 ,output3 ,X ,19 ,0 ,Z)," &
"170 (BC_7 ,rxserclk_0 ,bidir ,X ,171 ,0 ,PULL1)," &
"171 (BC_1 ,* ,control ,0)," &
"172 (BC_1 ,rxlos_0 ,output3 ,X ,173 ,0 ,Z)," &
"173 (BC_1 ,* ,control ,0)," &
"174 (BC_1 ,rxser_0 ,output3 ,X ,19 ,0 ,Z)";
end te18chip_jtag;
