BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: IDT72T1875

	idt72t1875.bsdl0000775000277400015630000002414211225475520013065 0ustar  jduhfcmdesign-- Boundary Scan Description Language (BSDL) for IDT72T1875
-- BSDL revision : 1.0
-- Date created  : 07/10/01
-- Last updated  : 07/10/01
-- Packages      : 144-Pin BGA

entity idt72t1875 is
    generic (PHYSICAL_PIN_MAP : string :=  "BB144");
    port (
        D                       :in             bit_vector(0 to 17);
        IW                      :in             bit;
        SCLK                    :in             bit;
        SENB                    :in             bit;
        WENB                    :in             bit;
        WCSB                    :in             bit;
        WCLK                    :in             bit;
        PRSB                    :in             bit;
        MRSB                    :in             bit;
        MARK                    :in             bit;
        ASYRB                   :in             bit;
        ASYWB                   :in             bit;
        ERCLK                   :buffer         bit;
        ERENB                   :buffer         bit;
        SHSTL                   :in             bit;
        WHSTL                   :in             bit;
        LDB                     :in             bit;
        FWFTSI                  :in             bit;
        FF                      :buffer         bit;
        PAF                     :buffer         bit;
        OW                      :in             bit;
        FSEL                    :in             bit_vector(0 to 1);
        HF                      :buffer         bit;
        BEB                     :in             bit;
        IP                      :in             bit;
        PAE                     :buffer         bit;
        PFM                     :in             bit;
        EF                      :buffer         bit;
        RCLK                    :in             bit;
        RENB                    :in             bit;
        RHSTL                   :in             bit;
        RTB                     :in             bit;
        OEB                     :in             bit;
        RCSB                    :in             bit;
        Q                       :buffer         bit_vector(0 to 17);
        TCK                     :in             bit;
        TMS                     :in             bit;
        TDI                     :in             bit;
        TRSTB                   :in             bit;
        TDO                     :out            bit;
        NC                      :linkage        bit;
        VREF                    :linkage        bit;
        VDDQ                    :linkage        bit_vector(0 to 18);
        GND                     :linkage        bit_vector(0 to 24);
        VDD                     :linkage        bit_vector(0 to 18)
    );

    use STD_1149_1_1994.all;

    attribute COMPONENT_CONFORMANCE of idt72t1875 : entity is
    "STD_1149_1_1993";

    attribute PIN_MAP of idt72t1875 : entity is PHYSICAL_PIN_MAP;

    constant BB144 : PIN_MAP_STRING :=
        "D      : (M5, L4, M4, L3, M3, L2, M2, L1, M1,  "&
	         " K1, K2, J1, J2, H1, H2, G1, G2, F2), "&
        "IW     : E2,  "&
        "SCLK   : E1,  "&
        "SENB   : D2,  "&
        "ASYWB  : D1,  "&
        "WHSTL  : C2,  "&
        "WENB   : C1,  "&
        "WCLK   : B1,  "&
        "WCSB   : A1,  "&
        "PRSB   : A2,  "&
        "MRSB   : B2,  "&
        "LDB    : A3,  "&
        "FWFTSI : B3,  "&
        "FF     : A4,  "&
        "PAF    : B4,  "&
        "OW     : A5,  "&
        "FSEL   : (B5, B7)," &
        "HF     : A6,  "&
        "SHSTL  : B6,  "&
        "BEB    : A7,  "&
        "IP     : A8,  "&
        "ASYRB  : A9,  "&
        "RHSTL  : B9,  "&
        "PFM    : A10, "&
        "PAE    : B10, "&
        "ERENB  : A11, "&
        "MARK   : A12, "&
        "EF     : B11, "&
        "RCLK   : B12, "&
        "RENB   : C11, "&
        "RTB    : C12, "&
        "RCSB   : D11, "&
        "OEB    : D12, "&
        "ERCLK  : L8,  "&
        "Q      : (M8,  L9,  M9,  L10, M10, L11, M11, M12, L12,  "&
	         " K12, K11, J12, J11, H12, H11, G12, F12, E12), "&
        "TCK    : L6,  "&
        "TMS    : M6,  "&
        "TDI    : L7,  "&
        "TDO    : M7,  "&
        "TRSTB  : L5,  "&
        "NC     : B8,  "&
        "VREF   : F1,  "&
        "VDDQ   : (C3,  C4,  C5,  C8, C9, C10, D3,  D10, E3,  H3, "&
		 " H10, J3,  J10, K3, K4, K5,  K8,  K9,  K10), "&
        "VDD    : (C6,  C7,  D4,  D5, D8, D9,  E10, F3,  F10, G3, "&
	         " G10, H4,  H9,  J4, J5, J8,  J9,  K6,  K7), "&
        "GND    : (D6,  D7,  E5,  E6, E7, E8,  E9,  F4,  F5,  F6, "&
		 " F7,  F8,  F9,  G4, G5, G6,  G7,  G8,  G9,  H5, "&
		 " H6,  H7,  H8,  J6, J7 )";

    --Scan port identification
    attribute TAP_SCAN_IN    of tdi   : signal is true;
    attribute TAP_SCAN_MODE  of tms   : signal is true;
    attribute TAP_SCAN_OUT   of tdo   : signal is true;
    attribute TAP_SCAN_CLOCK of tck   : signal is (1.0e7, LOW);
    attribute TAP_SCAN_RESET of trstb : signal is true;

    --Compliance to avoid oe issue
    attribute COMPLIANCE_PATTERNS of idt72t1875: entity is
        "(OEB, IW, OW, WHSTL, RHSTL, SHSTL) (000111)";

    --TAP Description
    attribute INSTRUCTION_LENGTH of idt72t1875 : entity is 4;
    attribute INSTRUCTION_OPCODE of idt72t1875 : entity is
        "EXTEST          (0000)," &
        "SAMPLE          (0001)," &
        "IDCODE          (0010)," &
        "HIGHZ           (0011)," &
        "BYPASS          (1111)";
    attribute INSTRUCTION_CAPTURE of idt72t1875 : entity is "1101";

    attribute IDCODE_REGISTER of idt72t1875 : entity is
        "0000" &                -- version
        "0000010000001011" &    -- part number
        "00000110011" &         -- manufacturer's identity
        "1";                    -- required by 1149.1
    --  Part IDCODE:
    --  1895 "0000010000001001"
    --  1885 "0000010000001010"
    --  1875 "0000010000001011"
    --  1865 "0000010000001100"
    --  1855 "0000010000001101"
    --  1845 "0000010000001110"

    attribute REGISTER_ACCESS of idt72t1875 : entity is
        "Bypass          (BYPASS, HIGHZ)," &
        "Boundary        (SAMPLE, EXTEST)," &
        "Device_ID       (IDCODE)";

    attribute BOUNDARY_LENGTH of idt72t1875 : entity is 70;

    attribute BOUNDARY_REGISTER  of idt72t1875 : entity is
     --
     -- num   cell   port     function safe[ccell disval rslt]
     --
        "69  (BC_0,  D(0),       input,      X)," &
        "68  (BC_0,  D(1),       input,      X)," &
        "67  (BC_0,  D(2),       input,      X)," &
        "66  (BC_0,  D(3),       input,      X)," &
        "65  (BC_0,  D(4),       input,      X)," &
        "64  (BC_0,  D(5),       input,      X)," &
        "63  (BC_0,  D(6),       input,      X)," &
        "62  (BC_0,  D(7),       input,      X)," &
        "61  (BC_0,  D(8),       input,      X)," &
        "60  (BC_0,  D(9),       input,      X)," &
        "59  (BC_0,  D(10),      input,      X)," &
        "58  (BC_0,  D(11),      input,      X)," &
        "57  (BC_0,  D(12),      input,      X)," &
        "56  (BC_0,  D(13),      input,      X)," &
        "55  (BC_0,  D(14),      input,      X)," &
        "54  (BC_0,  D(15),      input,      X)," &
        "53  (BC_0,  D(16),      input,      X)," &
        "52  (BC_0,  D(17),      input,      X)," &
        "51  (BC_0,  *,          internal,   X)," &
      --"51  (BC_0,  IW,         input,      X)," &
        "50  (BC_0,  SCLK,       input,      X)," &
        "49  (BC_0,  SENB,       input,      X)," &
        "48  (BC_0,  ASYWB,      input,      X)," &
        "47  (BC_0,  *,          internal,   X)," &
      --"47  (BC_0,  WHSTL,      input,      X)," &
        "46  (BC_0,  WENB,       input,      X)," &
        "45  (BC_0,  WCSB,       input,      X)," &
        "44  (BC_0,  WCLK,       input,      X)," &
        "43  (BC_0,  PRSB,       input,      X)," &
        "42  (BC_0,  MRSB,       input,      X)," &
        "41  (BC_0,  LDB,        input,      X)," &
        "40  (BC_0,  FWFTSI,     input,      X)," &
        "39  (BC_0,  FF,         output2,    X)," &
        "38  (BC_0,  PAF,        output2,    X)," &
        "37  (BC_0,  *,          internal,   X)," &
      --"37  (BC_0,  OW,         input,      X)," &
        "36  (BC_0,  FSEL(0),    input,      X)," &
        "35  (BC_0,  HF,         output2,    X)," &
        "34  (BC_0,  *,          internal,   X)," &
      --"34  (BC_0,  SHSTL,      input,      X)," &
        "33  (BC_0,  FSEL(1),    input,      X)," &
        "32  (BC_0,  BEB,        input,      X)," &
        "31  (BC_0,  IP,         input,      X)," &
        "30  (BC_0,  *,          internal,   X)," &
      --"30  (BC_0,  RHSTL,      input,      X)," &
        "29  (BC_0,  ASYRB,      input,      X)," &
        "28  (BC_0,  PAE,        output2,    X)," &
        "27  (BC_0,  PFM,        input,      X)," &
        "26  (BC_0,  EF,         output2,    X)," &
        "25  (BC_0,  ERENB,      output2,    X)," &
        "24  (BC_0,  MARK,       input,      X)," &
        "23  (BC_0,  RCLK,       input,      X)," &
        "22  (BC_0,  RENB,       input,      X)," &
        "21  (BC_0,  RTB,        input,      X)," &
        "20  (BC_0,  RCSB,       input,      X)," &
        "19  (BC_0,  *,          internal,   X)," &
      --"19  (BC_0,  OEB,        input,      X)," &
        "18  (BC_0,  Q(17),      output2,    X)," &
        "17  (BC_0,  Q(16),      output2,    X)," &
        "16  (BC_0,  Q(15),      output2,    X)," &
        "15  (BC_0,  Q(14),      output2,    X)," &
        "14  (BC_0,  Q(13),      output2,    X)," &
        "13  (BC_0,  Q(12),      output2,    X)," &
        "12  (BC_0,  Q(11),      output2,    X)," &
        "11  (BC_0,  Q(10),      output2,    X)," &
        "10  (BC_0,  Q(9),       output2,    X)," &
        "9   (BC_0,  Q(8),       output2,    X)," &
        "8   (BC_0,  Q(7),       output2,    X)," &
        "7   (BC_0,  Q(6),       output2,    X)," &
        "6   (BC_0,  Q(5),       output2,    X)," &
        "5   (BC_0,  Q(4),       output2,    X)," &
        "4   (BC_0,  Q(3),       output2,    X)," &
        "3   (BC_0,  Q(2),       output2,    X)," &
        "2   (BC_0,  Q(1),       output2,    X)," &
        "1   (BC_0,  Q(0),       output2,    X)," &
        "0   (BC_0,  ERCLK,      output2,    X)";

end idt72t1875;