-- $ XILINX$RCSfile: xc2c64a_vq44.bsd,v $
-- $ XILINX$Revision: 1.6 $
--
-- BSDL file for device XC2C64, package VQ44
-- Xilinx, Inc. $State: PRELIMINARY $ $Date: 2006/10/17 16:43:41 $
-- Generated by 1149.pl
-- =================================================
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--
entity xc2c64a_vq44 is
generic (PHYSICAL_PIN_MAP : string := "VQ44");
port ( tdi : in bit;
tck : in bit;
tms : in bit;
tdo : out bit;
IO_0 : inout bit;
IO_1 : inout bit;
IO_2 : inout bit;
IO_8 : inout bit;
IO_9 : inout bit;
IO_10 : inout bit;
IO_11 : inout bit;
IO_12 : inout bit;
IO_16 : inout bit;
IO_17 : inout bit;
IO_20 : inout bit;
IO_21 : inout bit;
IO_22 : inout bit;
IO_23 : inout bit;
IO_25 : inout bit;
IO_27 : inout bit;
IO_28 : inout bit;
IO_32 : inout bit;
IO_33 : inout bit;
IO_34 : inout bit;
IO_37 : inout bit;
IO_41 : inout bit;
IO_42 : inout bit;
IO_43 : inout bit;
IO_45 : inout bit;
IO_46 : inout bit;
IO_48 : inout bit;
IO_49 : inout bit;
IO_54 : inout bit;
IO_58 : inout bit;
IO_60 : inout bit;
IO_61 : inout bit;
vdd : linkage bit_vector(1 to 3);
gnd : linkage bit_vector(1 to 3);
IO_62 : inout bit);
use std_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of xc2c64a_vq44 : entity is "std_1149_1_1993";
attribute PIN_MAP of xc2c64a_vq44 : entity is PHYSICAL_PIN_MAP;
constant VQ44 : PIN_MAP_STRING :=
" tdi:9, tck:11, tms:10, tdo:24," &
" IO_0:38, IO_1:37, IO_2:36," &
" IO_8:34, IO_9:33," &
" IO_10:32, IO_11:31, IO_12:30," &
" IO_16:39, IO_17:40," &
" IO_20:41, IO_21:42, IO_22:43, IO_23:44," &
" IO_25:1, IO_27:2, IO_28:3," &
" IO_32:29, IO_33:28, IO_34:27," &
" IO_37:23," &
" IO_41:22, IO_42:21, IO_43:20," &
" IO_45:19, IO_46:18, IO_48:5, IO_49:6," &
" IO_54:8," &
" IO_58:12," &
" vdd : (7,15,26)," &
" gnd : (4,17,25), " &
" IO_60:13, IO_61:14, IO_62:16";
attribute TAP_SCAN_IN of tdi : signal is true;
attribute TAP_SCAN_CLOCK of tck : signal is (33.0e6, both);
attribute TAP_SCAN_MODE of tms : signal is true;
attribute TAP_SCAN_OUT of tdo : signal is true;
attribute INSTRUCTION_LENGTH of xc2c64a_vq44 : entity is 8;
attribute INSTRUCTION_OPCODE of xc2c64a_vq44 : entity is
"INTEST (00000010)," &
"BYPASS (11111111)," &
"SAMPLE (00000011)," &
"EXTEST (00000000)," &
"IDCODE (00000001)," &
"USERCODE (11111101)," &
"HIGHZ (11111100)," &
"ISC_ENABLE_CLAMP (11101001)," &
"ISC_ENABLEOTF (11100100)," &
"ISC_ENABLE (11101000)," &
"ISC_SRAM_READ (11100111)," &
"ISC_SRAM_WRITE (11100110)," &
"ISC_ERASE (11101101)," &
"ISC_PROGRAM (11101010)," &
"ISC_READ (11101110)," &
"ISC_INIT (11110000)," &
"ISC_DISABLE (11000000)," &
"TEST_ENABLE (00010001)," &
"BULKPROG (00010010)," &
"ERASE_ALL (00010100)," &
"MVERIFY (00010011)," &
"TEST_DISABLE (00010101)," &
-- "STCTEST (00010110)," &
"ISC_NOOP (11100000)";
attribute INSTRUCTION_CAPTURE of xc2c64a_vq44 : entity is "XXXXXX01" ;
attribute IDCODE_REGISTER of xc2c64a_vq44 : entity is "XXXX0110111001011110000010010011";
attribute USERCODE_REGISTER of xc2c64a_vq44 : entity is "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
attribute REGISTER_ACCESS of xc2c64a_vq44 : entity is
"BYPASS (BYPASS)," &
"BYPASS (HIGHZ)," &
"BOUNDARY (SAMPLE)," &
"BOUNDARY (EXTEST)," &
"BOUNDARY (INTEST)," &
"DATAREG[281] (ISC_ENABLEOTF)," &
"DATAREG[281] (ISC_ENABLE)," &
"DATAREG[281] (ISC_SRAM_READ)," &
"DATAREG[281] (ISC_SRAM_WRITE)," &
"DATAREG[281] (ISC_ERASE)," &
"DATAREG[281] (ISC_PROGRAM)," &
"DATAREG[281] (ISC_READ)," &
"DATAREG[281] (ISC_INIT)," &
"DATAREG[281] (ISC_DISABLE)," &
"DATAREG[281] (TEST_ENABLE)," &
"DATAREG[281] (BULKPROG)," &
"DATAREG[281] (ERASE_ALL)," &
"DATAREG[281] (MVERIFY)," &
"DATAREG[281] (TEST_DISABLE)," &
-- "STC[] (STCTEST)," &
"ISC_DEFAULT[1] (ISC_NOOP)," &
"DEVICE_ID (IDCODE, USERCODE)," &
"ISC_DEFAULT[1] (ISC_ENABLE_CLAMP)";
attribute BOUNDARY_LENGTH of xc2c64a_vq44 : entity is 192;
attribute BOUNDARY_REGISTER of xc2c64a_vq44 : entity is
--
-- num cell port function safe [ccell disval rslt]
--
" 191 (BC_1, IO_0, INPUT, X)," &
" 190 (BC_1, IO_0, OUTPUT3, X, 189, 0,Z),"&
" 189 (BC_1, *, CONTROL, 0)," &
" 188 (BC_1, IO_1, INPUT, X)," &
" 187 (BC_1, IO_1, OUTPUT3, X, 186, 0,Z),"&
" 186 (BC_1, *, CONTROL, 0)," &
" 185 (BC_1, IO_2, INPUT, X)," &
" 184 (BC_1, IO_2, OUTPUT3, X, 183, 0,Z),"&
" 183 (BC_1, *, CONTROL, 0)," &
" 182 (BC_1, *, INTERNAL, X)," &
" 181 (BC_1, *, INTERNAL, X)," &
" 180 (BC_1, *, INTERNAL, X)," &
" 179 (BC_1, *, INTERNAL, X)," &
" 178 (BC_1, *, INTERNAL, X)," &
" 177 (BC_1, *, INTERNAL, X)," &
" 176 (BC_1, *, INTERNAL, X)," &
" 175 (BC_1, *, INTERNAL, X)," &
" 174 (BC_1, *, INTERNAL, X)," &
" 173 (BC_1, *, INTERNAL, X)," &
" 172 (BC_1, *, INTERNAL, X)," &
" 171 (BC_1, *, INTERNAL, X)," &
" 170 (BC_1, *, INTERNAL, X)," &
" 169 (BC_1, *, INTERNAL, X)," &
" 168 (BC_1, *, INTERNAL, X)," &
" 167 (BC_1, IO_8, INPUT, X)," &
" 166 (BC_1, IO_8, OUTPUT3, X, 165, 0,Z),"&
" 165 (BC_1, *, CONTROL, 0)," &
" 164 (BC_1, IO_9, INPUT, X)," &
" 163 (BC_1, IO_9, OUTPUT3, X, 162, 0,Z),"&
" 162 (BC_1, *, CONTROL, 0)," &
" 161 (BC_1, IO_10, INPUT, X)," &
" 160 (BC_1, IO_10, OUTPUT3, X, 159, 0,Z),"&
" 159 (BC_1, *, CONTROL, 0)," &
" 158 (BC_1, IO_11, INPUT, X)," &
" 157 (BC_1, IO_11, OUTPUT3, X, 156, 0,Z),"&
" 156 (BC_1, *, CONTROL, 0)," &
" 155 (BC_1, IO_12, INPUT, X)," &
" 154 (BC_1, IO_12, OUTPUT3, X, 153, 0,Z),"&
" 153 (BC_1, *, CONTROL, 0)," &
" 152 (BC_1, *, INTERNAL, X)," &
" 151 (BC_1, *, INTERNAL, X)," &
" 150 (BC_1, *, INTERNAL, X)," &
" 149 (BC_1, *, INTERNAL, X)," &
" 148 (BC_1, *, INTERNAL, X)," &
" 147 (BC_1, *, INTERNAL, X)," &
" 146 (BC_1, *, INTERNAL, X)," &
" 145 (BC_1, *, INTERNAL, X)," &
" 144 (BC_1, *, INTERNAL, X)," &
" 143 (BC_1, IO_32, INPUT, X)," &
" 142 (BC_1, IO_32, OUTPUT3, X, 141, 0,Z),"&
" 141 (BC_1, *, CONTROL, 0)," &
" 140 (BC_1, IO_33, INPUT, X)," &
" 139 (BC_1, IO_33, OUTPUT3, X, 138, 0,Z),"&
" 138 (BC_1, *, CONTROL, 0)," &
" 137 (BC_1, IO_34, INPUT, X)," &
" 136 (BC_1, IO_34, OUTPUT3, X, 135, 0,Z),"&
" 135 (BC_1, *, CONTROL, 0)," &
" 134 (BC_1, *, INTERNAL, X)," &
" 133 (BC_1, *, INTERNAL, X)," &
" 132 (BC_1, *, INTERNAL, X)," &
" 131 (BC_1, *, INTERNAL, X)," &
" 130 (BC_1, *, INTERNAL, X)," &
" 129 (BC_1, *, INTERNAL, X)," &
" 128 (BC_1, IO_37, INPUT, X)," &
" 127 (BC_1, IO_37, OUTPUT3, X, 126, 0,Z),"&
" 126 (BC_1, *, CONTROL, 0)," &
" 125 (BC_1, *, INTERNAL, X)," &
" 124 (BC_1, *, INTERNAL, X)," &
" 123 (BC_1, *, INTERNAL, X)," &
" 122 (BC_1, *, INTERNAL, X)," &
" 121 (BC_1, *, INTERNAL, X)," &
" 120 (BC_1, *, INTERNAL, X)," &
" 119 (BC_1, *, INTERNAL, X)," &
" 118 (BC_1, *, INTERNAL, X)," &
" 117 (BC_1, *, INTERNAL, X)," &
" 116 (BC_1, IO_41, INPUT, X)," &
" 115 (BC_1, IO_41, OUTPUT3, X, 114, 0,Z),"&
" 114 (BC_1, *, CONTROL, 0)," &
" 113 (BC_1, IO_42, INPUT, X)," &
" 112 (BC_1, IO_42, OUTPUT3, X, 111, 0,Z),"&
" 111 (BC_1, *, CONTROL, 0)," &
" 110 (BC_1, IO_43, INPUT, X)," &
" 109 (BC_1, IO_43, OUTPUT3, X, 108, 0,Z),"&
" 108 (BC_1, *, CONTROL, 0)," &
" 107 (BC_1, *, INTERNAL, X)," &
" 106 (BC_1, *, INTERNAL, X)," &
" 105 (BC_1, *, INTERNAL, X)," &
" 104 (BC_1, IO_45, INPUT, X)," &
" 103 (BC_1, IO_45, OUTPUT3, X, 102, 0,Z),"&
" 102 (BC_1, *, CONTROL, 0)," &
" 101 (BC_1, IO_46, INPUT, X)," &
" 100 (BC_1, IO_46, OUTPUT3, X, 99, 0,Z),"&
" 99 (BC_1, *, CONTROL, 0)," &
" 98 (BC_1, *, INTERNAL, X)," &
" 97 (BC_1, *, INTERNAL, X)," &
" 96 (BC_1, *, INTERNAL, X)," &
" 95 (BC_1, IO_16, INPUT, X)," &
" 94 (BC_1, IO_16, OUTPUT3, X, 93, 0,Z),"&
" 93 (BC_1, *, CONTROL, 0)," &
" 92 (BC_1, IO_17, INPUT, X)," &
" 91 (BC_1, IO_17, OUTPUT3, X, 90, 0,Z),"&
" 90 (BC_1, *, CONTROL, 0)," &
" 89 (BC_1, *, INTERNAL, X)," &
" 88 (BC_1, *, INTERNAL, X)," &
" 87 (BC_1, *, INTERNAL, X)," &
" 86 (BC_1, *, INTERNAL, X)," &
" 85 (BC_1, *, INTERNAL, X)," &
" 84 (BC_1, *, INTERNAL, X)," &
" 83 (BC_1, IO_20, INPUT, X)," &
" 82 (BC_1, IO_20, OUTPUT3, X, 81, 0,Z),"&
" 81 (BC_1, *, CONTROL, 0)," &
" 80 (BC_1, IO_21, INPUT, X)," &
" 79 (BC_1, IO_21, OUTPUT3, X, 78, 0,Z),"&
" 78 (BC_1, *, CONTROL, 0)," &
" 77 (BC_1, IO_22, INPUT, X)," &
" 76 (BC_1, IO_22, OUTPUT3, X, 75, 0,Z),"&
" 75 (BC_1, *, CONTROL, 0)," &
" 74 (BC_1, IO_23, INPUT, X)," &
" 73 (BC_1, IO_23, OUTPUT3, X, 72, 0,Z),"&
" 72 (BC_1, *, CONTROL, 0)," &
" 71 (BC_1, *, INTERNAL, X)," &
" 70 (BC_1, *, INTERNAL, X)," &
" 69 (BC_1, *, INTERNAL, X)," &
" 68 (BC_1, IO_25, INPUT, X)," &
" 67 (BC_1, IO_25, OUTPUT3, X, 66, 0,Z),"&
" 66 (BC_1, *, CONTROL, 0)," &
" 65 (BC_1, *, INTERNAL, X)," &
" 64 (BC_1, *, INTERNAL, X)," &
" 63 (BC_1, *, INTERNAL, X)," &
" 62 (BC_1, IO_27, INPUT, X)," &
" 61 (BC_1, IO_27, OUTPUT3, X, 60, 0,Z),"&
" 60 (BC_1, *, CONTROL, 0)," &
" 59 (BC_1, IO_28, INPUT, X)," &
" 58 (BC_1, IO_28, OUTPUT3, X, 57, 0,Z),"&
" 57 (BC_1, *, CONTROL, 0)," &
" 56 (BC_1, *, INTERNAL, X)," &
" 55 (BC_1, *, INTERNAL, X)," &
" 54 (BC_1, *, INTERNAL, X)," &
" 53 (BC_1, *, INTERNAL, X)," &
" 52 (BC_1, *, INTERNAL, X)," &
" 51 (BC_1, *, INTERNAL, X)," &
" 50 (BC_1, *, INTERNAL, X)," &
" 49 (BC_1, *, INTERNAL, X)," &
" 48 (BC_1, *, INTERNAL, X)," &
" 47 (BC_1, IO_48, INPUT, X)," &
" 46 (BC_1, IO_48, OUTPUT3, X, 45, 0,Z),"&
" 45 (BC_1, *, CONTROL, 0)," &
" 44 (BC_1, IO_49, INPUT, X)," &
" 43 (BC_1, IO_49, OUTPUT3, X, 42, 0,Z),"&
" 42 (BC_1, *, CONTROL, 0)," &
" 41 (BC_1, *, INTERNAL, X)," &
" 40 (BC_1, *, INTERNAL, X)," &
" 39 (BC_1, *, INTERNAL, X)," &
" 38 (BC_1, *, INTERNAL, X)," &
" 37 (BC_1, *, INTERNAL, X)," &
" 36 (BC_1, *, INTERNAL, X)," &
" 35 (BC_1, *, INTERNAL, X)," &
" 34 (BC_1, *, INTERNAL, X)," &
" 33 (BC_1, *, INTERNAL, X)," &
" 32 (BC_1, *, INTERNAL, X)," &
" 31 (BC_1, *, INTERNAL, X)," &
" 30 (BC_1, *, INTERNAL, X)," &
" 29 (BC_1, IO_54, INPUT, X)," &
" 28 (BC_1, IO_54, OUTPUT3, X, 27, 0,Z),"&
" 27 (BC_1, *, CONTROL, 0)," &
" 26 (BC_1, *, INTERNAL, X)," &
" 25 (BC_1, *, INTERNAL, X)," &
" 24 (BC_1, *, INTERNAL, X)," &
" 23 (BC_1, *, INTERNAL, X)," &
" 22 (BC_1, *, INTERNAL, X)," &
" 21 (BC_1, *, INTERNAL, X)," &
" 20 (BC_1, *, INTERNAL, X)," &
" 19 (BC_1, *, INTERNAL, X)," &
" 18 (BC_1, *, INTERNAL, X)," &
" 17 (BC_1, IO_58, INPUT, X)," &
" 16 (BC_1, IO_58, OUTPUT3, X, 15, 0,Z),"&
" 15 (BC_1, *, CONTROL, 0)," &
" 14 (BC_1, *, INTERNAL, X)," &
" 13 (BC_1, *, INTERNAL, X)," &
" 12 (BC_1, *, INTERNAL, X)," &
" 11 (BC_1, IO_60, INPUT, X)," &
" 10 (BC_1, IO_60, OUTPUT3, X, 9, 0,Z),"&
" 9 (BC_1, *, CONTROL, 0)," &
" 8 (BC_1, IO_61, INPUT, X)," &
" 7 (BC_1, IO_61, OUTPUT3, X, 6, 0,Z),"&
" 6 (BC_1, *, CONTROL, 0)," &
" 5 (BC_1, IO_62, INPUT, X)," &
" 4 (BC_1, IO_62, OUTPUT3, X, 3, 0,Z),"&
" 3 (BC_1, *, CONTROL, 0)," &
" 2 (BC_1, *, INTERNAL, X)," &
" 1 (BC_1, *, INTERNAL, X)," &
" 0 (BC_1, *, INTERNAL, X)" ;
attribute DESIGN_WARNING of xc2c64a_vq44 : entity is
" Devices with IDCODE revision 0000 do not select a register when a null or " &
"nvalid instruction is sent to the device. This problem is corrected in devices with IDCODE revisions 0001 and greater.";
end xc2c64a_vq44;
