----------------------------------------------------------------------------------- -- DATE & TIME : Thu Jul 19 17:19:44 2018 -- File Type : BSDL Description for Top-Level Entity netX90 -- Created by cd ASIC/layout; make bsdl_MPW2 ----------------------------------------------------------------------------------- -- Jul 19, 2018 Lukas Bauer -- Changes: -- * -- -------------------------------------------------------------- -- Rev. 1.0 -- Jul 19, 2018 Lukas Bauer -- Changes: -- * ----------------------------------------------------------------------------------- entity netx90 is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "BGA144"); -- This section declares all the ports in the design. port ( BOD : linkage bit; CLK25OUT : inout bit; COM_IO0 : inout bit; COM_IO1 : inout bit; COM_IO2 : inout bit; COM_IO3 : inout bit; DCDC_GND : linkage bit; DCDC_LX_OUT : linkage bit; HIF_A0 : inout bit; HIF_A1 : inout bit; HIF_A10 : inout bit; HIF_A11 : inout bit; HIF_A12 : inout bit; HIF_A13 : inout bit; HIF_A14 : inout bit; HIF_A15 : inout bit; HIF_A16 : inout bit; HIF_A17 : inout bit; HIF_A2 : inout bit; HIF_A3 : inout bit; HIF_A4 : inout bit; HIF_A5 : inout bit; HIF_A6 : inout bit; HIF_A7 : inout bit; HIF_A8 : inout bit; HIF_A9 : inout bit; HIF_BHEN : inout bit; HIF_CSN : inout bit; HIF_D0 : inout bit; HIF_D1 : inout bit; HIF_D10 : inout bit; HIF_D11 : inout bit; HIF_D12 : inout bit; HIF_D13 : inout bit; HIF_D14 : inout bit; HIF_D15 : inout bit; HIF_D2 : inout bit; HIF_D3 : inout bit; HIF_D4 : inout bit; HIF_D5 : inout bit; HIF_D6 : inout bit; HIF_D7 : inout bit; HIF_D8 : inout bit; HIF_D9 : inout bit; HIF_DIRQ : inout bit; HIF_RDN : inout bit; HIF_RDY : inout bit; HIF_SDCLK : inout bit; HIF_WRN : inout bit; JT_TCK : in bit; JT_TDI : in bit; JT_TDO : out bit; JT_TMS : in bit; JT_TRST : in bit; MII0_COL : inout bit; MII0_CRS : inout bit; MII0_RXCLK : inout bit; MII0_RXD0 : in bit; MII0_RXD1 : inout bit; MII0_RXD2 : inout bit; MII0_RXD3 : in bit; MII0_RXDV : in bit; MII0_RXER : in bit; MII0_TXCLK : inout bit; MII0_TXD0 : inout bit; MII0_TXD1 : inout bit; MII0_TXD2 : inout bit; MII0_TXD3 : inout bit; MII0_TXEN : inout bit; MII1_COL : inout bit; MII1_CRS : inout bit; MII1_RXCLK : inout bit; MII1_RXD0 : in bit; MII1_RXD1 : inout bit; MII1_RXD2 : inout bit; MII1_RXD3 : in bit; MII1_RXDV : in bit; MII1_RXER : inout bit; MII1_TXCLK : inout bit; MII1_TXD0 : inout bit; MII1_TXD1 : inout bit; MII1_TXD2 : inout bit; MII1_TXD3 : inout bit; MII1_TXEN : inout bit; MII_MDC : inout bit; MII_MDIO : inout bit; MLED0 : out bit; MLED1 : out bit; MLED2 : out bit; MLED3 : out bit; MMIO0 : inout bit; MMIO1 : inout bit; MMIO2 : inout bit; MMIO3 : inout bit; MMIO4 : inout bit; MMIO5 : inout bit; MMIO6 : inout bit; MMIO7 : inout bit; PHY0_LED_LINK_IN : inout bit; PHY0_RXN : linkage bit; PHY0_RXP : linkage bit; PHY0_TXN : linkage bit; PHY0_TXP : linkage bit; PHY1_LED_LINK_IN : inout bit; PHY1_RXN : linkage bit; PHY1_RXP : linkage bit; PHY1_TXN : linkage bit; PHY1_TXP : linkage bit; PHY_EXTRES : linkage bit; PHY_VDDA : linkage bit; PHY_VDDHV : linkage bit; RDY_N : inout bit; RST_IN_N : in bit; RST_OUT_N : inout bit; RUN_N : inout bit; SQI_CLK : inout bit; SQI_CS0N : inout bit; SQI_MISO : inout bit; SQI_MOSI : inout bit; SQI_SIO2 : inout bit; SQI_SIO3 : inout bit; TESTMODE : in bit; UART_RXD : in bit; UART_TXD : out bit; VDD_PLL : linkage bit; VREF_ADC : linkage bit; VSS_REF : linkage bit; XTALIN : linkage bit; XTALOUT : linkage bit; -- 8 'BGA2' pins not bonded in product with internal Phy: MII0_COL_BGA2 : linkage bit; MII0_CRS_BGA2 : linkage bit; MII0_TXEN_BGA2 : linkage bit; MII1_COL_BGA2 : linkage bit; MII1_CRS_BGA2 : linkage bit; MII1_RXER_BGA2 : linkage bit; PHY0_LED_LINK_IN_BGA2 : linkage bit; PHY1_LED_LINK_IN_BGA2 : linkage bit; power_pins : linkage bit_vector (1 to 15) ); use STD_1149_1_2001.all; use LVS_BSCAN_CELLS.all; attribute COMPONENT_CONFORMANCE of netx90: entity is "STD_1149_1_2001"; attribute PIN_MAP of netx90: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port constant BGA144: PIN_MAP_STRING := "BOD : J3," & "CLK25OUT : L9," & "COM_IO0 : K7," & "COM_IO1 : K6," & "COM_IO2 : K5," & "COM_IO3 : K4," & "DCDC_GND : K2," & "DCDC_LX_OUT : K1," & "HIF_A0 : C5," & "HIF_A1 : B5," & "HIF_A10 : B2," & "HIF_A11 : C1," & "HIF_A12 : D1," & "HIF_A13 : D2," & "HIF_A14 : D3," & "HIF_A15 : D4," & "HIF_A16 : D5," & "HIF_A17 : D6," & "HIF_A2 : A5," & "HIF_A3 : C4," & "HIF_A4 : B4," & "HIF_A5 : A4," & "HIF_A6 : C3," & "HIF_A7 : B3," & "HIF_A8 : A3," & "HIF_A9 : C2," & "HIF_BHEN : D7," & "HIF_CSN : D8," & "HIF_D0 : B11," & "HIF_D1 : C10," & "HIF_D10 : C7," & "HIF_D11 : B7," & "HIF_D12 : A7," & "HIF_D13 : C6," & "HIF_D14 : B6," & "HIF_D15 : A6," & "HIF_D2 : B10," & "HIF_D3 : A10," & "HIF_D4 : C9," & "HIF_D5 : B9," & "HIF_D6 : A9," & "HIF_D7 : C8," & "HIF_D8 : B8," & "HIF_D9 : A8," & "HIF_DIRQ : F2," & "HIF_RDN : E2," & "HIF_RDY : E3," & "HIF_SDCLK : F1," & "HIF_WRN : E1," & "JT_TCK : D12," & "JT_TDI : C11," & "JT_TDO : C12," & "JT_TMS : D11," & "JT_TRST : D10," & "MII0_COL : E5," & "MII0_CRS : E4," & "MII0_RXCLK : F4," & "MII0_RXD0 : J5," & "MII0_RXD1 : J4," & "MII0_RXD2 : H5," & "MII0_RXD3 : H4," & "MII0_RXDV : G4," & "MII0_RXER : F3," & "MII0_TXCLK : G5," & "MII0_TXD0 : J7," & "MII0_TXD1 : J6," & "MII0_TXD2 : H7," & "MII0_TXD3 : H6," & "MII0_TXEN : F5," & "MII1_COL : E8," & "MII1_CRS : E9," & "MII1_RXCLK : D9," & "MII1_RXD0 : G9," & "MII1_RXD1 : G8," & "MII1_RXD2 : F9," & "MII1_RXD3 : F8," & "MII1_RXDV : F10," & "MII1_RXER : E10," & "MII1_TXCLK : H10," & "MII1_TXD0 : J9," & "MII1_TXD1 : J8," & "MII1_TXD2 : H9," & "MII1_TXD3 : H8," & "MII1_TXEN : K9," & "MII_MDC : K8," & "MII_MDIO : L8," & "MLED0 : L10," & "MLED1 : K10," & "MLED2 : J10," & "MLED3 : K11," & "MMIO0 : M7," & "MMIO1 : L7," & "MMIO2 : M6," & "MMIO3 : L6," & "MMIO4 : M5," & "MMIO5 : L5," & "MMIO6 : M4," & "MMIO7 : L4," & "PHY0_LED_LINK_IN : E7," & "PHY0_RXN : H11," & "PHY0_RXP : H12," & "PHY0_TXN : J11," & "PHY0_TXP : J12," & "PHY1_LED_LINK_IN : E6," & "PHY1_RXN : F11," & "PHY1_RXP : F12," & "PHY1_TXN : E11," & "PHY1_TXP : E12," & "PHY_EXTRES : G12," & "PHY_VDDA : K12," & "PHY_VDDHV : L11," & "RDY_N : J1," & "RST_IN_N : M3," & "RST_OUT_N : L3," & "RUN_N : J2," & "SQI_CLK : H2," & "SQI_CS0N : G1," & "SQI_MISO : G2," & "SQI_MOSI : H1," & "SQI_SIO2 : G3," & "SQI_SIO3 : H3," & "TESTMODE : K3," & "UART_RXD : G10," & "UART_TXD : G11," & "VDD_PLL : M8," & "VREF_ADC : L2," & "VSS_REF : M1," & "XTALIN : M9," & "XTALOUT : M10," & "power_pins :( A2, L1, A11, L12," & -- VDDIO (3.3V) "M11, M2, B12, B1," & -- VDD_CORE (1.2V) "G7, F7, G6, F6, M12, A1, A12)"; -- VSS -- This section specifies the TAP ports. For the TAP TCK port, the parameters in -- the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of JT_TCK : signal is (2.000000e+07, BOTH); attribute TAP_SCAN_IN of JT_TDI : signal is true; attribute TAP_SCAN_MODE of JT_TMS : signal is true; attribute TAP_SCAN_OUT of JT_TDO : signal is true; attribute TAP_SCAN_RESET of JT_TRST : signal is true; -- Specifies the compliance enable patterns for the design. It lists a set of -- design ports and the values that they should be set to, in order to enable -- compliance to IEEE Std 1149.1 attribute COMPLIANCE_PATTERNS of netx90: entity is "(TESTMODE) " & " (0) " ; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of netx90: entity is 4; -- Specifies the boundary-scan instructions implemented in the design and their -- opcodes. attribute INSTRUCTION_OPCODE of netx90: entity is "BYPASS (1111)," & "EXTEST (0000)," & "IDCODE (0001)," & "SAMPLE (0100)," & "PRELOAD (0100)," & "INTEST (0110)," & "HIGHZ (1000)"; -- Specifies the bit pattern that is loaded into the instruction register when -- the TAP controller passes through the Capture-IR state. The standard mandates -- that the two LSBs must be "01". The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of netx90: entity is "0001"; -- Specifies the bit pattern that is loaded into the DEVICE_ID register during -- the IDCODE instruction when the TAP controller passes through the Capture-DR -- state. attribute IDCODE_REGISTER of netx90: entity is "0001" & -- 4-bit version number "0000101000000100" & -- 16-bit part number "01101010110" & -- 11-bit identity of the manufacturer "1"; -- Required by IEEE Std 1149.1 -- This section specifies the test data register placed between TDI and TDO for -- each implemented instruction. attribute REGISTER_ACCESS of netx90: entity is "BYPASS (BYPASS, HIGHZ)," & "BOUNDARY (INTEST, EXTEST, SAMPLE, PRELOAD)," & "DEVICE_ID (IDCODE)"; -- The following list specifies the characteristics of each cell in the boundary -- scan register from TDI to TDO. The following is a description of the label -- fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not have a port -- name. -- function: Is the function of the cell as defined by the standard. Is one -- of input, output2, output3, bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be loaded with -- for safe operation when the software might otherwise choose a -- random value. -- ccell : The control cell number. Specifies the control cell that -- drives the output enable for this port. -- disval : Specifies the value that is loaded into the control cell to -- disable the output enable for the corresponding port. -- rslt : Resulting state. Shows the state of the driver when it is -- disabled. attribute BOUNDARY_LENGTH of netx90 : entity is 210; attribute BOUNDARY_REGISTER of netx90 : entity is --- num cell port function safe [ccell disval rslt] "0 ( bc_7, HIF_A15, bidir, X, 1, 0, Z)," & "1 ( bc_2, *, control, 0)," & "2 ( bc_7, HIF_A7, bidir, X, 3, 0, Z)," & "3 ( bc_2, *, control, 0)," & "4 ( bc_7, HIF_A6, bidir, X, 5, 0, Z)," & "5 ( bc_2, *, control, 0)," & "6 ( bc_7, HIF_A8, bidir, X, 7, 0, Z)," & "7 ( bc_2, *, control, 0)," & "8 ( bc_7, HIF_A3, bidir, X, 9, 0, Z)," & "9 ( bc_2, *, control, 0)," & "10 ( bc_7, HIF_A4, bidir, X, 11, 0, Z)," & "11 ( bc_2, *, control, 0)," & "12 ( bc_7, HIF_A16, bidir, X, 13, 0, Z)," & "13 ( bc_2, *, control, 0)," & "14 ( bc_7, HIF_A5, bidir, X, 15, 0, Z)," & "15 ( bc_2, *, control, 0)," & "16 ( bc_7, HIF_A0, bidir, X, 17, 0, Z)," & "17 ( bc_2, *, control, 0)," & "18 ( bc_7, HIF_A1, bidir, X, 19, 0, Z)," & "19 ( bc_2, *, control, 0)," & "20 ( bc_7, HIF_A2, bidir, X, 21, 0, Z)," & "21 ( bc_2, *, control, 0)," & "22 ( bc_7, PHY1_LED_LINK_IN, bidir, X, 23, 0, Z)," & "23 ( bc_2, *, control, 0)," & "24 ( bc_7, HIF_A17, bidir, X, 25, 0, Z)," & "25 ( bc_2, *, control, 0)," & "26 ( bc_7, HIF_D14, bidir, X, 27, 0, Z)," & "27 ( bc_2, *, control, 0)," & "28 ( bc_7, HIF_D15, bidir, X, 29, 0, Z)," & "29 ( bc_2, *, control, 0)," & "30 ( bc_1, MII0_CRS_BGA2, input, X)," & "31 ( bc_1, PHY1_LED_LINK_IN_BGA2, input, X)," & "32 ( bc_1, PHY0_LED_LINK_IN_BGA2, input, X)," & "33 ( bc_7, MII0_COL_BGA2, bidir, X, 34, 0, Z)," & "34 ( bc_2, *, control, 0)," & "35 ( bc_7, HIF_D12, bidir, X, 36, 0, Z)," & "36 ( bc_2, *, control, 0)," & "37 ( bc_7, HIF_D11, bidir, X, 38, 0, Z)," & "38 ( bc_2, *, control, 0)," & "39 ( bc_7, HIF_D13, bidir, X, 40, 0, Z)," & "40 ( bc_2, *, control, 0)," & "41 ( bc_7, HIF_D10, bidir, X, 42, 0, Z)," & "42 ( bc_2, *, control, 0)," & "43 ( bc_7, HIF_BHEN, bidir, X, 44, 0, Z)," & "44 ( bc_2, *, control, 0)," & "45 ( bc_7, HIF_D9, bidir, X, 46, 0, Z)," & "46 ( bc_2, *, control, 0)," & "47 ( bc_7, HIF_D8, bidir, X, 48, 0, Z)," & "48 ( bc_2, *, control, 0)," & "49 ( bc_7, PHY0_LED_LINK_IN, bidir, X, 50, 0, Z)," & "50 ( bc_2, *, control, 0)," & "51 ( bc_7, HIF_D6, bidir, X, 52, 0, Z)," & "52 ( bc_2, *, control, 0)," & "53 ( bc_7, HIF_D7, bidir, X, 54, 0, Z)," & "54 ( bc_2, *, control, 0)," & "55 ( bc_7, HIF_D5, bidir, X, 56, 0, Z)," & "56 ( bc_2, *, control, 0)," & "57 ( bc_7, HIF_D3, bidir, X, 58, 0, Z)," & "58 ( bc_2, *, control, 0)," & "59 ( bc_7, HIF_CSN, bidir, X, 60, 0, Z)," & "60 ( bc_2, *, control, 0)," & "61 ( bc_7, HIF_D2, bidir, X, 62, 0, Z)," & "62 ( bc_2, *, control, 0)," & "63 ( bc_7, HIF_D4, bidir, X, 64, 0, Z)," & "64 ( bc_2, *, control, 0)," & "65 ( bc_7, HIF_D0, bidir, X, 66, 0, Z)," & "66 ( bc_2, *, control, 0)," & "67 ( bc_7, HIF_D1, bidir, X, 68, 0, Z)," & "68 ( bc_2, *, control, 0)," & "69 ( bc_7, MII1_CRS, bidir, X, 70, 0, Z)," & "70 ( bc_2, *, control, 0)," & "71 ( bc_7, MII1_RXER, bidir, X, 72, 0, Z)," & "72 ( bc_2, *, control, 0)," & "73 ( bc_7, MII0_TXEN_BGA2, bidir, X, 74, 0, Z)," & "74 ( bc_2, *, control, 0)," & "75 ( bc_7, MII1_COL_BGA2, bidir, X, 76, 0, Z)," & "76 ( bc_2, *, control, 0)," & "77 ( bc_1, MII1_RXER_BGA2, input, X)," & "78 ( bc_1, MII1_CRS_BGA2, input, X)," & "79 ( bc_7, MII1_COL, bidir, X, 80, 0, Z)," & "80 ( bc_2, *, control, 0)," & "81 ( bc_7, MII1_RXCLK, bidir, X, 82, 0, Z)," & "82 ( bc_2, *, control, 0)," & "83 ( bc_1, MII1_RXDV, input, X)," & "84 ( bc_1, MII1_RXD3, input, X)," & "85 ( bc_7, MII1_RXD2, bidir, X, 86, 0, Z)," & "86 ( bc_2, *, control, 0)," & "87 ( bc_7, MII1_TXD0, bidir, X, 88, 0, Z)," & "88 ( bc_2, *, control, 0)," & "89 ( bc_7, MII1_TXD1, bidir, X, 90, 0, Z)," & "90 ( bc_2, *, control, 0)," & "91 ( bc_1, UART_TXD, output3, X, 92, 0, Z)," & "92 ( bc_2, *, control, 0)," & "93 ( bc_1, UART_RXD, input, X)," & "94 ( bc_1, MLED3, output3, X, 95, 0, Z)," & "95 ( bc_2, *, control, 0)," & "96 ( bc_7, MII1_TXCLK, bidir, X, 97, 0, Z)," & "97 ( bc_2, *, control, 0)," & "98 ( bc_1, MLED2, output3, X, 99, 0, Z)," & "99 ( bc_2, *, control, 0)," & "100 ( bc_1, MLED1, output3, X, 101, 0, Z)," & "101 ( bc_2, *, control, 0)," & "102 ( bc_1, MLED0, output3, X, 103, 0, Z)," & "103 ( bc_2, *, control, 0)," & "104 ( bc_7, MII1_TXEN, bidir, X, 105, 0, Z)," & "105 ( bc_2, *, control, 0)," & "106 ( bc_7, MII0_TXD2, bidir, X, 107, 0, Z)," & "107 ( bc_2, *, control, 0)," & "108 ( bc_7, CLK25OUT, bidir, X, 109, 0, Z)," & "109 ( bc_2, *, control, 0)," & "110 ( bc_7, MII_MDC, bidir, X, 111, 0, Z)," & "111 ( bc_2, *, control, 0)," & "112 ( bc_7, MII_MDIO, bidir, X, 113, 0, Z)," & "113 ( bc_2, *, control, 0)," & "114 ( bc_7, MII0_TXD0, bidir, X, 115, 0, Z)," & "115 ( bc_2, *, control, 0)," & "116 ( bc_7, MII1_TXD2, bidir, X, 117, 0, Z)," & "117 ( bc_2, *, control, 0)," & "118 ( bc_7, MII1_TXD3, bidir, X, 119, 0, Z)," & "119 ( bc_2, *, control, 0)," & "120 ( bc_7, MMIO0, bidir, X, 121, 0, Z)," & "121 ( bc_2, *, control, 0)," & "122 ( bc_1, MII1_RXD0, input, X)," & "123 ( bc_7, MII1_RXD1, bidir, X, 124, 0, Z)," & "124 ( bc_2, *, control, 0)," & "125 ( bc_7, COM_IO0, bidir, X, 126, 0, Z)," & "126 ( bc_2, *, control, 0)," & "127 ( bc_7, MMIO1, bidir, X, 128, 0, Z)," & "128 ( bc_2, *, control, 0)," & "129 ( bc_7, MMIO2, bidir, X, 130, 0, Z)," & "130 ( bc_2, *, control, 0)," & "131 ( bc_7, COM_IO1, bidir, X, 132, 0, Z)," & "132 ( bc_2, *, control, 0)," & "133 ( bc_7, MMIO3, bidir, X, 134, 0, Z)," & "134 ( bc_2, *, control, 0)," & "135 ( bc_7, MII0_TXD1, bidir, X, 136, 0, Z)," & "136 ( bc_2, *, control, 0)," & "137 ( bc_7, MII0_TXD3, bidir, X, 138, 0, Z)," & "138 ( bc_2, *, control, 0)," & "139 ( bc_7, RST_OUT_N, bidir, X, 140, 0, Z)," & "140 ( bc_2, *, control, 0)," & "141 ( bc_7, COM_IO2, bidir, X, 142, 0, Z)," & "142 ( bc_2, *, control, 0)," & "143 ( bc_7, COM_IO3, bidir, X, 144, 0, Z)," & "144 ( bc_2, *, control, 0)," & "145 ( bc_1, MII0_RXD0, input, X)," & "146 ( bc_1, RST_IN_N, input, X)," & "147 ( bc_7, MMIO4, bidir, X, 148, 0, Z)," & "148 ( bc_2, *, control, 0)," & "149 ( bc_7, MMIO5, bidir, X, 150, 0, Z)," & "150 ( bc_2, *, control, 0)," & "151 ( bc_7, MMIO6, bidir, X, 152, 0, Z)," & "152 ( bc_2, *, control, 0)," & "153 ( bc_7, MMIO7, bidir, X, 154, 0, Z)," & "154 ( bc_2, *, control, 0)," & "155 ( bc_7, MII0_RXD2, bidir, X, 156, 0, Z)," & "156 ( bc_2, *, control, 0)," & "157 ( bc_7, MII0_RXD1, bidir, X, 158, 0, Z)," & "158 ( bc_2, *, control, 0)," & "159 ( bc_1, MII0_RXD3, input, X)," & "160 ( bc_7, RUN_N, bidir, X, 161, 0, Z)," & "161 ( bc_2, *, control, 0)," & "162 ( bc_7, RDY_N, bidir, X, 163, 0, Z)," & "163 ( bc_2, *, control, 0)," & "164 ( bc_7, SQI_SIO3, bidir, X, 165, 0, Z)," & "165 ( bc_2, *, control, 0)," & "166 ( bc_7, MII0_TXCLK, bidir, X, 167, 0, Z)," & "167 ( bc_2, *, control, 0)," & "168 ( bc_7, SQI_CLK, bidir, X, 169, 0, Z)," & "169 ( bc_2, *, control, 0)," & "170 ( bc_7, SQI_MOSI, bidir, X, 171, 0, Z)," & "171 ( bc_2, *, control, 0)," & "172 ( bc_1, MII0_RXDV, input, X)," & "173 ( bc_7, SQI_SIO2, bidir, X, 174, 0, Z)," & "174 ( bc_2, *, control, 0)," & "175 ( bc_7, SQI_MISO, bidir, X, 176, 0, Z)," & "176 ( bc_2, *, control, 0)," & "177 ( bc_7, SQI_CS0N, bidir, X, 178, 0, Z)," & "178 ( bc_2, *, control, 0)," & "179 ( bc_7, HIF_SDCLK, bidir, X, 180, 0, Z)," & "180 ( bc_2, *, control, 0)," & "181 ( bc_7, HIF_DIRQ, bidir, X, 182, 0, Z)," & "182 ( bc_2, *, control, 0)," & "183 ( bc_1, MII0_RXER, input, X)," & "184 ( bc_7, MII0_RXCLK, bidir, X, 185, 0, Z)," & "185 ( bc_2, *, control, 0)," & "186 ( bc_7, HIF_WRN, bidir, X, 187, 0, Z)," & "187 ( bc_2, *, control, 0)," & "188 ( bc_7, MII0_TXEN, bidir, X, 189, 0, Z)," & "189 ( bc_2, *, control, 0)," & "190 ( bc_7, HIF_RDN, bidir, X, 191, 0, Z)," & "191 ( bc_2, *, control, 0)," & "192 ( bc_7, MII0_COL, bidir, X, 193, 0, Z)," & "193 ( bc_2, *, control, 0)," & "194 ( bc_7, HIF_A12, bidir, X, 195, 0, Z)," & "195 ( bc_2, *, control, 0)," & "196 ( bc_7, HIF_A13, bidir, X, 197, 0, Z)," & "197 ( bc_2, *, control, 0)," & "198 ( bc_7, HIF_RDY, bidir, X, 199, 0, Z)," & "199 ( bc_2, *, control, 0)," & "200 ( bc_7, HIF_A11, bidir, X, 201, 0, Z)," & "201 ( bc_2, *, control, 0)," & "202 ( bc_7, MII0_CRS, bidir, X, 203, 0, Z)," & "203 ( bc_2, *, control, 0)," & "204 ( bc_7, HIF_A9, bidir, X, 205, 0, Z)," & "205 ( bc_2, *, control, 0)," & "206 ( bc_7, HIF_A14, bidir, X, 207, 0, Z)," & "207 ( bc_2, *, control, 0)," & "208 ( bc_7, HIF_A10, bidir, X, 209, 0, Z)," & "209 ( bc_2, *, control, 0)"; end netx90;