-- **********************************************************************
--
-- FILE : zl30116ggg.bsd
-- generated by Cz. Piasta as zl30116 on Wed Nov 16 11:05:31 EST 2005
-- using p.jtag.bsd rev 3.3 July 18, 2003
--
-- BSDL description for top level entity zl30116
-- Device : ZL30116 Sonet SDH Low Jitter Network Sync
-- Package : 100-pin CABGA
--
-- Number of BSC cells: 85
--
-- **********************************************************************
-- Modification History:
-- Initial release: Wed Nov 16 11:05:31 EST 2005
-- ********************************************************************
--
-- IMPORTANT NOTICE
--
-- This information is for modeling purposes only, and is not guaranteed.
--
-- This information is provided "as is" without warranty of any kind.
-- It may contain technical inaccuracies or typographical errors.
--
-- ZARLINK and ZL30116 are trademarks of ZARLINK Semiconductor. ZARLINK
-- products, marketed under trademarks, are protected under numerous US
-- and foreign patents and pending applications, maskwork rights, and
-- copyrights.
--
-- ZARLINK reserves the right to make changes to any products and
-- services at any time without notice. ZARLINK assumes no
-- responsibility or liability arising out of the application or use of
-- any information, product, or service described herein except as
-- expressly agreed to in writing by ZARLINK Corporation. ZARLINK
-- customers are advised to obtain the latest version of device
-- specifications before relying on any published information and before
-- placing orders for products or services.
--
-- ********************************************************************
--
-- SPECIAL NOTES
--
-- 1. All instruction opcodes other than those defined in this file
-- should be considered PRIVATE.
--
-- 2. Balls {J2, J6, G3} (IC_GND1, IC_GND2, IC_GND3) are internal
-- connects, and they should be tied low for normal operation.
--
-- 3. Ball K6 (IC_OPEN) is an internal connect, which should be left
-- open for normal operation.
--
-- ********************************************************************
entity zl30116 is
generic(PHYSICAL_PIN_MAP : string := "BGA_PACKAGE");
port (
CS_B: in bit;
DIFF0_EN: in bit;
DIFF0_N: linkage bit;
DIFF0_P: linkage bit;
DIFF1_EN: in bit;
DIFF1_N: linkage bit;
DIFF1_P: linkage bit;
DPLL1_HOLDOVER: out bit;
DPLL1_HS_EN: in bit;
DPLL1_LOCK: out bit;
DPLL1_MOD_SEL: in bit_vector (0 to 2);
DPLL2_REF: out bit;
EXT_FB_CLK: in bit;
EXT_FB_FP: in bit;
FB_CLK: out bit;
FILTER_REF0: linkage bit;
FILTER_REF1: linkage bit;
IC_GND: linkage bit_vector (1 to 3);
IC_OPEN: linkage bit;
INT_B: out bit;
NC1: linkage bit;
NC2: linkage bit;
OSC_I: linkage bit;
OSC_O: linkage bit;
P0_CLK0: out bit;
P0_CLK1: out bit;
P0_FP0: out bit;
P0_FP1: out bit;
P1_CLK0: out bit;
P1_CLK1: out bit;
REF: in bit_vector (0 to 7);
RST_B: in bit;
SCK: inout bit;
SDH_CLK0: out bit;
SDH_CLK1: out bit;
SDH_FILTER: linkage bit;
SDH_FP0: out bit;
SDH_FP1: out bit;
SI: inout bit;
SLAVE_EN: in bit;
SO: out bit;
SYNC: in bit_vector (0 to 2);
TCK: in bit;
TDI: in bit;
TDO: out bit;
TMS: in bit;
TRST_B: in bit;
AVDD: linkage bit_vector (1 to 3);
AVDDCORE: linkage bit_vector (1 to 3);
AVSS: linkage bit_vector (1 to 6);
VDD: linkage bit_vector (1 to 8);
VDDCORE: linkage bit_vector (1 to 2);
VSS: linkage bit_vector (1 to 18)
);
use STD_1149_1_2001.all;
attribute COMPONENT_CONFORMANCE of zl30116 : entity is
"STD_1149_1_2001";
attribute PIN_MAP of zl30116 : entity is PHYSICAL_PIN_MAP;
constant BGA_PACKAGE : PIN_MAP_STRING :=
"CS_B : E3 , " &
"DIFF0_EN : K1 , " &
"DIFF0_N : B10 , " &
"DIFF0_P : A9 , " &
"DIFF1_EN : D3 , " &
"DIFF1_N : B9 , " &
"DIFF1_P : A10 , " &
"DPLL1_HOLDOVER : J1 , " &
"DPLL1_HS_EN : J5 , " &
"DPLL1_LOCK : H1 , " &
"DPLL1_MOD_SEL :(C2 , " & -- DPLL1_MOD_SEL[0]
"D2 , " & -- DPLL1_MOD_SEL[1]
"H7 ), " & -- DPLL1_MOD_SEL[2]
"DPLL2_REF : E1 , " &
"EXT_FB_CLK : C5 , " &
"EXT_FB_FP : B5 , " &
"FB_CLK : H10 , " &
"FILTER_REF0 : B6 , " &
"FILTER_REF1 : C6 , " &
"IC_GND :(J2 , " & -- IC_GND[1]
"J6 , " & -- IC_GND[2]
"G3 ), " & -- IC_GND[3]
"IC_OPEN : K6 , " &
"INT_B : G2 , " &
"NC1 : F2 , " &
"NC2 : F3 , " &
"OSC_I : K4 , " &
"OSC_O : K5 , " &
"P0_CLK0 : K9 , " &
"P0_CLK1 : K7 , " &
"P0_FP0 : K8 , " &
"P0_FP1 : J7 , " &
"P1_CLK0 : J10 , " &
"P1_CLK1 : K10 , " &
"REF :(C1 , " & -- REF[0]
"B2 , " & -- REF[1]
"A3 , " & -- REF[2]
"C3 , " & -- REF[3]
"B3 , " & -- REF[4]
"B4 , " & -- REF[5]
"C4 , " & -- REF[6]
"A4 ), " & -- REF[7]
"RST_B : H5 , " &
"SCK : E2 , " &
"SDH_CLK0 : D10 , " &
"SDH_CLK1 : G10 , " &
"SDH_FILTER : A6 , " &
"SDH_FP0 : E10 , " &
"SDH_FP1 : F10 , " &
"SI : F1 , " &
"SLAVE_EN : D1 , " &
"SO : G1 , " &
"SYNC :(B1 , " & -- SYNC[0]
"A1 , " & -- SYNC[1]
"A2 ), " & -- SYNC[2]
"TCK : K3 , " &
"TDI : K2 , " &
"TDO : J4 , " &
"TMS : J3 , " &
"TRST_B : H4 , " &
"AVDD :(A5, A8, C10)," &
"AVDDCORE :(B8, B7, H2)," &
"AVSS :(A7, C7, C8, C9, D8, H3)," &
"VDD :(D9, E4, G8, G9, J8, J9, H6, H8)," &
"VDDCORE :(E8, F4)," &
"VSS :(D4, D5, D6, D7, E5, E6, E7, F5, F6, F7, G4, G5," &
"G6, G7, E9, F8, F9, H9)";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6,BOTH);
attribute TAP_SCAN_RESET of TRST_B : signal is true;
--
-- NOTE: All instruction opcodes other than those defined in this file
-- should be considered PRIVATE.
--
attribute INSTRUCTION_LENGTH of zl30116 : entity is 16;
attribute INSTRUCTION_OPCODE of zl30116 : entity is
"bypass (0000000000000000)," &
"bypass (1111111111111111)," &
"clamp (1111111111101111)," &
"extest (1111111111101000)," &
"highz (1111111111001111)," &
"idcode (1111111111111110)," &
"preload (1111111111111000)," &
"sample (1111111111111000)";
attribute INSTRUCTION_CAPTURE of zl30116 : entity is "xxxxxxxxxxxxxx01";
attribute IDCODE_REGISTER of zl30116 : entity is
"0001" & -- version
"0111010110100100" & -- part number
"00010100101" & -- manufacturer id
"1";
attribute REGISTER_ACCESS of zl30116 : entity is
"boundary (extest, sample, preload)," &
"bypass (bypass, clamp, highz)," &
"device_id (idcode)" ;
attribute BOUNDARY_LENGTH of zl30116 : entity is 85;
attribute BOUNDARY_REGISTER of zl30116 : entity is
-- num cell port function safe ccel disval rslt
" 0 ( BC_0, *, internal, X) ," &
" 1 ( BC_0, *, internal, X) ," &
" 2 ( BC_4, DPLL1_HS_EN, input, X) ," &
" 3 ( BC_4, RST_B, input, X) ," &
" 4 ( BC_0, *, internal, X) ," &
" 5 ( BC_4, DPLL1_MOD_SEL(2), input, X) ," &
" 6 ( BC_0, *, internal, X) ," &
" 7 ( BC_0, *, internal, X) ," &
" 8 ( BC_0, *, internal, X) ," &
" 9 ( BC_2, P0_CLK1, output3, X, 10, 1, Z) ," &
" 10 ( BC_2, *, control, 1) ," &
" 11 ( BC_2, P0_FP1, output3, X, 12, 1, Z) ," &
" 12 ( BC_2, *, control, 1) ," &
" 13 ( BC_2, P0_FP0, output3, X, 14, 1, Z) ," &
" 14 ( BC_2, *, control, 1) ," &
" 15 ( BC_2, P0_CLK0, output3, X, 16, 1, Z) ," &
" 16 ( BC_2, *, control, 1) ," &
" 17 ( BC_2, P1_CLK1, output3, X, 18, 1, Z) ," &
" 18 ( BC_2, *, control, 1) ," &
" 19 ( BC_2, P1_CLK0, output3, X, 20, 1, Z) ," &
" 20 ( BC_2, *, control, 1) ," &
" 21 ( BC_2, FB_CLK, output3, X, 22, 1, Z) ," &
" 22 ( BC_2, *, control, 1) ," &
" 23 ( BC_2, SDH_CLK1, output3, X, 24, 1, Z) ," &
" 24 ( BC_2, *, control, 1) ," &
" 25 ( BC_2, SDH_FP1, output3, X, 26, 1, Z) ," &
" 26 ( BC_2, *, control, 1) ," &
" 27 ( BC_2, SDH_FP0, output3, X, 28, 1, Z) ," &
" 28 ( BC_2, *, control, 1) ," &
" 29 ( BC_2, SDH_CLK0, output3, X, 30, 1, Z) ," &
" 30 ( BC_2, *, control, 1) ," &
" 31 ( BC_0, *, internal, X) ," &
" 32 ( BC_0, *, internal, X) ," &
" 33 ( BC_0, *, internal, X) ," &
" 34 ( BC_0, *, internal, X) ," &
" 35 ( BC_0, *, internal, X) ," &
" 36 ( BC_4, EXT_FB_CLK, input, X) ," &
" 37 ( BC_4, EXT_FB_FP, input, X) ," &
" 38 ( BC_4, REF(7), input, X) ," &
" 39 ( BC_4, REF(6), input, X) ," &
" 40 ( BC_4, REF(5), input, X) ," &
" 41 ( BC_4, REF(4), input, X) ," &
" 42 ( BC_4, REF(3), input, X) ," &
" 43 ( BC_4, REF(2), input, X) ," &
" 44 ( BC_4, SYNC(2), input, X) ," &
" 45 ( BC_4, REF(1), input, X) ," &
" 46 ( BC_4, SYNC(1), input, X) ," &
" 47 ( BC_4, SYNC(0), input, X) ," &
" 48 ( BC_4, REF(0), input, X) ," &
" 49 ( BC_0, *, internal, X) ," &
" 50 ( BC_0, *, internal, X) ," &
" 51 ( BC_0, *, internal, 1) ," &
" 52 ( BC_0, *, internal, X) ," &
" 53 ( BC_0, *, internal, X) ," &
" 54 ( BC_0, *, internal, X) ," &
" 55 ( BC_4, DPLL1_MOD_SEL(0), input, X) ," &
" 56 ( BC_4, DPLL1_MOD_SEL(1), input, X) ," &
" 57 ( BC_4, DIFF1_EN, input, X) ," &
" 58 ( BC_0, *, internal, X) ," &
" 59 ( BC_4, SLAVE_EN, input, X) ," &
" 60 ( BC_2, DPLL2_REF, output3, X, 77, 1, Z) ," &
" 61 ( BC_0, *, internal, X) ," &
" 62 ( BC_7, SCK, bidir, X, 63, 1, Z) ," &
" 63 ( BC_2, *, control, 1) ," &
" 64 ( BC_4, CS_B, input, X) ," &
" 65 ( BC_0, *, internal, X) ," &
" 66 ( BC_0, *, internal, X) ," &
" 67 ( BC_7, SI, bidir, X, 68, 1, Z) ," &
" 68 ( BC_2, *, control, 1) ," &
" 69 ( BC_2, SO, output3, X, 70, 1, Z) ," &
" 70 ( BC_2, *, control, 1) ," &
" 71 ( BC_2, INT_B, output3, X, 72, 1, Z) ," &
" 72 ( BC_2, *, control, 1) ," &
" 73 ( BC_0, *, internal, X) ," &
" 74 ( BC_2, DPLL1_LOCK, output3, X, 77, 1, Z) ," &
" 75 ( BC_0, *, internal, X) ," &
" 76 ( BC_2, DPLL1_HOLDOVER, output3, X, 77, 1, Z) ," &
" 77 ( BC_2, *, control, 1) ," &
" 78 ( BC_0, *, internal, X) ," &
" 79 ( BC_0, *, internal, X) ," &
" 80 ( BC_0, *, internal, X) ," &
" 81 ( BC_4, DIFF0_EN, input, X) ," &
" 82 ( BC_0, *, internal, X) ," &
" 83 ( BC_0, *, internal, X) ," &
" 84 ( BC_0, *, internal, X) ";
end zl30116;
------------- end of BSDL description for the zl30116 ----------