-- ********************************************************************
-- * ispCLOCK5406D BSDL Model *
-- * File Version: 1.00 *
-- * File Date: 01/23/2009 *
-- * *
-- * This is a preliminary BSDL file. *
-- * It has not been verified on silicon. *
-- * *
-- * Standard Test Access Port and Boundary-Scan Architecture *
-- * VHDL Description File *
-- * *
-- * This BSDL file is created according to: *
-- * - IEEE 1149.1 2001 spec. *
-- * *
-- * This BSDL has been validated for syntax and semantics *
-- * compliance to IEEE 1149.1 using: *
-- * - Lattice BSDL Syntax Checker *
-- * - JTAG Technologies JTAG BSDL Verifier V2.4 *
-- * - Goepel BSDL Syntax Checker V3.1.2 *
-- * - ASSET/Agilent BSDL Validation Service *
-- * *
-- * Copyright 2000 - 2009 *
-- * Lattice Semiconductor Corporation *
-- * 5555 NE Moore Ct. *
-- * Hillsboro, OR 97124 *
-- * *
-- * All rights reserved. No part of this program or publication *
-- * may be reproduced, transmitted, transcribed, stored in a *
-- * retrieval system, or translated into any language or *
-- * computer language, in any form or by any means without this *
-- * notice appearing within. *
-- ********************************************************************
-- * *
-- * IMPORTANT *
-- * *
-- * The following is a BSDL file that tests all of the I/O pins *
-- * as bidirectional pins. The functionality of the BSCAN register *
-- * for this device is independent of the pattern programmed *
-- * into the device. An additional programming step is not *
-- * required to configure the I/O pins prior to BSCAN test. *
-- * *
-- * For Further assistance, please contact Tech Support at *
-- * 1-800-LATTICE or techsupport@latticesemi.com *
-- ********************************************************************
-- * *
-- * REVISION HISTORY *
-- * *
-- * Rev 1.00: 01/23/2009 *
-- * - rcs: Preliminary version. *
-- * *
-- ********************************************************************
-- The Overall Structure of the Entity Description
entity ispPAC_CLK5406D_XXSN48 is
-- Generic Parameter Statement
generic (PHYSICAL_PIN_MAP : string := "QFNS_48");
-- Logical Port Description Statement
port (
VCCO_0: linkage bit;
VCCO_1: linkage bit;
VCCO_2: linkage bit;
VCCO_3: linkage bit;
VCCO_4: linkage bit;
VCCO_5: linkage bit;
GND: linkage bit_vector(0 to 5);
BANK_0P: out bit;
BANK_0N: out bit;
BANK_1P: out bit;
BANK_1N: out bit;
BANK_2P: out bit;
BANK_2N: out bit;
BANK_3P: out bit;
BANK_3N: out bit;
BANK_4P: out bit;
BANK_4N: out bit;
BANK_5P: out bit;
BANK_5N: out bit;
VCCA: linkage bit;
GNDA: linkage bit;
VCCD: linkage bit;
GNDD: linkage bit;
RREF: linkage bit;
REFAP: in bit;
REFAN: in bit;
REFBP: in bit;
REFBN: in bit;
FBKP: in bit;
FBKN: in bit;
REFA_VTT: linkage bit;
REFB_VTT: linkage bit;
FBK_VTT: linkage bit;
RESET: in bit;
USER0: inout bit;
USER1: inout bit;
USER2: in bit;
USER3: in bit;
VCCJ: linkage bit;
TDO: out bit;
TMS: in bit;
TCK: in bit;
TDI: in bit;
NC: linkage bit_vector(0 to 1)
);
-- Version Control
use STD_1149_1_2001.all; -- 1149.1-2001 attributes
-- Component Conformance Statement
attribute COMPONENT_CONFORMANCE of ispPAC_CLK5406D_XXSN48 : entity is
"STD_1149_1_2001";
-- Device Package Pin Mapping
attribute PIN_MAP of ispPAC_CLK5406D_XXSN48 : entity is PHYSICAL_PIN_MAP;
constant QFNS_48 : PIN_MAP_STRING :=
"GND: (1, 8, 9, 28, 29, 36),"&
"BANK_5P: 2,"&
"BANK_5N: 3,"&
"VCCO_5: 4,"&
"VCCO_4: 5,"&
"BANK_4P: 6,"&
"BANK_4N: 7,"&
"BANK_3P: 10,"&
"BANK_3N: 11,"&
"VCCO_3: 12,"&
"GNDA: 13,"&
"REFA_VTT: 14,"&
"REFAN: 15,"&
"REFAP: 16,"&
"REFB_VTT: 17,"&
"REFBN: 18,"&
"REFBP: 19,"&
"FBK_VTT: 20,"&
"FBKN: 21,"&
"FBKP: 22,"&
"VCCA: 23,"&
"RREF: 24,"&
"VCCO_2: 25,"&
"BANK_2N: 26,"&
"BANK_2P: 27,"&
"BANK_1N: 30,"&
"BANK_1P: 31,"&
"VCCO_1: 32,"&
"VCCO_0: 33,"&
"BANK_0N: 34,"&
"BANK_0P: 35,"&
"VCCJ: 37,"&
"TDO: 38,"&
"TMS: 39,"&
"TCK: 40,"&
"TDI: 41,"&
"RESET: 42,"&
"GNDD: 43,"&
"VCCD: 44,"&
"USER3: 45,"&
"USER2: 46,"&
"USER1: 47,"&
"USER0: 48";
-- Differential Cell Identification
attribute PORT_GROUPING of ispPAC_CLK5406D_XXSN48 : entity is
"DIFFERENTIAL_VOLTAGE ( " &
"(REFAP, REFAN)," &
"(REFBP, REFBN)," &
"(FBKP, FBKN)," &
"(BANK_0P, BANK_0N)," &
"(BANK_1P, BANK_1N)," &
"(BANK_2P, BANK_2N)," &
"(BANK_3P, BANK_3N)," &
"(BANK_4P, BANK_4N)," &
"(BANK_5P, BANK_5N))";
-- Scan Port Identification
attribute TAP_SCAN_CLOCK of TCK : Signal is (25.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : Signal is True;
attribute TAP_SCAN_OUT of TDO : Signal is True;
attribute TAP_SCAN_MODE of TMS : Signal is True;
-- Instruction Register Description
attribute INSTRUCTION_LENGTH of ispPAC_CLK5406D_XXSN48 : entity is 8;
attribute INSTRUCTION_OPCODE of ispPAC_CLK5406D_XXSN48 : entity is
-- 1149.1 instructions
"BYPASS (11111111),"&
"EXTEST (00000000),"&
"PRELOAD (00011100),"&
"SAMPLE (00011100),"&
"INTEST (00101100),"&
"IDCODE (00010110),"&
"USERCODE (00010111),"&
"HIGHZ (00011000),"&
"CLAMP (00100000),"&
-- ISC instructions
"ISC_ENABLE (00010101),"&
"ISC_DISABLE (00011110),"&
"ISC_NOOP (00110000),"&
"ISC_ADDRESS_SHIFT (00000001),"&
"ISC_DATA_SHIFT (00000010),"&
"ISC_ERASE (00000011),"&
"ISC_DISCHARGE (00010100),"&
"ISC_PROGRAM_SECURITY (00001001),"&
"ISC_PROGRAM_DONE (00101111),"&
"ISC_ERASE_DONE (00100100),"&
"ISC_PROGRAM (00100111),"&
"ISC_READ (00101010),"&
"ISC_PROGRAM_USERCODE (00011010),"&
"LSC_USER_LOGIC_RESET (00100010),"&
"PRIVATE (00000111, 00001010)";
attribute INSTRUCTION_CAPTURE of ispPAC_CLK5406D_XXSN48 : entity is
"00011X01";
attribute INSTRUCTION_PRIVATE of ispPAC_CLK5406D_XXSN48 : entity is
"PRIVATE";
-- IDCODE Definition
attribute IDCODE_REGISTER of ispPAC_CLK5406D_XXSN48 : entity is
"XXXX"& -- version number
"0000000101110010"& -- part identification
"00000100001"& -- company code
"1"; -- mandatory
-- USERCODE Definition
attribute USERCODE_REGISTER of ispPAC_CLK5406D_XXSN48 : entity is
"11111111111111111111111111111111";
-- Register Access Description
attribute REGISTER_ACCESS of ispPAC_CLK5406D_XXSN48 : entity is
"BYPASS (BYPASS, "&
" HIGHZ, "&
" CLAMP),"&
"BOUNDARY (PRELOAD, "&
" SAMPLE, "&
" EXTEST, "&
" INTEST),"&
"DEVICE_ID (IDCODE, "&
" USERCODE, "&
" ISC_PROGRAM_USERCODE),"&
"ISC_DEFAULT[1] (ISC_ENABLE, "&
" ISC_DISABLE, "&
" ISC_NOOP, "&
" ISC_ERASE, "&
" ISC_DISCHARGE, "&
" ISC_PROGRAM_SECURITY, "&
" ISC_PROGRAM_DONE, "&
" ISC_ERASE_DONE, "&
" LSC_USER_LOGIC_RESET),"&
"ISC_ADDRESS[10] (ISC_ADDRESS_SHIFT),"&
"ISC_DATA[97] (ISC_DATA_SHIFT),"&
"ISC_PDATA[97] (ISC_PROGRAM, "&
" ISC_READ)";
-- *****************************************************************
-- Boundary Scan Register Description, Cell 0 is the closest to TDO
-- *****************************************************************
attribute BOUNDARY_LENGTH of ispPAC_CLK5406D_XXSN48 : entity is 32;
attribute BOUNDARY_REGISTER of ispPAC_CLK5406D_XXSN48 : entity is
--num cell port function safe [ccell disval rslt]
"31 (BC_1, *, INTERNAL, 0 ),"&
"30 (BC_1, *, INTERNAL, 0 ),"&
"29 (BC_1, *, INTERNAL, 0 ),"&
"28 (BC_1, *, INTERNAL, 0 ),"&
"27 (BC_1, *, INTERNAL, 0 ),"&
"26 (BC_1, *, INTERNAL, 0 ),"&
"25 (BC_1, *, INTERNAL, 0 ),"&
"24 (BC_1, *, INTERNAL, 0 ),"&
"23 (BC_1, BANK_5P, OUTPUT3, X, 22, 0, Z),"&
"22 (BC_1, *, CONTROL, 0 ),"&
"21 (BC_2, REFAP, INPUT, X ),"&
"20 (BC_2, REFBP, INPUT, X ),"&
"19 (BC_2, FBKP, INPUT, X ),"&
"18 (BC_1, BANK_4P, OUTPUT3, X, 17, 0, Z),"&
"17 (BC_1, *, CONTROL, 0 ),"&
"16 (BC_1, BANK_3P, OUTPUT3, X, 15, 0, Z),"&
"15 (BC_1, *, CONTROL, 0 ),"&
"14 (BC_1, BANK_2P, OUTPUT3, X, 13, 0, Z),"&
"13 (BC_1, *, CONTROL, 0 ),"&
"12 (BC_1, BANK_1P, OUTPUT3, X, 11, 0, Z),"&
"11 (BC_1, *, CONTROL, 0 ),"&
"10 (BC_1, BANK_0P, OUTPUT3, X, 9, 0, Z),"&
"9 (BC_1, *, CONTROL, 0 ),"&
"8 (BC_2, RESET, INPUT, X ),"&
"7 (BC_1, USER0, OUTPUT3, X, 6, 0, Z),"&
"6 (BC_1, *, CONTROL, 0 ),"&
"5 (BC_1, USER0, INPUT, X ),"&
"4 (BC_1, USER1, OUTPUT3, X, 3, 0, Z),"&
"3 (BC_1, *, CONTROL, 0 ),"&
"2 (BC_1, USER1, INPUT, X ),"&
"1 (BC_2, USER2, INPUT, X ),"&
"0 (BC_2, USER3, INPUT, X )";
end ispPAC_CLK5406D_XXSN48;