BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: CY7C1372D_119

	--*******************************************************************************************************
--**  Copyright (c) 2002 Cypress Semiconductor
--**  All rights reserved.
--**				    
--**  File Name:     	1372D_x18_119.bsdl
--**  Release:	 	1.1
--**  Last Updated:  	April 23 2006
--**  Part #:	  	CY7C1372D
--**  Package:		119-BGA
--**  Function:		1M x 18 Pipelined SRAM with NOBL, BSDL file for JTAG
--**This revision of the model is different from the previous revision (Rev
--1.0) in that the port type for the Data bits is declared as "inout"
--to comply with the IEEE 1149.1 standard.
--**  Notes:    		IMPORTANT NOTE: Please be aware that the CY7C1372D device is IEEE 
--**				1149.1 compliant. (Refer to datasheet for more.)
--**
--** Written by : Cypress MPD Applications
--** Queries ? :contact Cypress MPD Applications
--**				Reference CY7C1372D datasheet at http://www.cypress.com
--**
--*******************************************************************************************************

entity CY7C1372D_119 is
      generic (PHYSICAL_PIN_MAP : string := "BGA");
      port  (
      A:         in    bit_vector(0 to 19);
      ADV:     in    bit;
      BW_A_b:    in    bit;
      BW_B_b:    in    bit;
      CE1_b:     in    bit;
      CE2:       in    bit;
      CE3_b:     in    bit;
      CEN_b:     in    bit;  
      CLK:       in    bit;
      DP_A:      in    bit;
      DP_B:      in    bit;
      DQ_A:      inout    bit_vector(0 to 7);
      DQ_B:      inout    bit_vector(0 to 7);
      WE_b:      in    bit;
      OE_b:      in    bit;
      MODE:      in    bit;
      TMS:       in    bit;
      TDI:       in    bit;
      TCK:       in    bit;
      TDO:       out   bit;
      ZZ:        in    bit;
      VDD:       linkage bit_vector(0 to 4);
      VDDQ:      linkage bit_vector(0 to 9);
      VSS:       linkage bit_vector(0 to 15);
      NC:        linkage bit_vector(0 to 33)
             );

      use STD_1149_1_1994.all;

      attribute COMPONENT_CONFORMANCE of CY7C1372D_119 : entity is
      "STD_1149_1_1993";

      attribute PIN_MAP of CY7C1372D_119 : entity is PHYSICAL_PIN_MAP;

      constant  BGA:PIN_MAP_STRING:=
    "A:        (P4,N4,T5,T6,R6,C6,A6,C5,B5,A5,G4,A4,C3,B3, " &
               " A3,C2,A2,T2,R2,T3), " &             
                    -- Address
    "ADV:       B4, " &
    "BW_A_b:    L5, " &
    "BW_B_b:    G3, " &  -- Byte Write
    "CE1_b:     E4, " &
    "CE2:       B2, " &
    "CE3_b:     B6, " &
    "CEN_b:     M4, " &
    "CLK:       K4, " &       -- Clock
    "DP_A:      D6, " &
    "DP_B:      P2, " &
    "DQ_A:     (P7,N6,L6,K7,H6,G7,F6,E7), " &
    "DQ_B:     (D1,E2,G2,H1,K2,L1,M2,N1), " &
    "OE_b:      F4, " &
    "WE_b:      H4, " &
    "MODE:      R3, " &
    "TMS:       U2, " &
    "TDI:       U3, " &
    "TCK:       U4, " &
    "TDO:       U5, " &
    "VDD:       (C4,J2,J4,J6,R4), " &
    "VDDQ:      (A1,A7,F1,F7,J1,J7,M1,M7,U1,U7), " &
    "VSS:       (D3,D5,E3,E5,F3,F5,H3,H5,K3,K5, " &
                " M3,M5,N3,N5,P3,P5), " &
    "ZZ:        T7, " &
    "NC:        (B1,B7,C1,C7,D2,D4,D7,E1,E6,F2,G1,G5,G6,H2,H7, "&
                  " J3,J5,K1,K6,L2,L3,L4,L7,M6,N2,N7,P1,P6,R1,R5,"&
                  " R7,T1,T4,U6) ";

      attribute TAP_SCAN_IN    of TDI : signal is true;
      attribute TAP_SCAN_OUT   of TDO : signal is true;
      attribute TAP_SCAN_MODE  of TMS : signal is true;
      attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH);

      attribute INSTRUCTION_LENGTH of CY7C1372D_119 : entity is 3;

      attribute INSTRUCTION_OPCODE of CY7C1372D_119 : entity is
       "EXTEST      (000)," &
       "IDCODE      (001)," &
       "SAMPLE      (010)," &           -- Sample-Z
       "SAMPLD      (100)," &           -- Sample/Preload
       "BYPASS      (111) ";

      attribute INSTRUCTION_CAPTURE of CY7C1372D_119: entity is "001";

      attribute IDCODE_REGISTER of CY7C1372D_119 : entity is
           "000"           & -- Reserved for version number
           "01011"         & -- Defines the voltage of the part
           "001000"        & -- Defines the architecture of the part
           "010101"        & -- Defines the width and density of the part
           "00000110100"   & -- Manufacturer identity
           "1";            -- ID register Presence indicator


      attribute REGISTER_ACCESS of CY7C1372D_119 : entity is
       "BOUNDARY    (EXTEST,SAMPLE,SAMPLD)," &
       "BYPASS      (BYPASS)";

      attribute BOUNDARY_LENGTH of CY7C1372D_119 : entity is 85;

      attribute BOUNDARY_REGISTER of CY7C1372D_119 : entity is
        "0     (BC_4, WE_b,     input,      X)," &
        "1     (BC_4, *,        internal,   X)," &
        "2     (BC_4, A(2),     input,      X)," &
        "3     (BC_4, A(3),     input,      X)," &
        "4     (BC_4, *,        internal,   X)," &
        "5     (BC_4, BW_A_b,   input,      X)," &
        "6     (BC_4, A(4),     input,      X)," &
        "7     (BC_4, *,        internal,   X)," &
        "8     (BC_4, *,        internal,   X)," &
        "9     (BC_4, ZZ,       input,      X)," &
        "10    (BC_4, *,        internal,   X)," &
        "11    (BC_4, *,        internal,   X)," &
        "12    (BC_4, *,        internal,   X)," &
        "13    (BC_4, *,        internal,   X)," &
        "14    (BC_4, *,        internal,    X)," &
        "15    (BC_7, DQ_A(0),  bidir,    X, 84, 0, Z), " &
        "16    (BC_7, DQ_A(1),  bidir,    X, 84, 0, Z), " &  
        "17    (BC_7, DQ_A(2),  bidir,    X, 84, 0, Z), " &
        "18    (BC_7, DQ_A(3),  bidir,    X, 84, 0, Z), " &
        "19    (BC_4, *,        internal, X)," &
        "20    (BC_7, DQ_A(4),  bidir,    X, 84, 0, Z), " &
        "21    (BC_7, DQ_A(5),  bidir,    X, 84, 0, Z), " &
        "22    (BC_7, DQ_A(6),  bidir,    X, 84, 0, Z), " &
        "23    (BC_7, DQ_A(7),  bidir,    X, 84, 0, Z), " &
        "24    (BC_4, *,        internal, X)," &
        "25    (BC_4, *,        internal, X)," &
        "26    (BC_4, *,        internal, X)," &
        "27    (BC_4, *,        internal, X)," &
        "28    (BC_4, DP_A,     input,    X)," &
        "29    (BC_4, *,        internal, X)," &
        "30    (BC_4, *,        internal, X)," &
        "31    (BC_4, A(5),     input,    X)," &
        "32    (BC_4, A(6),     input,    X)," &
        "33    (BC_4, A(7),     input,    X)," &
        "34    (BC_4, A(8),     input,    X)," &
        "35    (BC_4, *,        internal, X)," &
        "36    (BC_4, CE3_b,    input,    X)," &
        "37    (BC_4, *,        internal, X)," &
        "38    (BC_4, ADV,      input,    X)," &
        "39    (BC_4, OE_b,     input,    X)," &
        "40    (BC_4, CEN_b,    input,    X)," &
        "41    (BC_4, A(9),     input,    X)," &
        "42    (BC_4, CLK,       input,    X)," &
        "43    (BC_4, CE1_b,     input,    X)," &
        "44    (BC_4, A(10),     input,    X)," &
        "45    (BC_4, A(11),     input,    X)," &
        "46    (BC_4, BW_B_b,    input,    X)," &
        "47    (BC_4, A(12),     input,    X)," &
        "48    (BC_4, CE2,       input,    X)," &
        "49    (BC_4, A(13),     input,    X)," &
        "50    (BC_4, A(14),     input,    X)," &
        "51    (BC_4, A(15),     input,    X)," &
        "52    (BC_4, A(16),    input,    X)," &
        "53    (BC_4, *,        internal, X)," &
        "54    (BC_4, *,        internal, X)," &
        "55    (BC_4, *,        internal, X)," &
        "56    (BC_4, *,        internal, X)," &
        "57    (BC_4, *,        internal, X)," &
        "58    (BC_4, *,        internal, X)," &
        "59    (BC_4, *,        internal, X)," &
        "60    (BC_7, DQ_B(0),  bidir,    X, 84, 0, Z), " &
        "61    (BC_7, DQ_B(1),  bidir,    X, 84, 0, Z), " &
        "62    (BC_7, DQ_B(2),  bidir,    X, 84, 0, Z), " &
        "63    (BC_7, DQ_B(3),  bidir,    X, 84, 0, Z), " &
        "64    (BC_4, *,        internal, X)," &
        "65    (BC_7, DQ_B(4),  bidir,    X, 84, 0, Z), " &
        "66    (BC_7, DQ_B(5),  bidir,    X, 84, 0, Z), " &
        "67    (BC_7, DQ_B(6),  bidir,    X, 84, 0, Z), " &
        "68    (BC_7, DQ_B(7),  bidir,    X, 84, 0, Z), " &
        "69    (BC_4, *,        internal, X)," &    
        "70    (BC_4, *,        internal, X)," &    
        "71    (BC_4, *,        internal, X)," &
        "72    (BC_4, *,        internal, X)," &
        "73    (BC_4, DP_B,     input,    X)," &
        "74    (BC_4, MODE,     input,    X)," &
        "75    (BC_4, *,        internal, X)," &
        "76    (BC_4, *,        internal, X)," &
        "77    (BC_4, A(17),    input,    X)," &
        "78    (BC_4, *,        internal, X)," &
        "79    (BC_4, A(18),    input,    X)," &
        "80    (BC_4, A(19),    input,    X)," &
        "81    (BC_4, *,        internal, X)," &
        "82    (BC_4, A(1),     input,    X)," &
        "83    (BC_4, A(0),     input,    X)," &
        "84    (BC_2, *,	  controlr,	0) " ;    
end CY7C1372D_119;