--------------------------------------------------------------------------------
-- BSDL File
--
-- Device : MPC5200B
-- File Version : $Revision: 1.2 $
-- File Name : $RCSfile: mpc5200B.bsdl,v $
-- Last modified : $Date: 2004/11/16 17:47:58 $
-- Package type : PBGA
-- Voltage Level : 1.5V, 2.5V, 3.3V
--
-- Revision History:
-- $Log: mpc5200B.bsdl,v $
-- Revision 1.2 2004/11/16 17:47:58 wolfgang
-- Initial check-in of BSDL file for MPC5200B
--
--
--------------------------------------------------------------------------------
--
--============================================================================--
-- IMPORTANT NOTICE --
-- This information is provided on an AS IS basis and without warranty. --
-- IN NO EVENT SHALL FREESCALE BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL --
-- DAMAGES ARISING FROM USE OF THIS INFORMATION. THIS DISCLAIMER OF --
-- WARRANTY EXTENDS TO THE USER OF THE INFORMATION, AND TO THEIR CUSTOMERS --
-- OR USERS OF PRODUCTS AND IS IN LIEU OF ALL WARRANTIES WHETHER EXPRESS, --
-- IMPLIED, OR STATUTORY, INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY --
-- OR FITNESS FOR PARTICULAR PURPOSE. --
-- --
-- FREESCALE does not represent or warrant that the information furnished --
-- hereunder is free of infringement of any third party patents, --
-- copyrights, trade secrets, or other intellectual property rights. --
-- FREESCALE does not represent or warrant that the information is free of --
-- defect, or that it meets any particular standard, requirements or need --
-- of the user of the infomation or their customers. --
-- --
-- FREESCALE reserves the right to change the information in this file --
-- without notice. The latest version of the file is available on the --
-- Freescale Freeware Data Services Bulletin Board system at (512)891-FREE --
-- (3733). Modem settings are 8-bit data, no parity, and one start and one --
-- stop bit. Asynchronous transmission rates to 9600 bits per second are --
-- supported. --
-- --
--============================================================================--
entity MPC5200 is
generic (PHYSICAL_PIN_MAP : string := "PBGA");
port ( test_mode_0: in bit;
test_mode_1: in bit;
test_sel_0: inout bit;
test_sel_1: inout bit;
rtc_xtal_in: linkage bit;
rtc_xtal_out: linkage bit;
timer_2: inout bit;
timer_3: inout bit;
timer_4: inout bit;
timer_5: inout bit;
timer_6: inout bit;
timer_7: inout bit;
usb_9: inout bit;
usb_8: inout bit;
usb_7: inout bit;
usb_6: inout bit;
usb_5: inout bit;
usb_4: inout bit;
usb_3: inout bit;
usb_2: inout bit;
usb_1: inout bit;
usb_0: inout bit;
eth_17: inout bit;
eth_10: inout bit;
eth_4: inout bit;
eth_3: inout bit;
eth_2: inout bit;
eth_1: inout bit;
eth_0: inout bit;
eth_11: inout bit;
eth_5: inout bit;
eth_16: inout bit;
eth_9: inout bit;
eth_8: inout bit;
eth_12: inout bit;
eth_13: inout bit;
eth_14: inout bit;
eth_15: inout bit;
eth_6: inout bit;
eth_7: inout bit;
irq0: inout bit;
irq2: inout bit;
irq1: inout bit;
pci_gnt_b: inout bit;
ext_ad_30: inout bit;
pci_reset_b: inout bit;
irq3: inout bit;
ext_ad_28: inout bit;
ext_ad_26: inout bit;
pci_clock: inout bit;
ext_ad_24: inout bit;
pci_idsel: inout bit;
pci_req_b: inout bit;
ext_ad_20: inout bit;
ext_ad_31: inout bit;
ext_ad_29: inout bit;
ext_ad_27: inout bit;
ext_ad_25: inout bit;
pci_cbe_3_b: inout bit;
ext_ad_22: inout bit;
ext_ad_23: inout bit;
ext_ad_21: inout bit;
ext_ad_18: inout bit;
ext_ad_16: inout bit;
ext_ad_19: inout bit;
pci_frame_b: inout bit;
pci_trdy_b: inout bit;
ext_ad_17: inout bit;
pci_stop_b: inout bit;
pci_cbe_2_b: inout bit;
pci_irdy_b: inout bit;
pci_par: inout bit;
pci_devsel_b: inout bit;
pci_perr_b: inout bit;
ext_ad_15: inout bit;
ext_ad_13: inout bit;
pci_serr_b: inout bit;
pci_cbe_1_b: inout bit;
ext_ad_11: inout bit;
ext_ad_14: inout bit;
ext_ad_12: inout bit;
ext_ad_9: inout bit;
pci_cbe_0_b: inout bit;
ext_ad_10: inout bit;
ext_ad_6: inout bit;
ext_ad_4: inout bit;
ext_ad_8: inout bit;
ext_ad_7: inout bit;
ext_ad_2: inout bit;
ext_ad_5: inout bit;
ext_ad_3: inout bit;
ext_ad_0: inout bit;
ext_ad_1: inout bit;
lp_ts_b: inout bit;
lp_ack: inout bit;
lp_ale_b: inout bit;
lp_cs0_b: inout bit;
lp_cs1_b: inout bit;
lp_cs2_b: inout bit;
lp_cs3_b: inout bit;
lp_cs4_b: inout bit;
lp_cs5_b: inout bit;
lp_rw: inout bit;
ata_isolation: inout bit;
ata_drq: inout bit;
ata_iow_b: inout bit;
ata_ior_b: inout bit;
ata_iochrdy: inout bit;
ata_dack_b: inout bit;
ata_intrq: inout bit;
timer_0: inout bit;
i2c_1: inout bit;
i2c_3: inout bit;
timer_1: inout bit;
i2c_0: inout bit;
i2c_2: inout bit;
mem_mdq_31: inout bit;
mem_mdq_1: inout bit;
mem_mdq_0: inout bit;
mem_mdq_30: inout bit;
mem_mdq_3: inout bit;
mem_mdq_2: inout bit;
mem_mdq_28: inout bit;
mem_mdq_29: inout bit;
mem_mdq_5: inout bit;
mem_mdq_4: inout bit;
mem_mdq_27: inout bit;
mem_mdq_7: inout bit;
mem_mdq_6: inout bit;
mem_mdq_25: inout bit;
mem_mdq_26: inout bit;
mem_dqm_0: inout bit;
mem_mdqs_0: inout bit;
mem_mdq_24: inout bit;
mem_mdq_14: inout bit;
mem_mdq_15: inout bit;
mem_dqm_3: inout bit;
mem_mdqs_3: inout bit;
mem_mdq_12: inout bit;
mem_mdq_13: inout bit;
mem_mdq_23: inout bit;
mem_mdq_10: inout bit;
mem_mdq_11: inout bit;
mem_mdq_22: inout bit;
mem_mdq_21: inout bit;
mem_mdq_8: inout bit;
mem_mdq_9: inout bit;
mem_mdq_20: inout bit;
mem_dqm_1: inout bit;
mem_mdqs_1: inout bit;
mem_mdq_18: inout bit;
mem_mdq_19: inout bit;
mem_clk: inout bit;
mem_clk_b: inout bit;
mem_mdq_17: inout bit;
mem_ma_12: inout bit;
mem_clk_en: inout bit;
mem_mdq_16: inout bit;
mem_ma_9: inout bit;
mem_ma_11: inout bit;
mem_mdqs_2: inout bit;
mem_ma_7: inout bit;
mem_ma_8: inout bit;
mem_ma_6: inout bit;
mem_ma_5: inout bit;
mem_ma_4: inout bit;
mem_dqm_2: inout bit;
mem_cas_b: inout bit;
mem_we_b: inout bit;
mem_mba_0: inout bit;
mem_cs_0_b: inout bit;
mem_ras_b: inout bit;
mem_ma_0: inout bit;
mem_ma_10: inout bit;
mem_mba_1: inout bit;
mem_ma_3: inout bit;
mem_ma_2: inout bit;
mem_ma_1: inout bit;
gpio_wkup_6: inout bit;
sys_pll_tpa: inout bit;
sys_xtal_in: linkage bit;
sys_xtal_out: linkage bit;
sys_pll_avss: linkage bit;
sys_pll_avdd: linkage bit;
sreset_b: inout bit;
psc6_3: inout bit;
hreset_b: inout bit;
porreset_b: in bit;
gpio_wkup_7: inout bit;
psc6_0: inout bit;
psc6_2: inout bit;
psc6_1: inout bit;
psc1_0: inout bit;
psc1_1: inout bit;
psc1_2: inout bit;
psc1_3: inout bit;
psc1_4: inout bit;
psc2_0: inout bit;
psc2_1: inout bit;
psc2_2: inout bit;
lp_oe: inout bit;
core_pll_avdd: linkage bit;
psc2_3: inout bit;
psc2_4: inout bit;
psc3_0: inout bit;
psc3_1: inout bit;
psc3_2: inout bit;
psc3_3: inout bit;
psc3_4: inout bit;
psc3_5: inout bit;
psc3_6: inout bit;
psc3_7: inout bit;
psc3_8: inout bit;
psc3_9: inout bit;
jtag_tck: in bit;
jtag_tms: in bit;
jtag_tdi: in bit;
jtag_trst_b: in bit;
jtag_tdo: out bit;
vdd_mem_io: linkage bit_vector(0 to 10);
vdd_io: linkage bit_vector(0 to 11);
vdd_core: linkage bit_vector(0 to 9);
vss_io_core: linkage bit_vector(0 to 19));
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of MPC5200 : entity is "STD_1149_1_1993";
attribute PIN_MAP of MPC5200 : entity is PHYSICAL_PIN_MAP;
constant PBGA : PIN_MAP_STRING :=
"test_mode_1: A1, " &
"jtag_tdo: A2, " &
"jtag_tdi: A3, " &
"jtag_tms: A4, " &
"psc3_8: A5, " &
"psc3_5: A6, " &
"psc3_2: A7, " &
"psc2_4: A8, " &
"psc2_2: A9, " &
"psc1_4: A10, " &
"psc1_1: A11, " &
"psc6_2: A12, " &
"porreset_b: A13, " &
"sreset_b: A14, " &
"sys_xtal_in: A15, " &
"mem_ma_1: A16, " &
"mem_mba_1: A17, " &
"mem_ras_b: A18, " &
"mem_we_b: A19, " &
"mem_dqm_2: A20, " &
"test_sel_0: B1, " &
"test_mode_0: B2, " &
"jtag_trst_b: B3, " &
"jtag_tck: B4, " &
"psc3_7: B5, " &
"psc3_4: B6, " &
"psc3_1: B7, " &
"psc2_3: B8, " &
"psc2_1: B9, " &
"psc1_3: B10, " &
"psc1_0: B11, " &
"psc6_0: B12, " &
"hreset_b: B13, " &
"sys_pll_avdd: B14, " &
"sys_pll_tpa: B15, " &
"mem_ma_2: B16, " &
"mem_ma_10: B17, " &
"mem_cs_0_b: B18, " &
"mem_cas_b: B19, " &
"mem_ma_4: B20, " &
"rtc_xtal_out: C1, " &
"rtc_xtal_in: C2, " &
"test_sel_1: C3, " &
"psc3_9: C4, " &
"psc3_6: C5, " &
"psc3_3: C6, " &
"psc3_0: C7, " &
"core_pll_avdd: C8, " &
"psc2_0: C9, " &
"psc1_2: C10, " &
"psc6_1: C11, " &
"gpio_wkup_7: C12, " &
"psc6_3: C13, " &
"sys_pll_avss: C14, " &
"gpio_wkup_6: C15, " &
"mem_ma_3: C16, " &
"mem_ma_0: C17, " &
"mem_mba_0: C18, " &
"mem_ma_5: C19, " &
"mem_ma_6: C20, " &
"timer_4: D1, " &
"timer_3: D2, " &
"timer_2: D3, " &
"vss_io_core: (D4, D16, J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, " &
"M12, U4, U17), " &
"vdd_core: (D5, D7, D10, D11, K4, M4, P4, U7, U12, U15), " &
"vdd_io: (D6, D9, E4, F4, H4, T4, U5, U6, U9, U10, U13, U16), " &
"lp_oe: D8, " &
"vdd_mem_io: (D12, D13, D15, D17, E17, F17, H17, K17, M17, P17, T17), " &
"sys_xtal_out: D14, " &
"mem_mdqs_2: D18, " &
"mem_ma_7: D19, " &
"mem_ma_8: D20, " &
"timer_7: E1, " &
"timer_6: E2, " &
"timer_5: E3, " &
"mem_mdq_16: E18, " &
"mem_ma_9: E19, " &
"mem_ma_11: E20, " &
"usb_7: F1, " &
"usb_8: F2, " &
"usb_9: F3, " &
"mem_mdq_17: F18, " &
"mem_ma_12: F19, " &
"mem_clk_en: F20, " &
"usb_3: G1, " &
"usb_4: G2, " &
"usb_5: G3, " &
"usb_6: G4, " &
"mem_mdq_18: G17, " &
"mem_mdq_19: G18, " &
"mem_clk: G19, " &
"mem_clk_b: G20, " &
"usb_0: H1, " &
"usb_1: H2, " &
"usb_2: H3, " &
"mem_mdq_20: H18, " &
"mem_dqm_1: H19, " &
"mem_mdqs_1: H20, " &
"eth_3: J1, " &
"eth_4: J2, " &
"eth_10: J3, " &
"eth_17: J4, " &
"mem_mdq_22: J17, " &
"mem_mdq_21: J18, " &
"mem_mdq_8: J19, " &
"mem_mdq_9: J20, " &
"eth_0: K1, " &
"eth_1: K2, " &
"eth_2: K3, " &
"mem_mdq_23: K18, " &
"mem_mdq_10: K19, " &
"mem_mdq_11: K20, " &
"eth_9: L1, " &
"eth_16: L2, " &
"eth_5: L3, " &
"eth_11: L4, " &
"mem_dqm_3: L17, " &
"mem_mdqs_3: L18, " &
"mem_mdq_12: L19, " &
"mem_mdq_13: L20, " &
"eth_13: M1, " &
"eth_12: M2, " &
"eth_8: M3, " &
"mem_mdq_24: M18, " &
"mem_mdq_14: M19, " &
"mem_mdq_15: M20, " &
"eth_7: N1, " &
"eth_6: N2, " &
"eth_15: N3, " &
"eth_14: N4, " &
"mem_mdq_25: N17, " &
"mem_mdq_26: N18, " &
"mem_dqm_0: N19, " &
"mem_mdqs_0: N20, " &
"irq1: P1, " &
"irq2: P2, " &
"irq0: P3, " &
"mem_mdq_27: P18, " &
"mem_mdq_7: P19, " &
"mem_mdq_6: P20, " &
"irq3: R1, " &
"pci_reset_b: R2, " &
"ext_ad_30: R3, " &
"pci_gnt_b: R4, " &
"mem_mdq_28: R17, " &
"mem_mdq_29: R18, " &
"mem_mdq_5: R19, " &
"mem_mdq_4: R20, " &
"pci_clock: T1, " &
"ext_ad_26: T2, " &
"ext_ad_28: T3, " &
"mem_mdq_30: T18, " &
"mem_mdq_3: T19, " &
"mem_mdq_2: T20, " &
"pci_req_b: U1, " &
"pci_idsel: U2, " &
"ext_ad_24: U3, " &
"ext_ad_15: U8, " &
"ext_ad_6: U11, " &
"lp_ack: U14, " &
"mem_mdq_31: U18, " &
"mem_mdq_1: U19, " &
"mem_mdq_0: U20, " &
"ext_ad_31: V1, " &
"ext_ad_20: V2, " &
"ext_ad_22: V3, " &
"ext_ad_18: V4, " &
"pci_frame_b: V5, " &
"pci_stop_b: V6, " &
"pci_par: V7, " &
"ext_ad_13: V8, " &
"ext_ad_11: V9, " &
"ext_ad_9: V10, " &
"ext_ad_4: V11, " &
"ext_ad_2: V12, " &
"ext_ad_0: V13, " &
"lp_ale_b: V14, " &
"lp_cs2_b: V15, " &
"lp_cs5_b: V16, " &
"ata_drq: V17, " &
"timer_1: V18, " &
"i2c_0: V19, " &
"i2c_2: V20, " &
"ext_ad_29: W1, " &
"ext_ad_25: W2, " &
"ext_ad_23: W3, " &
"ext_ad_16: W4, " &
"pci_trdy_b: W5, " &
"pci_cbe_2_b: W6, " &
"pci_devsel_b: W7, " &
"pci_serr_b: W8, " &
"ext_ad_14: W9, " &
"pci_cbe_0_b: W10, " &
"ext_ad_8: W11, " &
"ext_ad_5: W12, " &
"ext_ad_1: W13, " &
"lp_cs0_b: W14, " &
"lp_cs3_b: W15, " &
"lp_rw: W16, " &
"ata_iow_b: W17, " &
"ata_iochrdy: W18, " &
"i2c_1: W19, " &
"i2c_3: W20, " &
"ext_ad_27: Y1, " &
"pci_cbe_3_b: Y2, " &
"ext_ad_21: Y3, " &
"ext_ad_19: Y4, " &
"ext_ad_17: Y5, " &
"pci_irdy_b: Y6, " &
"pci_perr_b: Y7, " &
"pci_cbe_1_b: Y8, " &
"ext_ad_12: Y9, " &
"ext_ad_10: Y10, " &
"ext_ad_7: Y11, " &
"ext_ad_3: Y12, " &
"lp_ts_b: Y13, " &
"lp_cs1_b: Y14, " &
"lp_cs4_b: Y15, " &
"ata_isolation: Y16, " &
"ata_ior_b: Y17, " &
"ata_dack_b: Y18, " &
"ata_intrq: Y19, " &
"timer_0: Y20 ";
attribute TAP_SCAN_IN of jtag_tdi : signal is true;
attribute TAP_SCAN_OUT of jtag_tdo : signal is true;
attribute TAP_SCAN_MODE of jtag_tms : signal is true;
attribute TAP_SCAN_RESET of jtag_trst_b : signal is true;
attribute TAP_SCAN_CLOCK of jtag_tck : signal is (50.0e6, BOTH);
attribute COMPLIANCE_PATTERNS of MPC5200 : entity is
"(test_mode_0, test_mode_1) (00)";
attribute INSTRUCTION_LENGTH of MPC5200 : entity is 6;
attribute INSTRUCTION_OPCODE of MPC5200 : entity is
"IDCODE (011101)," &
"BYPASS (111111)," &
"SAMPLE (100000)," &
"EXTEST (000000)," &
"CLAMP (100001)," &
"HIGHZ (011111)," &
"BYPASS_TLMSEL (111110)," &
"HIGHZ_TLMSEL (011110)," &
"EXTEST_TLMSEL (000001)," &
"BURNIN (110110)," &
"IDDQ (110111)," &
"HRESET_B_ENABLE (001000)," &
"HRESET_B_DISABLE (001001)," &
"SRESET_B_ENABLE (001010)," &
"SRESET_B_DISABLE (001011)," &
"DBGCDM_DR_SEL (001100)," &
"DBGCDM (001101)," &
"RS_DBGCDM (100010)," &
"PMODE_DR_SEL (111011)," &
"PM_OVERRIDE (111100)," &
"RS_PM_OVERRIDE (111101)," &
"DBGCLKMUX_DR_SEL (100011)," &
"DBGCLKMUX (100100)," &
"RS_DBGCLKMUX (100101)," &
"MBIST_ADDR_SEL (001110)," &
"MBIST_DATA_SEL (001111)," &
"LONGSCAN (110010)," &
"RS_LONGSCAN (110011)," &
"MBAR_SEL (111010)," &
"PLLSCAN (110000)," &
"PPCLSSD (110001)," &
"ASICSCANPLL (110100)," &
"ASICSCANBYP (110101)," &
"MBIST (111000)," &
"MDIAG (111001)";
attribute INSTRUCTION_CAPTURE of MPC5200 : entity is "011101";
attribute INSTRUCTION_PRIVATE of MPC5200 : entity is
"BYPASS_TLMSEL, HIGHZ_TLMSEL, EXTEST_TLMSEL, BURNIN, IDDQ, HRESET_B_ENABLE, " &
"HRESET_B_DISABLE, SRESET_B_ENABLE, SRESET_B_DISABLE, DBGCDM_DR_SEL, " &
"DBGCDM, RS_DBGCDM, PMODE_DR_SEL, PM_OVERRIDE, RS_PM_OVERRIDE, " &
"DBGCLKMUX_DR_SEL, DBGCLKMUX, RS_DBGCLKMUX, MBIST_ADDR_SEL, MBIST_DATA_SEL, " &
"LONGSCAN, RS_LONGSCAN, MBAR_SEL, PLLSCAN, PPCLSSD, ASICSCANPLL, " &
"ASICSCANBYP, MBIST, MDIAG";
attribute IDCODE_REGISTER of MPC5200 : entity is
"00010000000000010001000000011101";
attribute REGISTER_ACCESS of MPC5200 : entity is
"BYPASS (BYPASS," &
" CLAMP," &
" HIGHZ," &
" BURNIN," &
" IDDQ," &
" HRESET_B_ENABLE," &
" HRESET_B_DISABLE," &
" SRESET_B_ENABLE," &
" SRESET_B_DISABLE," &
" DBGCDM," &
" RS_DBGCDM," &
" PM_OVERRIDE," &
" RS_PM_OVERRIDE," &
" DBGCLKMUX," &
" RS_DBGCLKMUX," &
" LONGSCAN," &
" RS_LONGSCAN," &
" PLLSCAN," &
" PPCLSSD," &
" ASICSCANPLL," &
" ASICSCANBYP," &
" MBIST," &
" MDIAG)," &
"LINKDR[2] (EXTEST_TLMSEL," &
" HIGHZ_TLMSEL," &
" BYPASS_TLMSEL)";
attribute BOUNDARY_LENGTH of MPC5200 : entity is 615;
attribute BOUNDARY_REGISTER of MPC5200 : entity is
-- num cell port func safe [ccell dis rslt]
"0 (BC_1, *, control, 1)," &
"1 (BC_1, test_sel_0, output3, 1, 0, 1, Pull1)," &
"2 (BC_1, test_sel_0, input, X)," &
"3 (BC_1, *, control, 1)," &
"4 (BC_1, test_sel_1, output3, 1, 3, 1, Z)," &
"5 (BC_1, test_sel_1, input, X)," &
"6 (BC_1, *, control, 1)," &
"7 (BC_1, timer_2, output3, 1, 6, 1, Z)," &
"8 (BC_1, timer_2, input, X)," &
"9 (BC_1, *, control, 1)," &
"10 (BC_1, timer_3, output3, 1, 9, 1, Z)," &
"11 (BC_1, timer_3, input, X)," &
"12 (BC_1, *, control, 1)," &
"13 (BC_1, timer_4, output3, 1, 12, 1, Z)," &
"14 (BC_1, timer_4, input, X)," &
"15 (BC_1, *, control, 1)," &
"16 (BC_1, timer_5, output3, 1, 15, 1, Z)," &
"17 (BC_1, timer_5, input, X)," &
"18 (BC_1, *, control, 1)," &
"19 (BC_1, timer_6, output3, 1, 18, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"20 (BC_1, timer_6, input, X)," &
"21 (BC_1, *, control, 1)," &
"22 (BC_1, timer_7, output3, 1, 21, 1, Z)," &
"23 (BC_1, timer_7, input, X)," &
"24 (BC_1, *, control, 1)," &
"25 (BC_1, usb_9, output3, 1, 24, 1, Z)," &
"26 (BC_1, usb_9, input, X)," &
"27 (BC_1, *, control, 1)," &
"28 (BC_1, usb_8, output3, 1, 27, 1, Z)," &
"29 (BC_1, usb_8, input, X)," &
"30 (BC_1, *, control, 1)," &
"31 (BC_1, usb_7, output3, 1, 30, 1, Z)," &
"32 (BC_1, usb_7, input, X)," &
"33 (BC_1, *, control, 1)," &
"34 (BC_1, usb_6, output3, 1, 33, 1, Z)," &
"35 (BC_1, usb_6, input, X)," &
"36 (BC_1, *, control, 1)," &
"37 (BC_1, usb_5, output3, 1, 36, 1, Z)," &
"38 (BC_1, usb_5, input, X)," &
"39 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"40 (BC_1, usb_4, output3, 1, 39, 1, Z)," &
"41 (BC_1, usb_4, input, X)," &
"42 (BC_1, *, control, 1)," &
"43 (BC_1, usb_3, output3, 1, 42, 1, Z)," &
"44 (BC_1, usb_3, input, X)," &
"45 (BC_1, *, control, 1)," &
"46 (BC_1, usb_2, output3, 1, 45, 1, Z)," &
"47 (BC_1, usb_2, input, X)," &
"48 (BC_1, *, control, 1)," &
"49 (BC_1, usb_1, output3, 1, 48, 1, Z)," &
"50 (BC_1, usb_1, input, X)," &
"51 (BC_1, *, control, 1)," &
"52 (BC_1, usb_0, output3, 1, 51, 1, Z)," &
"53 (BC_1, usb_0, input, X)," &
"54 (BC_1, *, control, 1)," &
"55 (BC_1, eth_17, output3, 1, 54, 1, Z)," &
"56 (BC_1, eth_17, input, X)," &
"57 (BC_1, *, control, 1)," &
"58 (BC_1, eth_10, output3, 1, 57, 1, Z)," &
"59 (BC_1, eth_10, input, X)," &
-- num cell port func safe [ccell dis rslt]
"60 (BC_1, *, control, 1)," &
"61 (BC_1, eth_4, output3, 1, 60, 1, Z)," &
"62 (BC_1, eth_4, input, X)," &
"63 (BC_1, *, control, 1)," &
"64 (BC_1, eth_3, output3, 1, 63, 1, Z)," &
"65 (BC_1, eth_3, input, X)," &
"66 (BC_1, *, control, 1)," &
"67 (BC_1, eth_2, output3, 1, 66, 1, Z)," &
"68 (BC_1, eth_2, input, X)," &
"69 (BC_1, *, control, 1)," &
"70 (BC_1, eth_1, output3, 1, 69, 1, Z)," &
"71 (BC_1, eth_1, input, X)," &
"72 (BC_1, *, control, 1)," &
"73 (BC_1, eth_0, output3, 1, 72, 1, Z)," &
"74 (BC_1, eth_0, input, X)," &
"75 (BC_1, *, control, 1)," &
"76 (BC_1, eth_11, output3, 1, 75, 1, Z)," &
"77 (BC_1, eth_11, input, X)," &
"78 (BC_1, *, control, 1)," &
"79 (BC_1, eth_5, output3, 1, 78, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"80 (BC_1, eth_5, input, X)," &
"81 (BC_1, *, control, 1)," &
"82 (BC_1, eth_16, output3, 1, 81, 1, Z)," &
"83 (BC_1, eth_16, input, X)," &
"84 (BC_1, *, control, 1)," &
"85 (BC_1, eth_9, output3, 1, 84, 1, Z)," &
"86 (BC_1, eth_9, input, X)," &
"87 (BC_1, *, control, 1)," &
"88 (BC_1, eth_8, output3, 1, 87, 1, Z)," &
"89 (BC_1, eth_8, input, X)," &
"90 (BC_1, *, control, 1)," &
"91 (BC_1, eth_12, output3, 1, 90, 1, Z)," &
"92 (BC_1, eth_12, input, X)," &
"93 (BC_1, *, control, 1)," &
"94 (BC_1, eth_13, output3, 1, 93, 1, Z)," &
"95 (BC_1, eth_13, input, X)," &
"96 (BC_1, *, control, 1)," &
"97 (BC_1, eth_14, output3, 1, 96, 1, Z)," &
"98 (BC_1, eth_14, input, X)," &
"99 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"100 (BC_1, eth_15, output3, 1, 99, 1, Z)," &
"101 (BC_1, eth_15, input, X)," &
"102 (BC_1, *, control, 1)," &
"103 (BC_1, eth_6, output3, 1, 102, 1, Z)," &
"104 (BC_1, eth_6, input, X)," &
"105 (BC_1, *, control, 1)," &
"106 (BC_1, eth_7, output3, 1, 105, 1, Z)," &
"107 (BC_1, eth_7, input, X)," &
"108 (BC_1, *, control, 1)," &
"109 (BC_1, irq0, output3, 1, 108, 1, Z)," &
"110 (BC_1, irq0, input, X)," &
"111 (BC_1, *, control, 1)," &
"112 (BC_1, irq2, output3, 1, 111, 1, Z)," &
"113 (BC_1, irq2, input, X)," &
"114 (BC_1, *, control, 1)," &
"115 (BC_1, irq1, output3, 1, 114, 1, Z)," &
"116 (BC_1, irq1, input, X)," &
"117 (BC_1, *, control, 1)," &
"118 (BC_1, pci_gnt_b, output3, 1, 117, 1, Z)," &
"119 (BC_1, pci_gnt_b, input, X)," &
-- num cell port func safe [ccell dis rslt]
"120 (BC_1, *, control, 1)," &
"121 (BC_1, ext_ad_30, output3, 1, 120, 1, Z)," &
"122 (BC_1, ext_ad_30, input, X)," &
"123 (BC_1, *, control, 1)," &
"124 (BC_1, pci_reset_b, output3, 1, 123, 1, Z)," &
"125 (BC_1, pci_reset_b, input, X)," &
"126 (BC_1, *, control, 1)," &
"127 (BC_1, irq3, output3, 1, 126, 1, Z)," &
"128 (BC_1, irq3, input, X)," &
"129 (BC_1, *, control, 1)," &
"130 (BC_1, ext_ad_28, output3, 1, 129, 1, Z)," &
"131 (BC_1, ext_ad_28, input, X)," &
"132 (BC_1, *, control, 1)," &
"133 (BC_1, ext_ad_26, output3, 1, 132, 1, Z)," &
"134 (BC_1, ext_ad_26, input, X)," &
"135 (BC_1, *, control, 1)," &
"136 (BC_1, pci_clock, output3, 1, 135, 1, Z)," &
"137 (BC_1, pci_clock, input, X)," &
"138 (BC_1, *, control, 1)," &
"139 (BC_1, ext_ad_24, output3, 1, 138, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"140 (BC_1, ext_ad_24, input, X)," &
"141 (BC_1, *, control, 1)," &
"142 (BC_1, pci_idsel, output3, 1, 141, 1, Z)," &
"143 (BC_1, pci_idsel, input, X)," &
"144 (BC_1, *, control, 1)," &
"145 (BC_1, pci_req_b, output3, 1, 144, 1, Z)," &
"146 (BC_1, pci_req_b, input, X)," &
"147 (BC_1, *, control, 1)," &
"148 (BC_1, ext_ad_20, output3, 1, 147, 1, Z)," &
"149 (BC_1, ext_ad_20, input, X)," &
"150 (BC_1, *, control, 1)," &
"151 (BC_1, ext_ad_31, output3, 1, 150, 1, Z)," &
"152 (BC_1, ext_ad_31, input, X)," &
"153 (BC_1, *, control, 1)," &
"154 (BC_1, ext_ad_29, output3, 1, 153, 1, Z)," &
"155 (BC_1, ext_ad_29, input, X)," &
"156 (BC_1, *, control, 1)," &
"157 (BC_1, ext_ad_27, output3, 1, 156, 1, Z)," &
"158 (BC_1, ext_ad_27, input, X)," &
"159 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"160 (BC_1, ext_ad_25, output3, 1, 159, 1, Z)," &
"161 (BC_1, ext_ad_25, input, X)," &
"162 (BC_1, *, control, 1)," &
"163 (BC_1, pci_cbe_3_b, output3, 1, 162, 1, Z)," &
"164 (BC_1, pci_cbe_3_b, input, X)," &
"165 (BC_1, *, control, 1)," &
"166 (BC_1, ext_ad_22, output3, 1, 165, 1, Z)," &
"167 (BC_1, ext_ad_22, input, X)," &
"168 (BC_1, *, control, 1)," &
"169 (BC_1, ext_ad_23, output3, 1, 168, 1, Z)," &
"170 (BC_1, ext_ad_23, input, X)," &
"171 (BC_1, *, control, 1)," &
"172 (BC_1, ext_ad_21, output3, 1, 171, 1, Z)," &
"173 (BC_1, ext_ad_21, input, X)," &
"174 (BC_1, *, control, 1)," &
"175 (BC_1, ext_ad_18, output3, 1, 174, 1, Z)," &
"176 (BC_1, ext_ad_18, input, X)," &
"177 (BC_1, *, control, 1)," &
"178 (BC_1, ext_ad_16, output3, 1, 177, 1, Z)," &
"179 (BC_1, ext_ad_16, input, X)," &
-- num cell port func safe [ccell dis rslt]
"180 (BC_1, *, control, 1)," &
"181 (BC_1, ext_ad_19, output3, 1, 180, 1, Z)," &
"182 (BC_1, ext_ad_19, input, X)," &
"183 (BC_1, *, control, 1)," &
"184 (BC_1, pci_frame_b, output3, 1, 183, 1, Z)," &
"185 (BC_1, pci_frame_b, input, X)," &
"186 (BC_1, *, control, 1)," &
"187 (BC_1, pci_trdy_b, output3, 1, 186, 1, Z)," &
"188 (BC_1, pci_trdy_b, input, X)," &
"189 (BC_1, *, control, 1)," &
"190 (BC_1, ext_ad_17, output3, 1, 189, 1, Z)," &
"191 (BC_1, ext_ad_17, input, X)," &
"192 (BC_1, *, control, 1)," &
"193 (BC_1, pci_stop_b, output3, 1, 192, 1, Z)," &
"194 (BC_1, pci_stop_b, input, X)," &
"195 (BC_1, *, control, 1)," &
"196 (BC_1, pci_cbe_2_b, output3, 1, 195, 1, Z)," &
"197 (BC_1, pci_cbe_2_b, input, X)," &
"198 (BC_1, *, control, 1)," &
"199 (BC_1, pci_irdy_b, output3, 1, 198, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"200 (BC_1, pci_irdy_b, input, X)," &
"201 (BC_1, *, control, 1)," &
"202 (BC_1, pci_par, output3, 1, 201, 1, Z)," &
"203 (BC_1, pci_par, input, X)," &
"204 (BC_1, *, control, 1)," &
"205 (BC_1, pci_devsel_b, output3, 1, 204, 1, Z)," &
"206 (BC_1, pci_devsel_b, input, X)," &
"207 (BC_1, *, control, 1)," &
"208 (BC_1, pci_perr_b, output3, 1, 207, 1, Z)," &
"209 (BC_1, pci_perr_b, input, X)," &
"210 (BC_1, *, control, 1)," &
"211 (BC_1, ext_ad_15, output3, 1, 210, 1, Z)," &
"212 (BC_1, ext_ad_15, input, X)," &
"213 (BC_1, *, control, 1)," &
"214 (BC_1, ext_ad_13, output3, 1, 213, 1, Z)," &
"215 (BC_1, ext_ad_13, input, X)," &
"216 (BC_1, *, control, 1)," &
"217 (BC_1, pci_serr_b, output3, 1, 216, 1, Z)," &
"218 (BC_1, pci_serr_b, input, X)," &
"219 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"220 (BC_1, pci_cbe_1_b, output3, 1, 219, 1, Z)," &
"221 (BC_1, pci_cbe_1_b, input, X)," &
"222 (BC_1, *, control, 1)," &
"223 (BC_1, ext_ad_11, output3, 1, 222, 1, Z)," &
"224 (BC_1, ext_ad_11, input, X)," &
"225 (BC_1, *, control, 1)," &
"226 (BC_1, ext_ad_14, output3, 1, 225, 1, Z)," &
"227 (BC_1, ext_ad_14, input, X)," &
"228 (BC_1, *, control, 1)," &
"229 (BC_1, ext_ad_12, output3, 1, 228, 1, Z)," &
"230 (BC_1, ext_ad_12, input, X)," &
"231 (BC_1, *, control, 1)," &
"232 (BC_1, ext_ad_9, output3, 1, 231, 1, Z)," &
"233 (BC_1, ext_ad_9, input, X)," &
"234 (BC_1, *, control, 1)," &
"235 (BC_1, pci_cbe_0_b, output3, 1, 234, 1, Z)," &
"236 (BC_1, pci_cbe_0_b, input, X)," &
"237 (BC_1, *, control, 1)," &
"238 (BC_1, ext_ad_10, output3, 1, 237, 1, Z)," &
"239 (BC_1, ext_ad_10, input, X)," &
-- num cell port func safe [ccell dis rslt]
"240 (BC_1, *, control, 1)," &
"241 (BC_1, ext_ad_6, output3, 1, 240, 1, Z)," &
"242 (BC_1, ext_ad_6, input, X)," &
"243 (BC_1, *, control, 1)," &
"244 (BC_1, ext_ad_4, output3, 1, 243, 1, Z)," &
"245 (BC_1, ext_ad_4, input, X)," &
"246 (BC_1, *, control, 1)," &
"247 (BC_1, ext_ad_8, output3, 1, 246, 1, Z)," &
"248 (BC_1, ext_ad_8, input, X)," &
"249 (BC_1, *, control, 1)," &
"250 (BC_1, ext_ad_7, output3, 1, 249, 1, Z)," &
"251 (BC_1, ext_ad_7, input, X)," &
"252 (BC_1, *, control, 1)," &
"253 (BC_1, ext_ad_2, output3, 1, 252, 1, Z)," &
"254 (BC_1, ext_ad_2, input, X)," &
"255 (BC_1, *, control, 1)," &
"256 (BC_1, ext_ad_5, output3, 1, 255, 1, Z)," &
"257 (BC_1, ext_ad_5, input, X)," &
"258 (BC_1, *, control, 1)," &
"259 (BC_1, ext_ad_3, output3, 1, 258, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"260 (BC_1, ext_ad_3, input, X)," &
"261 (BC_1, *, control, 1)," &
"262 (BC_1, ext_ad_0, output3, 1, 261, 1, Z)," &
"263 (BC_1, ext_ad_0, input, X)," &
"264 (BC_1, *, control, 1)," &
"265 (BC_1, ext_ad_1, output3, 1, 264, 1, Z)," &
"266 (BC_1, ext_ad_1, input, X)," &
"267 (BC_1, *, control, 1)," &
"268 (BC_1, lp_ts_b, output3, 1, 267, 1, Z)," &
"269 (BC_1, lp_ts_b, input, X)," &
"270 (BC_1, *, control, 1)," &
"271 (BC_1, lp_ack, output3, 1, 270, 1, Pull1)," &
"272 (BC_1, lp_ack, input, X)," &
"273 (BC_1, *, control, 1)," &
"274 (BC_1, lp_ale_b, output3, 1, 273, 1, Z)," &
"275 (BC_1, lp_ale_b, input, X)," &
"276 (BC_1, *, control, 1)," &
"277 (BC_1, lp_cs0_b, output3, 1, 276, 1, Z)," &
"278 (BC_1, lp_cs0_b, input, X)," &
"279 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"280 (BC_1, lp_cs1_b, output3, 1, 279, 1, Z)," &
"281 (BC_1, lp_cs1_b, input, X)," &
"282 (BC_1, *, control, 1)," &
"283 (BC_1, lp_cs2_b, output3, 1, 282, 1, Z)," &
"284 (BC_1, lp_cs2_b, input, X)," &
"285 (BC_1, *, control, 1)," &
"286 (BC_1, lp_cs3_b, output3, 1, 285, 1, Z)," &
"287 (BC_1, lp_cs3_b, input, X)," &
"288 (BC_1, *, control, 1)," &
"289 (BC_1, lp_cs4_b, output3, 1, 288, 1, Z)," &
"290 (BC_1, lp_cs4_b, input, X)," &
"291 (BC_1, *, control, 1)," &
"292 (BC_1, lp_cs5_b, output3, 1, 291, 1, Z)," &
"293 (BC_1, lp_cs5_b, input, X)," &
"294 (BC_1, *, control, 1)," &
"295 (BC_1, lp_rw, output3, 1, 294, 1, Z)," &
"296 (BC_1, lp_rw, input, X)," &
"297 (BC_1, *, control, 1)," &
"298 (BC_1, ata_isolation, output3, 1, 297, 1, Z)," &
"299 (BC_1, ata_isolation, input, X)," &
-- num cell port func safe [ccell dis rslt]
"300 (BC_1, *, control, 1)," &
"301 (BC_1, ata_drq, output3, 1, 300, 1, Pull0)," &
"302 (BC_1, ata_drq, input, X)," &
"303 (BC_1, *, control, 1)," &
"304 (BC_1, ata_iow_b, output3, 1, 303, 1, Z)," &
"305 (BC_1, ata_iow_b, input, X)," &
"306 (BC_1, *, control, 1)," &
"307 (BC_1, ata_ior_b, output3, 1, 306, 1, Z)," &
"308 (BC_1, ata_ior_b, input, X)," &
"309 (BC_1, *, control, 1)," &
"310 (BC_1, ata_iochrdy, output3, 1, 309, 1, Pull1)," &
"311 (BC_1, ata_iochrdy, input, X)," &
"312 (BC_1, *, control, 1)," &
"313 (BC_1, ata_dack_b, output3, 1, 312, 1, Z)," &
"314 (BC_1, ata_dack_b, input, X)," &
"315 (BC_1, *, control, 1)," &
"316 (BC_1, ata_intrq, output3, 1, 315, 1, Pull0)," &
"317 (BC_1, ata_intrq, input, X)," &
"318 (BC_1, *, control, 1)," &
"319 (BC_1, timer_0, output3, 1, 318, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"320 (BC_1, timer_0, input, X)," &
"321 (BC_1, *, control, 1)," &
"322 (BC_1, i2c_1, output3, 1, 321, 1, Z)," &
"323 (BC_1, i2c_1, input, X)," &
"324 (BC_1, *, control, 1)," &
"325 (BC_1, i2c_3, output3, 1, 324, 1, Z)," &
"326 (BC_1, i2c_3, input, X)," &
"327 (BC_1, *, control, 1)," &
"328 (BC_1, timer_1, output3, 1, 327, 1, Z)," &
"329 (BC_1, timer_1, input, X)," &
"330 (BC_1, *, control, 1)," &
"331 (BC_1, i2c_0, output3, 1, 330, 1, Z)," &
"332 (BC_1, i2c_0, input, X)," &
"333 (BC_1, *, control, 1)," &
"334 (BC_1, i2c_2, output3, 1, 333, 1, Z)," &
"335 (BC_1, i2c_2, input, X)," &
"336 (BC_1, *, control, 1)," &
"337 (BC_1, mem_mdq_31, output3, 1, 336, 1, Z)," &
"338 (BC_1, mem_mdq_31, input, X)," &
"339 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"340 (BC_1, mem_mdq_1, output3, 1, 339, 1, Z)," &
"341 (BC_1, mem_mdq_1, input, X)," &
"342 (BC_1, *, control, 1)," &
"343 (BC_1, mem_mdq_0, output3, 1, 342, 1, Z)," &
"344 (BC_1, mem_mdq_0, input, X)," &
"345 (BC_1, *, control, 1)," &
"346 (BC_1, mem_mdq_30, output3, 1, 345, 1, Z)," &
"347 (BC_1, mem_mdq_30, input, X)," &
"348 (BC_1, *, control, 1)," &
"349 (BC_1, mem_mdq_3, output3, 1, 348, 1, Z)," &
"350 (BC_1, mem_mdq_3, input, X)," &
"351 (BC_1, *, control, 1)," &
"352 (BC_1, mem_mdq_2, output3, 1, 351, 1, Z)," &
"353 (BC_1, mem_mdq_2, input, X)," &
"354 (BC_1, *, control, 1)," &
"355 (BC_1, mem_mdq_28, output3, 1, 354, 1, Z)," &
"356 (BC_1, mem_mdq_28, input, X)," &
"357 (BC_1, *, control, 1)," &
"358 (BC_1, mem_mdq_29, output3, 1, 357, 1, Z)," &
"359 (BC_1, mem_mdq_29, input, X)," &
-- num cell port func safe [ccell dis rslt]
"360 (BC_1, *, control, 1)," &
"361 (BC_1, mem_mdq_5, output3, 1, 360, 1, Z)," &
"362 (BC_1, mem_mdq_5, input, X)," &
"363 (BC_1, *, control, 1)," &
"364 (BC_1, mem_mdq_4, output3, 1, 363, 1, Z)," &
"365 (BC_1, mem_mdq_4, input, X)," &
"366 (BC_1, *, control, 1)," &
"367 (BC_1, mem_mdq_27, output3, 1, 366, 1, Z)," &
"368 (BC_1, mem_mdq_27, input, X)," &
"369 (BC_1, *, control, 1)," &
"370 (BC_1, mem_mdq_7, output3, 1, 369, 1, Z)," &
"371 (BC_1, mem_mdq_7, input, X)," &
"372 (BC_1, *, control, 1)," &
"373 (BC_1, mem_mdq_6, output3, 1, 372, 1, Z)," &
"374 (BC_1, mem_mdq_6, input, X)," &
"375 (BC_1, *, control, 1)," &
"376 (BC_1, mem_mdq_25, output3, 1, 375, 1, Z)," &
"377 (BC_1, mem_mdq_25, input, X)," &
"378 (BC_1, *, control, 1)," &
"379 (BC_1, mem_mdq_26, output3, 1, 378, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"380 (BC_1, mem_mdq_26, input, X)," &
"381 (BC_1, *, control, 1)," &
"382 (BC_1, mem_dqm_0, output3, 1, 381, 1, Z)," &
"383 (BC_1, mem_dqm_0, input, X)," &
"384 (BC_1, *, control, 1)," &
"385 (BC_1, mem_mdqs_0, output3, 1, 384, 1, Z)," &
"386 (BC_1, mem_mdqs_0, input, X)," &
"387 (BC_1, *, control, 1)," &
"388 (BC_1, mem_mdq_24, output3, 1, 387, 1, Z)," &
"389 (BC_1, mem_mdq_24, input, X)," &
"390 (BC_1, *, control, 1)," &
"391 (BC_1, mem_mdq_14, output3, 1, 390, 1, Z)," &
"392 (BC_1, mem_mdq_14, input, X)," &
"393 (BC_1, *, control, 1)," &
"394 (BC_1, mem_mdq_15, output3, 1, 393, 1, Z)," &
"395 (BC_1, mem_mdq_15, input, X)," &
"396 (BC_1, *, control, 1)," &
"397 (BC_1, mem_dqm_3, output3, 1, 396, 1, Z)," &
"398 (BC_1, mem_dqm_3, input, X)," &
"399 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"400 (BC_1, mem_mdqs_3, output3, 1, 399, 1, Z)," &
"401 (BC_1, mem_mdqs_3, input, X)," &
"402 (BC_1, *, control, 1)," &
"403 (BC_1, mem_mdq_12, output3, 1, 402, 1, Z)," &
"404 (BC_1, mem_mdq_12, input, X)," &
"405 (BC_1, *, control, 1)," &
"406 (BC_1, mem_mdq_13, output3, 1, 405, 1, Z)," &
"407 (BC_1, mem_mdq_13, input, X)," &
"408 (BC_1, *, control, 1)," &
"409 (BC_1, mem_mdq_23, output3, 1, 408, 1, Z)," &
"410 (BC_1, mem_mdq_23, input, X)," &
"411 (BC_1, *, control, 1)," &
"412 (BC_1, mem_mdq_10, output3, 1, 411, 1, Z)," &
"413 (BC_1, mem_mdq_10, input, X)," &
"414 (BC_1, *, control, 1)," &
"415 (BC_1, mem_mdq_11, output3, 1, 414, 1, Z)," &
"416 (BC_1, mem_mdq_11, input, X)," &
"417 (BC_1, *, control, 1)," &
"418 (BC_1, mem_mdq_22, output3, 1, 417, 1, Z)," &
"419 (BC_1, mem_mdq_22, input, X)," &
-- num cell port func safe [ccell dis rslt]
"420 (BC_1, *, control, 1)," &
"421 (BC_1, mem_mdq_21, output3, 1, 420, 1, Z)," &
"422 (BC_1, mem_mdq_21, input, X)," &
"423 (BC_1, *, control, 1)," &
"424 (BC_1, mem_mdq_8, output3, 1, 423, 1, Z)," &
"425 (BC_1, mem_mdq_8, input, X)," &
"426 (BC_1, *, control, 1)," &
"427 (BC_1, mem_mdq_9, output3, 1, 426, 1, Z)," &
"428 (BC_1, mem_mdq_9, input, X)," &
"429 (BC_1, *, control, 1)," &
"430 (BC_1, mem_mdq_20, output3, 1, 429, 1, Z)," &
"431 (BC_1, mem_mdq_20, input, X)," &
"432 (BC_1, *, control, 1)," &
"433 (BC_1, mem_dqm_1, output3, 1, 432, 1, Z)," &
"434 (BC_1, mem_dqm_1, input, X)," &
"435 (BC_1, *, control, 1)," &
"436 (BC_1, mem_mdqs_1, output3, 1, 435, 1, Z)," &
"437 (BC_1, mem_mdqs_1, input, X)," &
"438 (BC_1, *, control, 1)," &
"439 (BC_1, mem_mdq_18, output3, 1, 438, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"440 (BC_1, mem_mdq_18, input, X)," &
"441 (BC_1, *, control, 1)," &
"442 (BC_1, mem_mdq_19, output3, 1, 441, 1, Z)," &
"443 (BC_1, mem_mdq_19, input, X)," &
"444 (BC_1, *, control, 1)," &
"445 (BC_1, mem_clk, output3, 1, 444, 1, Z)," &
"446 (BC_1, mem_clk, input, X)," &
"447 (BC_1, *, control, 1)," &
"448 (BC_1, mem_clk_b, output3, 1, 447, 1, Z)," &
"449 (BC_1, mem_clk_b, input, X)," &
"450 (BC_1, *, control, 1)," &
"451 (BC_1, mem_mdq_17, output3, 1, 450, 1, Z)," &
"452 (BC_1, mem_mdq_17, input, X)," &
"453 (BC_1, *, control, 1)," &
"454 (BC_1, mem_ma_12, output3, 1, 453, 1, Z)," &
"455 (BC_1, mem_ma_12, input, X)," &
"456 (BC_1, *, control, 1)," &
"457 (BC_1, mem_clk_en, output3, 1, 456, 1, Z)," &
"458 (BC_1, mem_clk_en, input, X)," &
"459 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"460 (BC_1, mem_mdq_16, output3, 1, 459, 1, Z)," &
"461 (BC_1, mem_mdq_16, input, X)," &
"462 (BC_1, *, control, 1)," &
"463 (BC_1, mem_ma_9, output3, 1, 462, 1, Z)," &
"464 (BC_1, mem_ma_9, input, X)," &
"465 (BC_1, *, control, 1)," &
"466 (BC_1, mem_ma_11, output3, 1, 465, 1, Z)," &
"467 (BC_1, mem_ma_11, input, X)," &
"468 (BC_1, *, control, 1)," &
"469 (BC_1, mem_mdqs_2, output3, 1, 468, 1, Z)," &
"470 (BC_1, mem_mdqs_2, input, X)," &
"471 (BC_1, *, control, 1)," &
"472 (BC_1, mem_ma_7, output3, 1, 471, 1, Z)," &
"473 (BC_1, mem_ma_7, input, X)," &
"474 (BC_1, *, control, 1)," &
"475 (BC_1, mem_ma_8, output3, 1, 474, 1, Z)," &
"476 (BC_1, mem_ma_8, input, X)," &
"477 (BC_1, *, control, 1)," &
"478 (BC_1, mem_ma_6, output3, 1, 477, 1, Z)," &
"479 (BC_1, mem_ma_6, input, X)," &
-- num cell port func safe [ccell dis rslt]
"480 (BC_1, *, control, 1)," &
"481 (BC_1, mem_ma_5, output3, 1, 480, 1, Z)," &
"482 (BC_1, mem_ma_5, input, X)," &
"483 (BC_1, *, control, 1)," &
"484 (BC_1, mem_ma_4, output3, 1, 483, 1, Z)," &
"485 (BC_1, mem_ma_4, input, X)," &
"486 (BC_1, *, control, 1)," &
"487 (BC_1, mem_dqm_2, output3, 1, 486, 1, Z)," &
"488 (BC_1, mem_dqm_2, input, X)," &
"489 (BC_1, *, control, 1)," &
"490 (BC_1, mem_cas_b, output3, 1, 489, 1, Z)," &
"491 (BC_1, mem_cas_b, input, X)," &
"492 (BC_1, *, control, 1)," &
"493 (BC_1, mem_we_b, output3, 1, 492, 1, Z)," &
"494 (BC_1, mem_we_b, input, X)," &
"495 (BC_1, *, control, 1)," &
"496 (BC_1, mem_mba_0, output3, 1, 495, 1, Z)," &
"497 (BC_1, mem_mba_0, input, X)," &
"498 (BC_1, *, control, 1)," &
"499 (BC_1, mem_cs_0_b, output3, 1, 498, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"500 (BC_1, mem_cs_0_b, input, X)," &
"501 (BC_1, *, control, 1)," &
"502 (BC_1, mem_ras_b, output3, 1, 501, 1, Z)," &
"503 (BC_1, mem_ras_b, input, X)," &
"504 (BC_1, *, control, 1)," &
"505 (BC_1, mem_ma_0, output3, 1, 504, 1, Z)," &
"506 (BC_1, mem_ma_0, input, X)," &
"507 (BC_1, *, control, 1)," &
"508 (BC_1, mem_ma_10, output3, 1, 507, 1, Z)," &
"509 (BC_1, mem_ma_10, input, X)," &
"510 (BC_1, *, control, 1)," &
"511 (BC_1, mem_mba_1, output3, 1, 510, 1, Z)," &
"512 (BC_1, mem_mba_1, input, X)," &
"513 (BC_1, *, control, 1)," &
"514 (BC_1, mem_ma_3, output3, 1, 513, 1, Z)," &
"515 (BC_1, mem_ma_3, input, X)," &
"516 (BC_1, *, control, 1)," &
"517 (BC_1, mem_ma_2, output3, 1, 516, 1, Z)," &
"518 (BC_1, mem_ma_2, input, X)," &
"519 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"520 (BC_1, mem_ma_1, output3, 1, 519, 1, Z)," &
"521 (BC_1, mem_ma_1, input, X)," &
"522 (BC_1, *, control, 1)," &
"523 (BC_1, gpio_wkup_6, output3, 1, 522, 1, Pull1)," &
"524 (BC_1, gpio_wkup_6, input, X)," &
"525 (BC_1, *, control, 1)," &
"526 (BC_1, sys_pll_tpa, output3, 1, 525, 1, Z)," &
"527 (BC_1, sys_pll_tpa, input, X)," &
"528 (BC_1, *, control, 1)," &
"529 (BC_1, sreset_b, output3, 1, 528, 1, Z)," &
"530 (BC_1, sreset_b, input, X)," &
"531 (BC_1, *, control, 1)," &
"532 (BC_1, psc6_3, output3, 1, 531, 1, Z)," &
"533 (BC_1, psc6_3, input, X)," &
"534 (BC_1, *, control, 1)," &
"535 (BC_1, hreset_b, output3, 1, 534, 1, Z)," &
"536 (BC_1, hreset_b, input, X)," &
"537 (BC_1, *, internal, 0)," &
"538 (BC_1, *, internal, 0)," &
"539 (BC_1, porreset_b, input, X)," &
-- num cell port func safe [ccell dis rslt]
"540 (BC_1, *, control, 1)," &
"541 (BC_1, gpio_wkup_7, output3, 1, 540, 1, Z)," &
"542 (BC_1, gpio_wkup_7, input, X)," &
"543 (BC_1, *, control, 1)," &
"544 (BC_1, psc6_0, output3, 1, 543, 1, Z)," &
"545 (BC_1, psc6_0, input, X)," &
"546 (BC_1, *, control, 1)," &
"547 (BC_1, psc6_2, output3, 1, 546, 1, Z)," &
"548 (BC_1, psc6_2, input, X)," &
"549 (BC_1, *, control, 1)," &
"550 (BC_1, psc6_1, output3, 1, 549, 1, Z)," &
"551 (BC_1, psc6_1, input, X)," &
"552 (BC_1, *, control, 1)," &
"553 (BC_1, psc1_0, output3, 1, 552, 1, Z)," &
"554 (BC_1, psc1_0, input, X)," &
"555 (BC_1, *, control, 1)," &
"556 (BC_1, psc1_1, output3, 1, 555, 1, Z)," &
"557 (BC_1, psc1_1, input, X)," &
"558 (BC_1, *, control, 1)," &
"559 (BC_1, psc1_2, output3, 1, 558, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"560 (BC_1, psc1_2, input, X)," &
"561 (BC_1, *, control, 1)," &
"562 (BC_1, psc1_3, output3, 1, 561, 1, Z)," &
"563 (BC_1, psc1_3, input, X)," &
"564 (BC_1, *, control, 1)," &
"565 (BC_1, psc1_4, output3, 1, 564, 1, Z)," &
"566 (BC_1, psc1_4, input, X)," &
"567 (BC_1, *, control, 1)," &
"568 (BC_1, psc2_0, output3, 1, 567, 1, Z)," &
"569 (BC_1, psc2_0, input, X)," &
"570 (BC_1, *, control, 1)," &
"571 (BC_1, psc2_1, output3, 1, 570, 1, Z)," &
"572 (BC_1, psc2_1, input, X)," &
"573 (BC_1, *, control, 1)," &
"574 (BC_1, psc2_2, output3, 1, 573, 1, Z)," &
"575 (BC_1, psc2_2, input, X)," &
"576 (BC_1, *, control, 1)," &
"577 (BC_1, lp_oe, output3, 1, 576, 1, Z)," &
"578 (BC_1, lp_oe, input, X)," &
"579 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"580 (BC_1, psc2_3, output3, 1, 579, 1, Z)," &
"581 (BC_1, psc2_3, input, X)," &
"582 (BC_1, *, control, 1)," &
"583 (BC_1, psc2_4, output3, 1, 582, 1, Z)," &
"584 (BC_1, psc2_4, input, X)," &
"585 (BC_1, *, control, 1)," &
"586 (BC_1, psc3_0, output3, 1, 585, 1, Z)," &
"587 (BC_1, psc3_0, input, X)," &
"588 (BC_1, *, control, 1)," &
"589 (BC_1, psc3_1, output3, 1, 588, 1, Z)," &
"590 (BC_1, psc3_1, input, X)," &
"591 (BC_1, *, control, 1)," &
"592 (BC_1, psc3_2, output3, 1, 591, 1, Z)," &
"593 (BC_1, psc3_2, input, X)," &
"594 (BC_1, *, control, 1)," &
"595 (BC_1, psc3_3, output3, 1, 594, 1, Z)," &
"596 (BC_1, psc3_3, input, X)," &
"597 (BC_1, *, control, 1)," &
"598 (BC_1, psc3_4, output3, 1, 597, 1, Z)," &
"599 (BC_1, psc3_4, input, X)," &
-- num cell port func safe [ccell dis rslt]
"600 (BC_1, *, control, 1)," &
"601 (BC_1, psc3_5, output3, 1, 600, 1, Z)," &
"602 (BC_1, psc3_5, input, X)," &
"603 (BC_1, *, control, 1)," &
"604 (BC_1, psc3_6, output3, 1, 603, 1, Z)," &
"605 (BC_1, psc3_6, input, X)," &
"606 (BC_1, *, control, 1)," &
"607 (BC_1, psc3_7, output3, 1, 606, 1, Z)," &
"608 (BC_1, psc3_7, input, X)," &
"609 (BC_1, *, control, 1)," &
"610 (BC_1, psc3_8, output3, 1, 609, 1, Z)," &
"611 (BC_1, psc3_8, input, X)," &
"612 (BC_1, *, control, 1)," &
"613 (BC_1, psc3_9, output3, 1, 612, 1, Z)," &
"614 (BC_1, psc3_9, input, X)";
end MPC5200;
