BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: ASIC_TOP

-- *****************************************************************************

--   BSDL file for design LAN9513JZX

--   Created by Synopsys Version B-2008.09 (Aug 25, 2008)

--   Designer: 
--   Company:  

--   Date: Tue Nov  4 15:50:20 2008

-- *****************************************************************************


 entity asic_top is
   
-- This section identifies the default device package selected.
   
   generic (PHYSICAL_PIN_MAP: string:= "LAN9513JZX");
   
-- This section declares all the ports in the design.
   
   port ( 
          AUTOMDIX_EN : in       bit;
          CLK24_EN    : in       bit;
          EEDI        : in       bit;
          TCK         : in       bit;
          TDI         : in       bit;
          TMS         : in       bit;
          nRESET      : in       bit;
          nTRST       : in       bit;
          GPIO3       : inout    bit;
          GPIO4       : inout    bit;
          GPIO5       : inout    bit;
          GPIO6       : inout    bit;
          GPIO7       : inout    bit;
          PRTCTL2     : inout    bit;
          PRTCTL3     : inout    bit;
          PRTCTL4     : inout    bit;
          NC1         : inout    bit;
          VBUS_DET    : inout    bit;
          nFDX_LED    : inout    bit;
          nLNKA_LED   : inout    bit;
          nSPD_LED    : inout    bit;
          TDO         : out      bit;
          CLK24_OUT   : buffer   bit;
          EECLK       : buffer   bit;
          EECS        : buffer   bit;
          EEDO        : buffer   bit;
          EXRES       : linkage  bit;
          RXN         : linkage  bit;
          RXP         : linkage  bit;
          TEST1       : in  bit;
          TEST2       : in  bit;
          TEST3       : linkage  bit;
          TEST4       : in  bit;
          TXN         : linkage  bit;
          TXP         : linkage  bit;
          USBDM0      : linkage  bit;
          USBDM2      : linkage  bit;
          USBDM3      : linkage  bit;
          USBDM4      : linkage  bit;
          USBDP0      : linkage  bit;
          USBDP2      : linkage  bit;
          USBDP3      : linkage  bit;
          USBDP4      : linkage  bit;
          USBRBIAS    : linkage  bit;
          VDD18CORE   : linkage  bit_vector (1 to 2);
          VDD33A      : linkage  bit_vector (1 to 7);
          VDD33IO     : linkage  bit_vector (1 to 5);
          VDD18USBPLL : linkage  bit;
          NC          : linkage  bit_vector (1 to 2);
          XI          : linkage  bit;
          XO          : linkage  bit
   );
   
   use STD_1149_1_2001.all;
   
   attribute COMPONENT_CONFORMANCE of asic_top: entity is "STD_1149_1_2001";
   
   attribute PIN_MAP of asic_top: entity is PHYSICAL_PIN_MAP;
   
-- This section specifies the pin map for each port. This information is 
-- extracted from the port-to-pin map file that was read in using the 
-- "read_pin_map" command.
   
     constant LAN9513JZX: PIN_MAP_STRING := 
        "USBDM2      : 1," &
        "USBDP2      : 2," &
        "USBDM3      : 3," &
        "USBDP3      : 4," &
        "VDD33A      : (5,10,49,51,54,57,64)," &
        "USBDM4      : 6," & 	
        "USBDP4      : 7," & 	
        "NC          : (8,9)," & 	
        "VBUS_DET    : 11," &
        "nRESET      : 12," &
        "TEST1       : 13," &
        "PRTCTL2     : 14," &
        "VDD18CORE   : (15,38)," &
        "PRTCTL3     : 16," &
        "PRTCTL4     : 17," &
        "NC1         : 18," &
        "VDD33IO     : (19,27,33,39,46)," &
        "nFDX_LED    : 20," &
        "nLNKA_LED   : 21," &
        "nSPD_LED    : 22," &
        "EECLK       : 23," &
        "EECS        : 24," &
        "EEDO        : 25," &
        "EEDI        : 26," &
        "nTRST       : 28," &
        "TMS         : 29," &
        "TDI         : 30," &
        "TDO         : 31," &
        "TCK         : 32," &
        "TEST2       : 34," &
        "GPIO3       : 35," &
        "GPIO4       : 36," &
        "GPIO5       : 37," &
        "TEST3       : 40," &
        "AUTOMDIX_EN : 41," &
        "GPIO6       : 42," &
        "GPIO7       : 43," &
        "CLK24_EN    : 44," &
        "CLK24_OUT   : 45," &
        "TEST4       : 47," &
        "EXRES       : 50," &
        "RXP         : 52," &
        "RXN         : 53," &
        "TXP         : 55," &
        "TXN         : 56," &
        "USBDM0      : 58," &
        "USBDP0      : 59," &
        "XO          : 60," &
        "XI          : 61," &
        "VDD18USBPLL : 62," &
        "USBRBIAS    : 63";
   
-- This section specifies the TAP ports. For the TAP TCK port, the parameters in 
-- the brackets are:
--        First Field : Maximum  TCK frequency.
--        Second Field: Allowable states TCK may be stopped in.
   
   attribute TAP_SCAN_CLOCK of TCK  : signal is (2.500000e+07, BOTH);
   attribute TAP_SCAN_IN    of TDI  : signal is true;
   attribute TAP_SCAN_MODE  of TMS  : signal is true;
   attribute TAP_SCAN_OUT   of TDO  : signal is true;
   attribute TAP_SCAN_RESET of nTRST: signal is true;
   
-- Specifies the compliance enable patterns for the design. It lists a set of 
-- design ports and the values that they should be set to, in order to enable 
-- compliance to IEEE Std 1149.1
   
   attribute COMPLIANCE_PATTERNS of asic_top: entity is 
        "(TEST1, TEST2, TEST4) (000)";
   
-- Specifies the number of bits in the instruction register.
   
   attribute INSTRUCTION_LENGTH of asic_top: entity is 4;
   
-- Specifies the boundary-scan instructions implemented in the design and their 
-- opcodes.
   
   attribute INSTRUCTION_OPCODE of asic_top: entity is 
     "BYPASS  (1111)," &
     "EXTEST  (0001)," &
     "SAMPLE  (0100)," &
     "PRELOAD (0100)," &
     "HIGHZ   (0011)," &
     "IDCODE  (1010)";
   
-- Specifies the bit pattern that is loaded into the instruction register when 
-- the TAP controller passes through the Capture-IR state. The standard mandates 
-- that the two LSBs must be "01". The remaining bits are design specific.
   
   attribute INSTRUCTION_CAPTURE of asic_top: entity is "0001";
   
-- Specifies the bit pattern that is loaded into the DEVICE_ID register during 
-- the IDCODE instruction when the TAP controller passes through the Capture-DR 
-- state.
   
   attribute IDCODE_REGISTER of asic_top: entity is 
     "0001" &                  
 -- 4-bit version number
     "0000000000010001" &      
 -- 16-bit part number
     "01000100010" &           
 -- 11-bit identity of the manufacturer
     "1";                      
 -- Required by IEEE Std 1149.1
   
-- This section specifies the test data register placed between TDI and TDO for 
-- each implemented instruction.
   
   attribute REGISTER_ACCESS of asic_top: entity is 
        "BYPASS    (BYPASS, HIGHZ)," &
        "BOUNDARY  (EXTEST, SAMPLE, PRELOAD)," &
        "DEVICE_ID (IDCODE)";
   
-- Specifies the length of the boundary scan register.
   
   attribute BOUNDARY_LENGTH of asic_top: entity is 34;
   
-- The following list specifies the characteristics of each cell in the boundary 
-- scan register from TDI to TDO. The following is a description of the label 
-- fields:
--      num     : Is the cell number.
--      cell    : Is the cell type as defined by the standard.
--      port    : Is the design port name. Control cells do not have a port 
--                name.
--      function: Is the function of the cell as defined by the standard. Is one 
--                of input, output2, output3, bidir, control or controlr.
--      safe    : Specifies the value that the BSR cell should be loaded with 
--                for safe operation when the software might otherwise choose a 
--                random value.
--      ccell   : The control cell number. Specifies the control cell that 
--                drives the output enable for this port.
--      disval  : Specifies the value that is loaded into the control cell to 
--                disable the output enable for the corresponding port.
--      rslt    : Resulting state. Shows the state of the driver when it is 
--                disabled.
   
   attribute BOUNDARY_REGISTER of asic_top: entity is 
--     
--    num   cell   port         function      safe  [ccell  disval  rslt]
--     
     "33   (BC_2,  *,           control,      1),                        " &
     "32   (BC_7,  VBUS_DET,    bidir,        X,    33,     1,      Z),  " &
     "31   (BC_2,  *,           control,      1),                        " &
     "30   (BC_7,  PRTCTL2,     bidir,        X,    31,     1,      Z),  " &
     "29   (BC_2,  *,           control,      1),                        " &
     "28   (BC_7,  PRTCTL3,     bidir,        X,    29,     1,      Z),  " &
     "27   (BC_2,  *,           control,      1),                        " &
     "26   (BC_7,  PRTCTL4,     bidir,        X,    27,     1,      Z),  " &
     "25   (BC_2,  *,           control,      1),                        " &
     "24   (BC_7,  NC1,         bidir,        X,    25,     1,      Z),  " &
     "23   (BC_2,  *,           control,      1),                        " &
     "22   (BC_7,  nFDX_LED,    bidir,        X,    23,     1,      Z),  " &
     "21   (BC_2,  *,           control,      1),                        " &
     "20   (BC_7,  nLNKA_LED,   bidir,        X,    21,     1,      Z),  " &
     "19   (BC_2,  *,           control,      1),                        " &
     "18   (BC_7,  nSPD_LED,    bidir,        X,    19,     1,      Z),  " &
     "17   (BC_1,  EECLK,       output2,      X),                        " &
     "16   (BC_1,  EECS,        output2,      X),                        " &
     "15   (BC_1,  EEDO,        output2,      X),                        " &
     "14   (BC_2,  EEDI,        input,        X),                        " &
     "13   (BC_2,  nRESET,      input,        X),                        " &
     "12   (BC_2,  *,           control,      1),                        " &
     "11   (BC_7,  GPIO3,       bidir,        X,    12,     1,      Z),  " &
     "10   (BC_2,  *,           control,      1),                        " &
     "9    (BC_7,  GPIO4,       bidir,        X,    10,     1,      Z),  " &
     "8    (BC_2,  *,           control,      1),                        " &
     "7    (BC_7,  GPIO5,       bidir,        X,    8,      1,      Z),  " &
     "6    (BC_2,  AUTOMDIX_EN, input,        X),                        " &
     "5    (BC_2,  *,           control,      1),                        " &
     "4    (BC_7,  GPIO6,       bidir,        X,    5,      1,      Z),  " &
     "3    (BC_2,  *,           control,      1),                        " &
     "2    (BC_7,  GPIO7,       bidir,        X,    3,      1,      Z),  " &
     "1    (BC_2,  CLK24_EN,    input,        X),                        " &
     "0    (BC_1,  CLK24_OUT,   output2,      X)                         ";
 
 end asic_top;