-- *********************************************************************
-- * *
-- * ispLSI2032VL 49 pin BGA BSDL Model *
-- * copyright 1996-1999, Lattice Semiconductor Corporation *
-- * IEEE 1149.1b-1994 *
-- * Standard Test Access Port and Boundary-Scan Architecture *
-- * VHDL Description File *
-- * *
-- * Date: Jul 15 1999 *
-- * File Version: v2.0-00 *
-- * *
-- * This BSDL file has been syntaxed checked with: *
-- * - Teradyne VICTORY *
-- * - Assett Intertech *
-- * *
-- *********************************************************************
-- * *
-- * E2CMOS, GAL, ispGAL, pDS, pLSI, Silicon Forest and UltraMOS are *
-- * registered trademarks of Lattice Semiconductor Corporation *
-- * *
-- * Generic Array Logic, ISP, ispCODE, ispDOWNLOAD, ispGDS, ispLSI *
-- * ispSTREAM, Latch-Lock, pDS+ and RFT are trademarks of Lattice *
-- * Semiconductor Corporation. *
-- * *
-- *********************************************************************
-- * *
-- * IMPORTANT *
-- * *
-- * The following is a BSDL file that tests all of the I/O pins *
-- * as bidirectional pins. The functionality of the BSCAN register *
-- * for this device is independent of the pattern programmed *
-- * into the device. An addtional programming step is not *
-- * required to configure the I/O pins prior to BSCAN test. *
-- * *
-- *********************************************************************
-- The Overall Structute of the Entity Description
entity ispLSI2032VL is
-- Generic Parameter Statement
generic (PHYSICAL_PIN_MAP : string := "BGA_49");
-- Logical Port Description Statement
port ( TDI: in bit; -- JTAG input pin
TMS: in bit; -- JTAG input pin
TCK: in bit; -- JTAG input pin
TDO: out bit; -- JTAG output pin
ispEN: linkage bit; -- ispEN pin
RESET: in bit; -- Active low RESET pin
GOE: in bit; -- Global Output Enable
Clk: in bit; -- Clock input pin
NoC: linkage bit_vector (0 to 4); -- No connect pins
BIp: inout bit_vector (0 to 31); -- Bi-Directional pins
VCC: linkage bit_vector (0 to 1); -- VCC pins
GND: linkage bit_vector (0 to 1) -- GND pins
);
-- Version Control
use STD_1149_1_1994.all; -- 1149.1-1994 attributes
-- Component Conformance Statement
attribute COMPONENT_CONFORMANCE of ispLSI2032VL : entity is
"STD_1149_1_1993";
-- Device Pacakge Pin Mapping
attribute PIN_MAP of ispLSI2032VL : entity is PHYSICAL_PIN_MAP;
constant BGA_49: PIN_MAP_STRING:=
"TDI:E2," & -- JTAG (TDI) input pin
"TMS:C6," & -- JTAG (TMS) input pin
"TCK:E7," & -- JTAG (TCK) input pin
"TDO:G4," & -- JTAG (TDO) output pin
"RESET:D7," & -- RESET input pin
"ispEN:D1," & -- ispEN control pin
"GOE:A4," & -- Global OE pin
"Clk:C1," & -- Clock pin
"NoC:( A1, A7, D4, G1, G7), " & -- No Connect pins
"BIp:( E1, F2, F1, E3, F3, G2, F4, " & -- I/O pins
" G3, F5, G5, F6, G6, E5, E6, " & -- I/O pins
" F7, D6, C7, B6, B7, C5, B5, " & -- I/O pins
" A6, B4, A5, B3, A3, B2, A2, " & -- I/O pins
" C3, C2, B1, D2), " & -- I/O pins
"VCC:( D3, D5), " & -- VCC pins
"GND:( C4, E4) " ; -- GND pins
-- Scan Port Identification
attribute TAP_SCAN_CLOCK of TCK : Signal is (5.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : Signal is True;
attribute TAP_SCAN_OUT of TDO : Signal is True;
attribute TAP_SCAN_MODE of TMS : Signal is True;
-- Instruction Register Description
attribute INSTRUCTION_LENGTH of ispLSI2032VL : entity is 5;
attribute INSTRUCTION_OPCODE of ispLSI2032VL : entity is
"BYPASS (11111), " &
"SAMPLE (11100), " &
"EXTEST (00000), " &
"IDCODE (10110), " &
"USERCODE (10111), " &
"HIGHZ (11000), " &
"ADDSHFT (00001), " &
"DATASHFT (00010), " &
"UBE (10000), " &
"PRGM (00111), " &
"VFY (10010), " &
"PRGMSC (01001), " &
"PRIVATE (00011,00100,00101,00110,01000,01010, " &
"01011,01100,01110,01111,10001,10011, " &
"10100,10101,11001,11010,11011,11101, " &
"11110)" ;
attribute INSTRUCTION_CAPTURE of ispLSI2032VL : entity is "11001";
attribute INSTRUCTION_PRIVATE of ispLSI2032VL : entity is "PRIVATE";
-- IDCODE Defintion
attribute IDCODE_REGISTER of ispLSI2032VL: entity is
"0001" & -- version
"0000001100000001" & -- part number (0301)
"00000100001" & -- manufacturer's identity
"1" ; -- required by 1149.1
-- USERCODE Defintion
attribute USERCODE_REGISTER of ispLSI2032VL: entity is
"11111111111111111111111111111111";
-- Register Access Description
attribute REGISTER_ACCESS of ispLSI2032VL : entity is
"BOUNDARY (SAMPLE, EXTEST), " &
"BYPASS (BYPASS, HIGHZ), " &
"ADDREG[102] (ADDSHFT), " &
"DATAREG[80] (DATASHFT), " &
"UBEREG[1] (UBE), " &
"PRGREG[102] (PRGM), " &
"VFYREG[80] (VFY), " &
"SECREG[1] (PRGMSC) " ;
-- **********************************************************************
-- Boundary Scan Register Description, Cell 0 is the closest to TDO
-- **********************************************************************
attribute BOUNDARY_LENGTH of ispLSI2032VL : entity is 102;
attribute BOUNDARY_REGISTER of ispLSI2032VL : entity is
-- num cell port function safe [ccell disval rslt]
"0101 (BC_1, *, internal, x)," &
"0100 (BC_1, *, internal, x)," &
"0099 (BC_1, Clk, input, x)," &
"0098 (BC_1, RESET, input, x)," &
"0097 (BC_1, *, internal, x)," &
"0096 (BC_1, GOE, input, x)," &
"0095 (BC_1, *, control, 0)," &
"0094 (BC_1, BIp(12), output3, x, 95, 0, z)," &
"0093 (BC_1, BIp(12), input, x)," &
"0092 (BC_1, *, control, 0)," &
"0091 (BC_1, BIp(13), output3, x, 92, 0, z)," &
"0090 (BC_1, BIp(13), input, x)," &
"0089 (BC_1, *, control, 0)," &
"0088 (BC_1, BIp(14), output3, x, 89, 0, z)," &
"0087 (BC_1, BIp(14), input, x)," &
"0086 (BC_1, *, control, 0)," &
"0085 (BC_1, BIp(15), output3, x, 86, 0, z)," &
"0084 (BC_1, BIp(15), input, x)," &
"0083 (BC_1, *, control, 0)," &
"0082 (BC_1, BIp(8), output3, x, 83, 0, z)," &
"0081 (BC_1, BIp(8), input, x)," &
"0080 (BC_1, *, control, 0)," &
"0079 (BC_1, BIp(9), output3, x, 80, 0, z)," &
"0078 (BC_1, BIp(9), input, x)," &
"0077 (BC_1, *, control, 0)," &
"0076 (BC_1, BIp(10), output3, x, 77, 0, z)," &
"0075 (BC_1, BIp(10), input, x)," &
"0074 (BC_1, *, control, 0)," &
"0073 (BC_1, BIp(11), output3, x, 74, 0, z)," &
"0072 (BC_1, BIp(11), input, x)," &
"0071 (BC_1, *, control, 0)," &
"0070 (BC_1, BIp(4), output3, x, 71, 0, z)," &
"0069 (BC_1, BIp(4), input, x)," &
"0068 (BC_1, *, control, 0)," &
"0067 (BC_1, BIp(5), output3, x, 68, 0, z)," &
"0066 (BC_1, BIp(5), input, x)," &
"0065 (BC_1, *, control, 0)," &
"0064 (BC_1, BIp(6), output3, x, 65, 0, z)," &
"0063 (BC_1, BIp(6), input, x)," &
"0062 (BC_1, *, control, 0)," &
"0061 (BC_1, BIp(7), output3, x, 62, 0, z)," &
"0060 (BC_1, BIp(7), input, x)," &
"0059 (BC_1, *, control, 0)," &
"0058 (BC_1, BIp(0), output3, x, 59, 0, z)," &
"0057 (BC_1, BIp(0), input, x)," &
"0056 (BC_1, *, control, 0)," &
"0055 (BC_1, BIp(1), output3, x, 56, 0, z)," &
"0054 (BC_1, BIp(1), input, x)," &
"0053 (BC_1, *, control, 0)," &
"0052 (BC_1, BIp(2), output3, x, 53, 0, z)," &
"0051 (BC_1, BIp(2), input, x)," &
"0050 (BC_1, *, control, 0)," &
"0049 (BC_1, BIp(3), output3, x, 50, 0, z)," &
"0048 (BC_1, BIp(3), input, x)," &
"0047 (BC_1, *, control, 0)," &
"0046 (BC_1, BIp(16), output3, x, 47, 0, z)," &
"0045 (BC_1, BIp(16), input, x)," &
"0044 (BC_1, *, control, 0)," &
"0043 (BC_1, BIp(17), output3, x, 44, 0, z)," &
"0042 (BC_1, BIp(17), input, x)," &
"0041 (BC_1, *, control, 0)," &
"0040 (BC_1, BIp(18), output3, x, 41, 0, z)," &
"0039 (BC_1, BIp(18), input, x)," &
"0038 (BC_1, *, control, 0)," &
"0037 (BC_1, BIp(19), output3, x, 38, 0, z)," &
"0036 (BC_1, BIp(19), input, x)," &
"0035 (BC_1, *, control, 0)," &
"0034 (BC_1, BIp(20), output3, x, 35, 0, z)," &
"0033 (BC_1, BIp(20), input, x)," &
"0032 (BC_1, *, control, 0)," &
"0031 (BC_1, BIp(21), output3, x, 32, 0, z)," &
"0030 (BC_1, BIp(21), input, x)," &
"0029 (BC_1, *, control, 0)," &
"0028 (BC_1, BIp(22), output3, x, 29, 0, z)," &
"0027 (BC_1, BIp(22), input, x)," &
"0026 (BC_1, *, control, 0)," &
"0025 (BC_1, BIp(23), output3, x, 26, 0, z)," &
"0024 (BC_1, BIp(23), input, x)," &
"0023 (BC_1, *, control, 0)," &
"0022 (BC_1, BIp(24), output3, x, 23, 0, z)," &
"0021 (BC_1, BIp(24), input, x)," &
"0020 (BC_1, *, control, 0)," &
"0019 (BC_1, BIp(25), output3, x, 20, 0, z)," &
"0018 (BC_1, BIp(25), input, x)," &
"0017 (BC_1, *, control, 0)," &
"0016 (BC_1, BIp(26), output3, x, 17, 0, z)," &
"0015 (BC_1, BIp(26), input, x)," &
"0014 (BC_1, *, control, 0)," &
"0013 (BC_1, BIp(27), output3, x, 14, 0, z)," &
"0012 (BC_1, BIp(27), input, x)," &
"0011 (BC_1, *, control, 0)," &
"0010 (BC_1, BIp(28), output3, x, 11, 0, z)," &
"0009 (BC_1, BIp(28), input, x)," &
"0008 (BC_1, *, control, 0)," &
"0007 (BC_1, BIp(29), output3, x, 8, 0, z)," &
"0006 (BC_1, BIp(29), input, x)," &
"0005 (BC_1, *, control, 0)," &
"0004 (BC_1, BIp(30), output3, x, 5, 0, z)," &
"0003 (BC_1, BIp(30), input, x)," &
"0002 (BC_1, *, control, 0)," &
"0001 (BC_1, BIp(31), output3, x, 2, 0, z)," &
"0000 (BC_1, BIp(31), input, x)";
end ispLSI2032VL;