BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: CY7C1332V25_119

--*******************************************************************************************************
--**  Copyright (c) 2000 Cypress Semiconductor
--**  All rights reserved.
--**                            
--**  File Name:     1332V25_x18_119.bsdl
--**  Release:       1.0			
--**  Last Updated:  June 3,2005			      
--**   
--**  Function:      1M x 18 Sync Flow Through SRAM, BSDL file for JTAG
--**  Part #:        CY7C1332V25
--**  Simulator:     Agilent Server
--**Notes:    IMPORTANT NOTE: Please be aware that the CY7C1461AV25 device is     --** NOT fully IEEE 1149.1 compliant.
--**                Ref CY7C1332V25 Datasheet at www.cypress.com
--** Queries ? :contact Cypress MPD Applications
--** Written by : Cypress MPD Applications
--*******************************************************************************************************
entity CY7C1332V25_119 is
      generic (PHYSICAL_PIN_MAP : string := "BGA");

       port  (
       A:      in    bit_vector(0 to 19);
      BWS_A_b: in    bit;
      BWS_B_b: in    bit;
      WE_b:    in    bit;
      CE_b:    in    bit;
      DQ_A:    in    bit_vector(0 to 8);
      DQ_B:    in    bit_vector(0 to 8);
      K:       in    bit;
      K_b:     in    bit;
      OE_b:    in    bit;
      M1:      in    bit;
      M2:      in    bit;
      TMS:     in    bit;
      TDI:     in    bit;
      TCK:     in    bit;
      TDO:     out   bit;
      ZZ:      in    bit;
      ZQ:      in    bit; 
      VREF:	   linkage bit_vector(0 to 1);
      VDD:     linkage bit_vector(0 to 4);
      VSS:     linkage bit_vector(0 to 15);
      VDDQ:    linkage bit_vector(0 to 9);
      NC:      linkage bit_vector(0 to 32)
             );

      use STD_1149_1_1994.all;
      
      attribute COMPONENT_CONFORMANCE of CY7C1332V25_119 : entity is
"STD_1149_1_1993";

      attribute PIN_MAP of CY7C1332V25_119 : entity is PHYSICAL_PIN_MAP;

      constant BGA : PIN_MAP_STRING:=
    "A:(N4,P4,T6,R6,T5,A6,C6,C5,A5,B6,B5,B3,B2, " &
    " A3,C3,C2,A2,T3,R2,T2), " & -- Address
    "BWS_A_b: L5, " &
    "BWS_B_b: G3, " &                         
    "WE_b:    M4, " &  -- Write Enable
    "CE_b:    E4, " &
    "K:       K4, " &-- Input positive Clock
    "K_b:     L4, " &-- Input negative Clock

    "DQ_A:   (P7,N6,L6,K7,H6,G7,F6,E7,D6), " &
    "DQ_B:   (D1,E2,G2,H1,K2,L1,M2,N1,P2), " &
    "OE_b:   F4, " &
    "M1:     R3, " &
    "M2:     R5, " &
    "TMS:    U2, " &
    "TDI:    U3, " &
    "TCK:    U4, " &
    "TDO:    U5, " &
    "VDD:    (C4,J2,J4,J6,R4), " &
    "VDDQ:   (A1,A7,F1,F7,J1,J7,M1,M7,U1,U7), " &
    "VSS:    (D3,D5,E3,E5,F3,F5,H3,H5,K3,K5, " &
    "M3,M5,N3,N5,P3,P5), " &
    "VREF:(J3,J5), " &--Input Voltage Reference 
    "ZZ:T7, " &
    "ZQ:D4, " &
    "NC:(A4,B1,B4,B7,C1,C7,D2,D7,E1,E6,F2,G1,G4,G5,G6, " &
    "H2,H4,H7,K1,K6,L2,L3,L7,M6,N2,N7,P1,P6, " &
    "R1,R7,T1,T4,U6)" ;

      attribute TAP_SCAN_IN    of TDI : signal is true;
      attribute TAP_SCAN_OUT   of TDO : signal is true;
      attribute TAP_SCAN_MODE  of TMS : signal is true;
      attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH);

      attribute INSTRUCTION_LENGTH of CY7C1332V25_119 : entity is 3;

      attribute INSTRUCTION_OPCODE of CY7C1332V25_119 : entity is
       "EXTEST      (000)," &
       "IDCODE      (001)," &
       "SAMPLE      (010)," &           -- Sample-Z
       "SAMPLD      (100)," &           -- Sample/Preload
       "BYPASS      (111) ";

      attribute INSTRUCTION_CAPTURE of CY7C1332V25_119: entity is "001";

      attribute IDCODE_REGISTER of CY7C1332V25_119 : entity is
      "000"  & -- Revision number
    "01011110101010101" & -- Device description
      "00000110100" & -- Manufacturer identity
      "1";  -- ID register Presence indicator


      attribute REGISTER_ACCESS of CY7C1332V25_119 : entity is
       "BOUNDARY    (EXTEST,SAMPLE,SAMPLD)," &
       "BYPASS      (BYPASS)";

      attribute BOUNDARY_LENGTH of CY7C1332V25_119 : entity is 51;
    attribute BOUNDARY_REGISTER of CY7C1332V25_119 : entity is
        "0     (BC_4, M2,       input,    X)," &
        "1     (BC_4, A(2),     input,    X)," &
        "2     (BC_4, A(1),     input,    X)," &
        "3     (BC_4, A(3),     input,    X)," &
        "4     (BC_4, A(4),     input,    X)," &
        "5     (BC_4, ZZ,       input,    X)," &
        "6     (BC_4, DQ_A(0),  input,    X)," &
        "7     (BC_4, DQ_A(1),  input,    X)," &
        "8     (BC_4, DQ_A(2),  input,    X)," &
        "9     (BC_4, DQ_A(3),  input,    X)," &
        "10    (BC_4, BWS_A_b,  input,    X)," &
        "11    (BC_4, K_b,      input,    X)," &
        "12    (BC_4, K,        input,    X)," &
        "13    (BC_4, OE_b,     input,    X)," &
        "14    (BC_4, DQ_A(4),  input,    X)," &
        "15    (BC_4, DQ_A(5),  input,    X)," &
        "16    (BC_4, DQ_A(6),  input,    X)," &  
        "17    (BC_4, DQ_A(7),  input,    X)," &
        "18    (BC_4, DQ_A(8),  input,    X)," &
        "19    (BC_4, A(5),     input,    X)," &
        "20    (BC_4, A(6),     input,    X)," &
        "21    (BC_4, A(7),     input,    X)," &
        "22    (BC_4, A(8),     input,    X)," &
        "23    (BC_4, A(9),     input,    X)," &
        "24    (BC_4, A(10),    input,    X)," &
        "25    (BC_4, A(11),    input,    X)," &
        "26    (BC_4, A(12),    input,    X)," &
        "27    (BC_4, A(13),    input,    X)," &
        "28    (BC_4, A(14),    input,    X)," &
        "29    (BC_4, A(15),    input,    X)," &
        "30    (BC_4, A(16),    input,    X)," &
        "31    (BC_4, DQ_B(0),  input,    X)," &
        "32    (BC_4, DQ_B(1),  input,    X)," &
        "33    (BC_4, DQ_B(2),  input,    X)," &
        "34    (BC_4, DQ_B(3),  input,    X)," &
        "35    (BC_4, BWS_B_b,  input,    X)," &
        "36    (BC_4, ZQ,       input,    X)," &
        "37    (BC_4, CE_b,     input,    X)," &
        "38    (BC_4, *,        internal,    X)," &
        "39    (BC_4, *,        internal,    X)," &
        "40    (BC_4, WE_b,     input,    X)," &
        "41    (BC_4, DQ_B(4),  input,    X)," &
        "42    (BC_4, DQ_B(5),  input,    X)," &
        "43    (BC_4, DQ_B(6),  input,    X)," &
        "44    (BC_4, DQ_B(7),  input,    X)," &
        "45    (BC_4, DQ_B(8),  input,    X)," &
        "46    (BC_4, A(17),    input,    X)," &
        "47    (BC_4, A(18),    input,    X)," &
        "48    (BC_4, A(0),     input,    X)," &
        "49    (BC_4, A(19),    input,    X)," &
        "50    (BC_4, M1,       input,    X)" ;
        
            

end CY7C1332V25_119;