-- bsdl file for ct612
-- mg73q011-181tc
-- 8/14/99
entity ct612 is
generic(physical_pin_map : string:= "lqfp176");
port (
nc : linkage bit_vector (1 to 21);
vddo : linkage bit_vector (1 to 23);
vsso : linkage bit_vector (1 to 23);
vddc : linkage bit_vector (1 to 4);
vssc : linkage bit_vector (1 to 4);
ale : in bit;
cs_n : in bit;
rd_n : in bit;
wr_n : in bit;
reset : in bit;
i_n : in bit;
int : inout bit;
d : inout bit_vector (7 downto 0);
a : in bit_vector (7 downto 0);
l_netref : in bit_vector (1 downto 0);
apll_vddo : linkage bit;
apll_vddc : linkage bit;
apll_pc : linkage bit;
apll_vco : linkage bit;
apll_vssc : linkage bit;
apll_vsso : linkage bit;
apll_clkref : in bit;
apll_test : in bit;
tms : in bit;
tck : in bit;
trst_n : in bit;
tdi : in bit;
tdo : out bit;
mc_txd : in bit;
mc_rxd : inout bit;
mc_clk : inout bit;
c16_neg_n : inout bit;
c16_pos_n : inout bit;
c4_n : inout bit;
c2 : inout bit;
sclkx2_n : inout bit;
sclk : inout bit;
fr_comp_n : inout bit;
ct_mc : inout bit;
ct_c8_b : inout bit;
ct_frame_b_n : inout bit;
ct_netref_2 : inout bit;
ct_netref_1 : inout bit;
ct_c8_a : inout bit;
ct_frame_a_n : inout bit;
ct_d : inout bit_vector (31 downto 0);
gpio : inout bit_vector (3 downto 0);
l_si : in bit_vector (1 downto 0);
l_so : inout bit_vector (1 downto 0);
l_clk_0 : inout bit;
l_fs_0 : inout bit;
l_clk_1 : inout bit;
l_fs_1 : inout bit;
ct_d_disable : inout bit;
test : in bit );
use std_1149_1_1994.all;
attribute component_conformance of ct612 : entity is "std_1149_1_1990";
attribute pin_map of ct612 : entity is physical_pin_map;
constant lqfp176:pin_map_string :=
"nc : ( 31, 32, 33, 37, 38, 40, 41 ,"&
" 42, 43,152,153,155,156,157 ,"&
" 158,162,163,165,166,167,168),"&
"vddo : ( 3, 11, 21, 34, 46, 61, 68, 74 ,"&
" 79, 84, 91, 97,101,107,112,117 ,"&
" 122,127,135,140,146,154,164 ),"&
"vsso : ( 7, 16, 26, 39, 53, 65, 71, 77 ,"&
" 81, 86, 94, 99,104,109,114,120 ,"&
" 124,130,137,143,149,159,169 ),"&
"vddc : ( 1, 45, 89,133),"&
"vssc : ( 44, 88,132,176),"&
"ale : 2,"&
"cs_n : 4,"&
"rd_n : 5,"&
"wr_n : 6,"&
"reset : 8,"&
"i_n : 9,"&
"int : 10,"&
"d : (29,27,24,22,19,17,14,12),"&
"a : (30,28,25,23,20,18,15,13),"&
"l_netref : (36,35),"&
"apll_vddo : 47,"&
"apll_vddc : 48,"&
"apll_pc : 49,"&
"apll_vco : 50,"&
"apll_vssc : 51,"&
"apll_vsso : 52,"&
"apll_clkref : 54,"&
"apll_test : 55,"&
"tms : 56,"&
"tck : 57,"&
"trst_n : 58,"&
"tdi : 59,"&
"tdo : 60,"&
"mc_txd : 62,"&
"mc_rxd : 63,"&
"mc_clk : 64,"&
"c16_neg_n : 66,"&
"c16_pos_n : 67,"&
"c4_n : 69,"&
"c2 : 70,"&
"sclkx2_n : 72,"&
"sclk : 73,"&
"fr_comp_n : 75,"&
"ct_mc : 76,"&
"ct_c8_b : 78,"&
"ct_frame_b_n : 80,"&
"ct_netref_2 : 82,"&
"ct_netref_1 : 83,"&
"ct_c8_a : 85,"&
"ct_frame_a_n : 87,"&
"ct_d : (142,141,139,138,136,134,131,129 ,"&
" 128,126,125,123,121,119,118,116 ,"&
" 115,113,111,110,108,106,105,103 ,"&
" 102,100, 98, 96, 95, 93, 92, 90),"&
"gpio : (148,147,145,144),"&
"l_si : (151,150),"&
"l_so : (161,160),"&
"l_clk_0 : 170,"&
"l_fs_0 : 171,"&
"l_clk_1 : 172,"&
"l_fs_1 : 173,"&
"ct_d_disable : 174,"&
"test : 175 ";
attribute tap_scan_clock of tck : signal is (10.0e6,both);
attribute tap_scan_in of tdi : signal is true;
attribute tap_scan_mode of tms : signal is true;
attribute tap_scan_out of tdo : signal is true;
attribute tap_scan_reset of trst_n : signal is true;
attribute instruction_length of ct612 : entity is 3;
attribute instruction_opcode of ct612 : entity is
"extest (000),"&
"idcode (001),"&
"sample (010),"&
"intest (100),"&
"highz (101),"&
"clamp (110),"&
"bypass (111) ";
attribute instruction_capture of ct612 : entity is "001";
attribute idcode_register of ct612 : entity is
"0000" & -- 4 bit version
"0000011011000000"& -- 16 bit part number
"00000101110" & -- 11 bit manufacturer
"1" ; -- 1 bit mandatory lsb
attribute register_access of ct612 : entity is
"boundary (extest, sample, intest),"&
"bypass (highz, clamp, bypass),"&
"device_id (idcode) ";
attribute boundary_length of ct612 : entity is 227;
attribute boundary_register of ct612 : entity is
-- num cell port function safe [ccell disval rslt]
"226 (bc_1, ale, input, x ),"&
"225 (bc_1, cs_n, input, x ),"&
"224 (bc_1, rd_n, input, x ),"&
"223 (bc_1, wr_n, input, x ),"&
"222 (bc_1, reset, input, x ),"&
"221 (bc_1, i_n, input, x ),"&
"220 (bc_1, int, input, x ),"&
"219 (bc_1, int, output3, x, 218, 0, z),"&
"218 (bc_1, *, control, 0 ),"&
"217 (bc_1, d(0), input, x ),"&
"216 (bc_1, d(0), output3, x, 215, 0, z),"&
"215 (bc_1, *, control, 0 ),"&
"214 (bc_1, a(0), input, x ),"&
"213 (bc_1, d(1), input, x ),"&
"212 (bc_1, d(1), output3, x, 211, 0, z),"&
"211 (bc_1, *, control, 0 ),"&
"210 (bc_1, a(1), input, x ),"&
"209 (bc_1, d(2), input, x ),"&
"208 (bc_1, d(2), output3, x, 207, 0, z),"&
"207 (bc_1, *, control, 0 ),"&
"206 (bc_1, a(2), input, x ),"&
"205 (bc_1, d(3), input, x ),"&
"204 (bc_1, d(3), output3, x, 203, 0, z),"&
"203 (bc_1, *, control, 0 ),"&
"202 (bc_1, a(3), input, x ),"&
"201 (bc_1, d(4), input, x ),"&
"200 (bc_1, d(4), output3, x, 199, 0, z),"&
"199 (bc_1, *, control, 0 ),"&
"198 (bc_1, a(4), input, x ),"&
"197 (bc_1, d(5), input, x ),"&
"196 (bc_1, d(5), output3, x, 195, 0, z),"&
"195 (bc_1, *, control, 0 ),"&
"194 (bc_1, a(5), input, x ),"&
"193 (bc_1, d(6), input, x ),"&
"192 (bc_1, d(6), output3, x, 191, 0, z),"&
"191 (bc_1, *, control, 0 ),"&
"190 (bc_1, a(6), input, x ),"&
"189 (bc_1, d(7), input, x ),"&
"188 (bc_1, d(7), output3, x, 187, 0, z),"&
"187 (bc_1, *, control, 0 ),"&
"186 (bc_1, a(7), input, x ),"&
"185 (bc_1, l_netref(0), input, x ),"&
"184 (bc_1, l_netref(1), input, x ),"&
"183 (bc_1, apll_clkref, input, x ),"&
"182 (bc_1, apll_test, input, x ),"&
"181 (bc_1, mc_txd, input, x ),"&
"180 (bc_1, mc_rxd, input, x ),"&
"179 (bc_1, mc_rxd, output3, x, 178, 0, z),"&
"178 (bc_1, *, control, 0 ),"&
"177 (bc_1, mc_clk, input, x ),"&
"176 (bc_1, mc_clk, output3, x, 175, 0, z),"&
"175 (bc_1, *, control, 0 ),"&
"174 (bc_1, c16_neg_n, input, x ),"&
"173 (bc_1, c16_neg_n, output3, x, 172, 0, z),"&
"172 (bc_1, *, control, 0 ),"&
"171 (bc_1, c16_pos_n, input, x ),"&
"170 (bc_1, c16_pos_n, output3, x, 169, 0, z),"&
"169 (bc_1, *, control, 0 ),"&
"168 (bc_1, c4_n, input, x ),"&
"167 (bc_1, c4_n, output3, x, 166, 0, z),"&
"166 (bc_1, *, control, 0 ),"&
"165 (bc_1, c2, input, x ),"&
"164 (bc_1, c2, output3, x, 163, 0, z),"&
"163 (bc_1, *, control, 0 ),"&
"162 (bc_1, sclkx2_n, input, x ),"&
"161 (bc_1, sclkx2_n, output3, x, 160, 0, z),"&
"160 (bc_1, *, control, 0 ),"&
"159 (bc_1, sclk, input, x ),"&
"158 (bc_1, sclk, output3, x, 157, 0, z),"&
"157 (bc_1, *, control, 0 ),"&
"156 (bc_1, fr_comp_n, input, x ),"&
"155 (bc_1, fr_comp_n, output3, x, 154, 0, z),"&
"154 (bc_1, *, control, 0 ),"&
"153 (bc_1, ct_mc, input, x ),"&
"152 (bc_1, ct_mc, output3, x, 151, 0, z),"&
"151 (bc_1, *, control, 0 ),"&
"150 (bc_1, ct_c8_b, input, x ),"&
"149 (bc_1, ct_c8_b, output3, x, 148, 0, z),"&
"148 (bc_1, *, control, 0 ),"&
"147 (bc_1, ct_frame_b_n, input, x ),"&
"146 (bc_1, ct_frame_b_n, output3, x, 145, 0, z),"&
"145 (bc_1, *, control, 0 ),"&
"144 (bc_1, ct_netref_2, input, x ),"&
"143 (bc_1, ct_netref_2, output3, x, 142, 0, z),"&
"142 (bc_1, *, control, 0 ),"&
"141 (bc_1, ct_netref_1, input, x ),"&
"140 (bc_1, ct_netref_1, output3, x, 139, 0, z),"&
"139 (bc_1, *, control, 0 ),"&
"138 (bc_1, ct_c8_a, input, x ),"&
"137 (bc_1, ct_c8_a, output3, x, 136, 0, z),"&
"136 (bc_1, *, control, 0 ),"&
"135 (bc_1, ct_frame_a_n, input, x ),"&
"134 (bc_1, ct_frame_a_n, output3, x, 133, 0, z),"&
"133 (bc_1, *, control, 0 ),"&
"132 (bc_1, ct_d(0), input, x ),"&
"131 (bc_1, ct_d(0), output3, x, 130, 0, z),"&
"130 (bc_1, *, control, 0 ),"&
"129 (bc_1, ct_d(1), input, x ),"&
"128 (bc_1, ct_d(1), output3, x, 127, 0, z),"&
"127 (bc_1, *, control, 0 ),"&
"126 (bc_1, ct_d(2), input, x ),"&
"125 (bc_1, ct_d(2), output3, x, 124, 0, z),"&
"124 (bc_1, *, control, 0 ),"&
"123 (bc_1, ct_d(3), input, x ),"&
"122 (bc_1, ct_d(3), output3, x, 121, 0, z),"&
"121 (bc_1, *, control, 0 ),"&
"120 (bc_1, ct_d(4), input, x ),"&
"119 (bc_1, ct_d(4), output3, x, 118, 0, z),"&
"118 (bc_1, *, control, 0 ),"&
"117 (bc_1, ct_d(5), input, x ),"&
"116 (bc_1, ct_d(5), output3, x, 115, 0, z),"&
"115 (bc_1, *, control, 0 ),"&
"114 (bc_1, ct_d(6), input, x ),"&
"113 (bc_1, ct_d(6), output3, x, 112, 0, z),"&
"112 (bc_1, *, control, 0 ),"&
"111 (bc_1, ct_d(7), input, x ),"&
"110 (bc_1, ct_d(7), output3, x, 109, 0, z),"&
"109 (bc_1, *, control, 0 ),"&
"108 (bc_1, ct_d(8), input, x ),"&
"107 (bc_1, ct_d(8), output3, x, 106, 0, z),"&
"106 (bc_1, *, control, 0 ),"&
"105 (bc_1, ct_d(9), input, x ),"&
"104 (bc_1, ct_d(9), output3, x, 103, 0, z),"&
"103 (bc_1, *, control, 0 ),"&
"102 (bc_1, ct_d(10), input, x ),"&
"101 (bc_1, ct_d(10), output3, x, 100, 0, z),"&
"100 (bc_1, *, control, 0 ),"&
" 99 (bc_1, ct_d(11), input, x ),"&
" 98 (bc_1, ct_d(11), output3, x, 97, 0, z),"&
" 97 (bc_1, *, control, 0 ),"&
" 96 (bc_1, ct_d(12), input, x ),"&
" 95 (bc_1, ct_d(12), output3, x, 94, 0, z),"&
" 94 (bc_1, *, control, 0 ),"&
" 93 (bc_1, ct_d(13), input, x ),"&
" 92 (bc_1, ct_d(13), output3, x, 91, 0, z),"&
" 91 (bc_1, *, control, 0 ),"&
" 90 (bc_1, ct_d(14), input, x ),"&
" 89 (bc_1, ct_d(14), output3, x, 88, 0, z),"&
" 88 (bc_1, *, control, 0 ),"&
" 87 (bc_1, ct_d(15), input, x ),"&
" 86 (bc_1, ct_d(15), output3, x, 85, 0, z),"&
" 85 (bc_1, *, control, 0 ),"&
" 84 (bc_1, ct_d(16), input, x ),"&
" 83 (bc_1, ct_d(16), output3, x, 82, 0, z),"&
" 82 (bc_1, *, control, 0 ),"&
" 81 (bc_1, ct_d(17), input, x ),"&
" 80 (bc_1, ct_d(17), output3, x, 79, 0, z),"&
" 79 (bc_1, *, control, 0 ),"&
" 78 (bc_1, ct_d(18), input, x ),"&
" 77 (bc_1, ct_d(18), output3, x, 76, 0, z),"&
" 76 (bc_1, *, control, 0 ),"&
" 75 (bc_1, ct_d(19), input, x ),"&
" 74 (bc_1, ct_d(19), output3, x, 73, 0, z),"&
" 73 (bc_1, *, control, 0 ),"&
" 72 (bc_1, ct_d(20), input, x ),"&
" 71 (bc_1, ct_d(20), output3, x, 70, 0, z),"&
" 70 (bc_1, *, control, 0 ),"&
" 69 (bc_1, ct_d(21), input, x ),"&
" 68 (bc_1, ct_d(21), output3, x, 67, 0, z),"&
" 67 (bc_1, *, control, 0 ),"&
" 66 (bc_1, ct_d(22), input, x ),"&
" 65 (bc_1, ct_d(22), output3, x, 64, 0, z),"&
" 64 (bc_1, *, control, 0 ),"&
" 63 (bc_1, ct_d(23), input, x ),"&
" 62 (bc_1, ct_d(23), output3, x, 61, 0, z),"&
" 61 (bc_1, *, control, 0 ),"&
" 60 (bc_1, ct_d(24), input, x ),"&
" 59 (bc_1, ct_d(24), output3, x, 58, 0, z),"&
" 58 (bc_1, *, control, 0 ),"&
" 57 (bc_1, ct_d(25), input, x ),"&
" 56 (bc_1, ct_d(25), output3, x, 55, 0, z),"&
" 55 (bc_1, *, control, 0 ),"&
" 54 (bc_1, ct_d(26), input, x ),"&
" 53 (bc_1, ct_d(26), output3, x, 52, 0, z),"&
" 52 (bc_1, *, control, 0 ),"&
" 51 (bc_1, ct_d(27), input, x ),"&
" 50 (bc_1, ct_d(27), output3, x, 49, 0, z),"&
" 49 (bc_1, *, control, 0 ),"&
" 48 (bc_1, ct_d(28), input, x ),"&
" 47 (bc_1, ct_d(28), output3, x, 46, 0, z),"&
" 46 (bc_1, *, control, 0 ),"&
" 45 (bc_1, ct_d(29), input, x ),"&
" 44 (bc_1, ct_d(29), output3, x, 43, 0, z),"&
" 43 (bc_1, *, control, 0 ),"&
" 42 (bc_1, ct_d(30), input, x ),"&
" 41 (bc_1, ct_d(30), output3, x, 40, 0, z),"&
" 40 (bc_1, *, control, 0 ),"&
" 39 (bc_1, ct_d(31), input, x ),"&
" 38 (bc_1, ct_d(31), output3, x, 37, 0, z),"&
" 37 (bc_1, *, control, 0 ),"&
" 36 (bc_1, gpio(0), input, x ),"&
" 35 (bc_1, gpio(0), output3, x, 34, 0, pull1),"&
" 34 (bc_1, *, control, 0 ),"&
" 33 (bc_1, gpio(1), input, x ),"&
" 32 (bc_1, gpio(1), output3, x, 31, 0, pull1),"&
" 31 (bc_1, *, control, 0 ),"&
" 30 (bc_1, gpio(2), input, x ),"&
" 29 (bc_1, gpio(2), output3, x, 28, 0, pull1),"&
" 28 (bc_1, *, control, 0 ),"&
" 27 (bc_1, gpio(3), input, x ),"&
" 26 (bc_1, gpio(3), output3, x, 25, 0, pull1),"&
" 25 (bc_1, *, control, 0 ),"&
" 24 (bc_1, l_si(0), input, x ),"&
" 23 (bc_1, l_si(1), input, x ),"&
" 22 (bc_1, l_so(0), input, x ),"&
" 21 (bc_1, l_so(0), output3, x, 20, 0, pull1),"&
" 20 (bc_1, *, control, 0 ),"&
" 19 (bc_1, l_so(1), input, x ),"&
" 18 (bc_1, l_so(1), output3, x, 17, 0, pull1),"&
" 17 (bc_1, *, control, 0 ),"&
" 16 (bc_1, l_clk_0, input, x ),"&
" 15 (bc_1, l_clk_0, output3, x, 14, 0, pull1),"&
" 14 (bc_1, *, control, 0 ),"&
" 13 (bc_1, l_fs_0, input, x ),"&
" 12 (bc_1, l_fs_0, output3, x, 11, 0, pull1),"&
" 11 (bc_1, *, control, 0 ),"&
" 10 (bc_1, l_clk_1, input, x ),"&
" 9 (bc_1, l_clk_1, output3, x, 8, 0, pull1),"&
" 8 (bc_1, *, control, 0 ),"&
" 7 (bc_1, l_fs_1, input, x ),"&
" 6 (bc_1, l_fs_1, output3, x, 5, 0, pull1),"&
" 5 (bc_1, *, control, 0 ),"&
" 4 (bc_1, ct_d_disable, input, x ),"&
" 3 (bc_1, ct_d_disable, output3, x, 2, 0, pull1),"&
" 2 (bc_1, *, control, 0 ),"&
" 1 (bc_1, test, input, x ),"&
" 0 (bc_1, *, internal, x ) ";
end ct612;
