-------------------------------------------------------------------------------
-- SA-110.bsdl
-- The BSDL Description for SA-110 IEEE 1149.1 Circuits
-- Validated by Corelis (562)926-6727, 08-APR-1999
-------------------------------------------------------------------------------
entity SA110 is -- (ref B.8)
generic (PHYSICAL_PIN_MAP: string:= "TQFP_144"); -- (ref B.8.2)
port( -- (ref B.8.3)
MSE :linkage bit;
ABE :linkage bit;
MCLK :linkage bit;
SNA :in bit;
CONFIG :in bit;
NMREQ :out bit;
NRW :out bit; -- line 15
SEQ :out bit;
CLF :out bit;
LOCK :out bit;
MCCFG :in bit_vector (2 downto 0);
CCCFG :in bit_vector (3 downto 0);
RSTOUT :out bit;
MAS :out bit_vector (1 downto 0);
A :out bit_vector (31 downto 0);
SPDF :in bit;
APE :in bit;
ABORT :in bit;
NMCLK :out bit;
NWAIT :in bit;
CLK :in bit;
TESTBYP :in bit;
TESTCLK :in bit;
NRESET :in bit;
FIQ :in bit;
IRQ :in bit;
D :inout bit_vector (31 downto 0);
DBE :in bit;
PWRSLP :linkage bit;
TRST :in bit;
TCK :in bit;
TDI :in bit;
TDO :out bit;
TMS :in bit;
VDD :linkage bit_vector(8 downto 0);
VSS :linkage bit_vector(7 downto 0);
VDDX :linkage bit_vector(9 downto 0);
VSSX :linkage bit_vector(9 downto 0);
NC :linkage bit_vector(4 downto 0)
) ;
use STD_1149_1_1994.all ; -- (ref B.8.4)
-- changed to 1990 for Teradyne Victory compiler -- "COMPILERSENSITIVE"
-- use STD_1149_1_1990.all ; -- "COMPILERSENSITIVE"
attribute COMPONENT_CONFORMANCE of SA110: entity is "STD_1149_1_1993"; -- (ref B.8.6)
attribute PIN_MAP of SA110 : entity is PHYSICAL_PIN_MAP ; -- (ref B.8.7)
constant TQFP_144 : PIN_MAP_STRING :=
"MSE: 56, " &
"CONFIG: 57, " &
"NMREQ: 58, " &
"SEQ: 59, " &
"CLF: 60, " &
"LOCK: 61, " &
"NRW: 62, " &
"SPDF: 65, " &
"MCCFG: (68, 67, 66), " &
"CCCFG: (70, 69, 138, 139), " &
"RSTOUT: 71, " &
"ABE: 72, " &
"MAS: (74, 73), " &
"A: (120, 119, 118, 117, 116, 115, 112, 111, 110, 109, " &
" 108, 107, 106, 101, 100, 99, 98, 97, 96, 95, " &
" 94, 89, 88, 87, 86, 85, 84, 83, 82, 77, " &
" 76, 75), " &
"APE: 121, " &
"ABORT: 122, " &
"MCLK: 123, " &
"NMCLK: 124, " &
"NWAIT: 127, " &
"CLK: 128, " &
"TESTBYP: 130, " &
"TESTCLK: 131, " &
"NRESET: 141, " &
"SNA: 142, " &
"FIQ: 143, " &
"IRQ: 144, " &
"D: ( 47, 46, 45, 44, 41, 40, 39, 38, 37, 35, " &
" 34, 33, 28, 27, 26, 25, 24, 23, 22, 21, " &
" 16, 15, 14, 13, 12, 11, 10, 9, 4, 3, " &
" 2, 1), " &
"DBE: 36, " &
"PWRSLP: 140, " &
"TRST: 50, " &
"TCK: 52, " &
"TDI: 49, " &
"TDO: 48, " &
"TMS: 51, " &
"VDD: ( 5, 20, 32, 55, 81, 90, 105, 129, 133), " &
"VSS: ( 6, 19, 31, 54, 80, 91, 104, 132), " &
"VDDX: ( 8, 17, 29, 43, 64, 78, 93, 102, 114, 126)," &
"VSSX: ( 7, 18, 30, 42, 63, 79, 92, 103, 113, 125)," &
"NC: ( 53, 134, 135, 136, 137)";
attribute TAP_SCAN_CLOCK of TCK : signal is (16.60e6, LOW); -- (Ref B.8.9)
attribute TAP_SCAN_IN of TDI : signal is TRUE;
attribute TAP_SCAN_OUT of TDO : signal is TRUE;
attribute TAP_SCAN_MODE of TMS : signal is TRUE;
attribute TAP_SCAN_RESET of TRST : signal is TRUE;
--attribute COMPLIANCE_PATTERNS of SA110 : entity is -- (Ref B.8.10)."COMPILERSENSITIVE"
-- "(PWRSLP), (1)" ; --comment out if unsupported by compiler
attribute INSTRUCTION_LENGTH of SA110 : entity is 5 ; -- (Ref B.8.11)
attribute INSTRUCTION_OPCODE of SA110 : entity is
"EXTEST (00000)," &
"SAMPLE (00001)," &
"CLAMP (00100)," &
"HIGHZ (00101)," &
"IDCODE (00110)," &
"BYPASS (11111)" ;
attribute INSTRUCTION_CAPTURE of SA110 : entity is "00001" ;
-- attribute INSTRUCTION_PRIVATE of SA110 : entity is "Private"; -- "COMPILERSENSITIVE" Comment out
-- if unsupported by the compile
-- ID Register Description
attribute IDCODE_REGISTER of SA110: entity is
"0011" & -- Version Changed from 0010 to 0011 10/7/97 RJW
"0001000000101100" & -- Part Number
"00000110101" & -- Manufacturer
"1"; -- Mandatory LSB
attribute REGISTER_ACCESS of SA110 : entity is -- (ref B.8.13)
"BOUNDARY (EXTEST, SAMPLE)," & -- Redundant. Added for completeness
"BYPASS (BYPASS, HIGHZ, CLAMP)"; -- ditto
-- "DIE_ID[32] (DIE_ID)";
attribute BOUNDARY_LENGTH of SA110 : entity is 130 ; -- (ref B.8.14)
attribute BOUNDARY_REGISTER of SA110 : entity is
------------------------------------------------------------------------------
-- scan cell cntr disable disable
-- cell type port function safe cell value state
------------------------------------------------------------------------------
"0 (BC_1, D(31), OUTPUT3, x, 19, 0, Z ), " &
"1 (BC_4, D(31), INPUT, x), " &
"2 (BC_1, D(30), OUTPUT3, x, 19, 0, Z ), " &
"3 (BC_4, D(30), INPUT, x), " &
"4 (BC_1, D(29), OUTPUT3, x, 19, 0, Z ), " &
"5 (BC_4, D(29), INPUT, x), " &
"6 (BC_1, D(28), OUTPUT3, x, 19, 0, Z ), " &
"7 (BC_4, D(28), INPUT, x), " &
"8 (BC_1, D(27), OUTPUT3, x, 19, 0, Z ), " &
"9 (BC_4, D(27), INPUT, x), " &
"10 (BC_1, D(26), OUTPUT3, x, 19, 0, Z ), " &
"11 (BC_4, D(26), INPUT, x), " &
"12 (BC_1, D(25), OUTPUT3, x, 19, 0, Z ), " &
"13 (BC_4, D(25), INPUT, x), " &
"14 (BC_1, D(24), OUTPUT3, x, 19, 0, Z ), " &
"15 (BC_4, D(24), INPUT, x), " &
"16 (BC_1, D(23), OUTPUT3, x, 19, 0, Z ), " &
"17 (BC_4, D(23), INPUT, x), " &
"18 (BC_4, DBE, INPUT, x), " &
"19 (BC_2, *, CONTROL, x), " & -- bc_7
"20 (BC_1, D(22), OUTPUT3, x, 19, 0, Z ), " &
"21 (BC_4, D(22), INPUT, x), " &
"22 (BC_1, D(21), OUTPUT3, x, 19, 0, Z ), " &
"23 (BC_4, D(21), INPUT, x), " &
"24 (BC_1, D(20), OUTPUT3, x, 19, 0, Z ), " &
"25 (BC_4, D(20), INPUT, x), " &
"26 (BC_1, D(19), OUTPUT3, x, 19, 0, Z ), " &
"27 (BC_4, D(19), INPUT, x), " &
"28 (BC_1, D(18), OUTPUT3, x, 19, 0, Z ), " &
"29 (BC_4, D(18), INPUT, x), " &
"30 (BC_1, D(17), OUTPUT3, x, 19, 0, Z ), " &
"31 (BC_4, D(17), INPUT, x), " &
"32 (BC_1, D(16), OUTPUT3, x, 19, 0, Z ), " &
"33 (BC_4, D(16), INPUT, x), " &
"34 (BC_1, D(15), OUTPUT3, x, 19, 0, Z ), " &
"35 (BC_4, D(15), INPUT, x), " &
"36 (BC_1, D(14), OUTPUT3, x, 19, 0, Z ), " &
"37 (BC_4, D(14), INPUT, x), " &
"38 (BC_1, D(13), OUTPUT3, x, 19, 0, Z ), " &
"39 (BC_4, D(13), INPUT, x), " &
"40 (BC_1, D(12), OUTPUT3, x, 19, 0, Z ), " &
"41 (BC_4, D(12), INPUT, x), " &
"42 (BC_1, D(11), OUTPUT3, x, 19, 0, Z ), " &
"43 (BC_4, D(11), INPUT, x), " &
"44 (BC_1, D(10), OUTPUT3, x, 19, 0, Z ), " &
"45 (BC_4, D(10), INPUT, x), " &
"46 (BC_1, D(9), OUTPUT3, x, 19, 0, Z ), " &
"47 (BC_4, D(9), INPUT, x), " &
"48 (BC_1, D(8), OUTPUT3, x, 19, 0, Z ), " &
"49 (BC_4, D(8), INPUT, x), " &
"50 (BC_1, D(7), OUTPUT3, x, 19, 0, Z ), " &
"51 (BC_4, D(7), INPUT, x), " &
"52 (BC_1, D(6), OUTPUT3, x, 19, 0, Z ), " &
"53 (BC_4, D(6), INPUT, x), " &
"54 (BC_1, D(5), OUTPUT3, x, 19, 0, Z ), " &
"55 (BC_4, D(5), INPUT, x), " &
"56 (BC_1, D(4), OUTPUT3, x, 19, 0, Z ), " &
"57 (BC_4, D(4), INPUT, x), " &
"58 (BC_1, D(3), OUTPUT3, x, 19, 0, Z ), " &
"59 (BC_4, D(3), INPUT, x), " &
"60 (BC_1, D(2), OUTPUT3, x, 19, 0, Z ), " &
"61 (BC_4, D(2), INPUT, x), " &
"62 (BC_1, D(1), OUTPUT3, x, 19, 0, Z ), " &
"63 (BC_4, D(1), INPUT, x), " &
"64 (BC_1, D(0), OUTPUT3, x, 19, 0, Z ), " &
"65 (BC_4, D(0), INPUT, x), " &
"66 (BC_4, IRQ, INPUT, x), " &
"67 (BC_4, FIQ, INPUT, x), " &
"68 (BC_4, SNA, INPUT, x), " &
"68 (BC_2, *, control, 1), " &
"69 (BC_4, NRESET, INPUT, x), " &
"70 (BC_4, CCCFG(0), INPUT, x), " &
"71 (BC_4, CCCFG(1), INPUT, x), " &
"72 (BC_4, TESTCLK, INPUT, x), " &
"73 (BC_4, TESTBYP, INPUT, x), " &
"74 (BC_4, CLK, INPUT, x), " &
"75 (BC_4, NWAIT, INPUT, x), " &
"76 (BC_1, NMCLK, OUTPUT3, x, 68, 0, Z ), " & -- was BC_4
"77 (BC_4, *, internal,x), " &
"78 (BC_4, *, internal,x), " &
"79 (BC_4, ABORT, INPUT, x), " &
"80 (BC_4, APE, INPUT, x), " &
"81 (BC_1, A(31), OUTPUT3, x, 115, 0, Z ), " &
"82 (BC_1, A(30), OUTPUT3, x, 115, 0, Z ), " &
"83 (BC_1, A(29), OUTPUT3, x, 115, 0, Z ), " &
"84 (BC_1, A(28), OUTPUT3, x, 115, 0, Z ), " &
"85 (BC_1, A(27), OUTPUT3, x, 115, 0, Z ), " &
"86 (BC_1, A(26), OUTPUT3, x, 115, 0, Z ), " &
"87 (BC_1, A(25), OUTPUT3, x, 115, 0, Z ), " &
"88 (BC_1, A(24), OUTPUT3, x, 115, 0, Z ), " &
"89 (BC_1, A(23), OUTPUT3, x, 115, 0, Z ), " &
"90 (BC_1, A(22), OUTPUT3, x, 115, 0, Z ), " &
"91 (BC_1, A(21), OUTPUT3, x, 115, 0, Z ), " &
"92 (BC_1, A(20), OUTPUT3, x, 115, 0, Z ), " &
"93 (BC_1, A(19), OUTPUT3, x, 115, 0, Z ), " &
"94 (BC_1, A(18), OUTPUT3, x, 115, 0, Z ), " &
"95 (BC_1, A(17), OUTPUT3, x, 115, 0, Z ), " &
"96 (BC_1, A(16), OUTPUT3, x, 115, 0, Z ), " &
"97 (BC_1, A(15), OUTPUT3, x, 115, 0, Z ), " &
"98 (BC_1, A(14), OUTPUT3, x, 115, 0, Z ), " &
"99 (BC_1, A(13), OUTPUT3, x, 115, 0, Z ), " &
"100 (BC_1, A(12), OUTPUT3, x, 115, 0, Z ), " &
"101 (BC_1, A(11), OUTPUT3, x, 115, 0, Z ), " &
"102 (BC_1, A(10), OUTPUT3, x, 115, 0, Z ), " &
"103 (BC_1, A(9), OUTPUT3, x, 115, 0, Z ), " &
"104 (BC_1, A(8), OUTPUT3, x, 115, 0, Z ), " &
"105 (BC_1, A(7), OUTPUT3, x, 115, 0, Z ), " &
"106 (BC_1, A(6), OUTPUT3, x, 115, 0, Z ), " &
"107 (BC_1, A(5), OUTPUT3, x, 115, 0, Z ), " &
"108 (BC_1, A(4), OUTPUT3, x, 115, 0, Z ), " &
"109 (BC_1, A(3), OUTPUT3, x, 115, 0, Z ), " &
"110 (BC_1, A(2), OUTPUT3, x, 115, 0, Z ), " &
"111 (BC_1, A(1), OUTPUT3, x, 115, 0, Z ), " &
"112 (BC_1, A(0), OUTPUT3, x, 115, 0, Z ), " &
"113 (BC_1, MAS(1), OUTPUT3, x, 115, 0, Z ), " &
"114 (BC_1, MAS(0), OUTPUT3, x, 115, 0, Z ), " &
"115 (BC_2, *, control, x), " &
"116 (BC_1, RSTOUT, OUTPUT2, x), " &
"117 (BC_4, CCCFG(3), INPUT, x), " &
"118 (BC_4, CCCFG(2), INPUT, x), " &
"119 (BC_4, MCCFG(2), INPUT, x), " &
"120 (BC_4, MCCFG(1), INPUT, x), " &
"121 (BC_4, MCCFG(0), INPUT, x), " &
"122 (BC_4, SPDF, INPUT, x), " &
"123 (BC_1, NRW, OUTPUT3, x, 115, 0, Z ), " &
"124 (BC_1, LOCK, OUTPUT3, x, 115, 0, Z ), " &
"125 (BC_1, CLF, OUTPUT3, x, 115, 0, Z ), " &
"126 (BC_1, SEQ, OUTPUT3, x, 129, 0, Z ), " &
"127 (BC_1, NMREQ, OUTPUT3, x, 129, 0, Z ), " &
"128 (BC_4, CONFIG, INPUT, x), " &
"129 (BC_2, *, control, x) " ;
------------------------------------------------------------------------------
-- scan cell port function safe cntrl disable disable
-- cell type cell value state
------------------------------------------------------------------------------
attribute DESIGN_WARNING of SA110: entity is -- (ref B.8.18)
" 1.IEEE 1149.1 circuits on SA110 are designed " &
" primarily to support testing in off-line module " &
" manufacturing environment. The SAMPLE/PRELOAD " &
" instruction support is designed primarily for " &
" supporting interconnection verification test and not " &
" for at-speed samples of pin data. " &
" 2.Ensure to drive PWRSLP to logic 1, or else the chip will sleep! " &
" 3.MCLK is on the BSR at cells 77 (input) and 78 (output), but " &
" the control cells for MCLK is not 1149.1 complient. Therefore " &
" this signal is best described as a linkage pin. However, be " &
" warned that MCLK will drive OUT whenever SNA is logic 1. " &
" If your design can not tolerate MCLK turning on when JTAG vectors " &
" are ran, you must constrain your JTAG pattern generator by keeping " &
" input SNA always logic 0. If your design ties SNA to Vss, then " &
" MCLK will never drive out. ";
end SA110;
