BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: top_750fx

--
-- File:                750FX_DD1.X-DD2.X25July02.bdsl
-- Application:         IBM PowerPC(R) 750FX Revisions DD1.X-DD2.X 
--                      at 1.8V, 2.5V, and 3.3V
--
--      IMPORTANT NOTE: Before using this file, select the voltage
--                      and Processor Version Register (PVR). 
--
--                      For information on how to select the voltage,
--                      see the comments in the "Option: User-Selectable  
--                      Options for COMPLIANCE_PATTERNS" section in this
--                      file.
--
--                      For information on how to select the Processor
--                      Version Register (PVR) number, see the comments
--                      in the "OPTION: User-Selectable Options for PVR"
--                      section in this file.
--                        
--
-- Released:            25 July 2002
-- Copyright:           IBM Microelectronics Division, 2001, 2002
-- Revision:            1.1
--
--
-- The receipt or possession of this file does not convey any
-- rights to reproduce or disclose its contents, or to manufacture, use
-- or sell anything that it may describe, in whole or in part, without
-- specific written consent of IBM CORPORATION.
-- Any reproduction of this file without the express written consent of
-- IBM CORPORATION is a violation of the copyright laws and may subject
-- you to civil liability and criminal prosecution.
-- 
-- ************************ DISCLAIMER ************************
-- This information is for modeling purposes only, and is not guaranteed.
--
-- The following are trademarks of International Business Machines Corporation  
-- in the United States, or other countries, or both:
--  IBM            IBM logo   
--  PowerPC Logo   PowerPC
--  PowerPC 750
--
-- Other company, product and service names may be trademarks or service
-- marks of others.
--
-- All information contained in this document is subject to change without 
-- notice. The products described in this document are NOT intended for 
-- use in applications such as implantation, life support, or other 
-- hazardous uses where malfunction could result in death, bodily injury,
-- or catastrophic property damage. The information contained in this 
-- document does not affect or change IBM product specifications 
-- or warranties. Nothing in this document shall operate as an express 
-- or implied license or indemnity under the intellectual property rights 
-- of IBM or third parties. All information contained in this document was 
-- obtained in specific environments, and is presented as an illustration.
-- The results obtained in other operating environments may vary.

-- THIS INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY
-- KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, AND NON-INFRINGEMENT. SOME JURISDICTIONS
-- DO NOT ALLOW THE EXCLUSION OF IMPLIED WARRANTIES, SO THE
-- ABOVE EXCLUSION MAY NOT APPLY TO YOU.		
--
-- This Information may contain technical inaccuracies or
-- typographical errors. IBM reserves the right to modify or
-- withdraw this information at any time without notice.
-- All information contained in this document was obtained in 
-- specific environments, and is presented as an illustration. 
-- The results obtained in other operating environments may vary.	
--
-- IN NO EVENT WILL IBM BE LIABLE TO ANY PARTY FOR ANY DIRECT,
-- INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES FOR ANY USE OF
-- THIS INFORMATION, INCLUDING, WITHOUT LIMITATION, ANY LOST
-- PROFITS, BUSINESS INTERRUPTION, LOSS OF PROGRAMS OR OTHER
-- DATA ON YOUR INFORMATION HANDLING SYSTEM OR OTHERWISE, EVEN
-- IF WE ARE EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH
-- DAMAGES.
--
-- ************************ NOTES ************************
--
-- BSDL printed by TestBench
-- Generated BSDL for IBM PowerPC 750FX revision DD1.X-DD2.x
--
-- BSDL manually modified in order to correct errors which
-- allowed file to pass the AGILENT syntax checker.
--
-- LIST of MODIFICATIONS
--
-- 19 December 2001
--
-- Removed PSRO_1, PSRO_2 and PSRO_3. Apparently they are 
-- not part of the device.
-- Removed all "pin_" preceeding the bit/bit_vector_names 
-- (also from TestBench_Port_Alias)
-- Several pins in the PHYSICAL PIN MAP were defined as inout
-- (the original definition is commented beside the proper one).
-- The power were missing from the original bsdl (see comments).
-- Some pins missing from the PIN_MAP_STRING (see comments).
-- Pin T13 defined twice in the VDD definition
-- Added the "attribute REGISTER_ACCESS" section.
-- Pins Y1 and Y2 not included in the BSDL. Added as linkage bits.
-- Modified the timing for tap_scan_clk (it as too long)
-- To see all the modifications look for AGP.
--
-- 19 July 2002
--
-- Change made to COMPLIANCE PATTERNS  to make the  bsdl run on various 
-- voltage levels (right now the  BSDL  is good to run  at 1.8V
-- Change the PATTERN structure and comment out the other two modes. 
-- See the comments in the "Options: User-Selectable Options for
-- COMPLIANCE_PATTERNS" section of this file for information on 
-- how to select a voltage.
--
-- See the comments in the "Options: User-Selectable Options for PVR"
-- section of this file for information on how to select one of the
-- folowing PVRs.
--
--  The DD2.X PVR is  Hex ' 7000 02xx 
--  The DD1.X PVR is  Hex ' 7000 01xx


entity top_750fx is
  generic (PHYSICAL_PIN_MAP : string := "CBGA292");

--  port (PSRO_2: in bit;       --AGP
--        PSRO_3: in bit;       --AGP
    port (    BVSEL: in bit;
        BLANK1: linkage bit;    --AGP  not in the original BSDL
        BLANK2: linkage bit;    --AGP  not in the original BSDL
        L1_TSTCLK: in bit;
        L2_TSTCLK: in bit;
        LSSD_MODE_N: in bit;
        TCK: in bit;
        TDI: in bit;
        TMS: in bit;
        TRST_N: in bit;
--      PSRO_1: inout bit;      --AGP
        A: inout bit_vector(0 to 31);
        AACK_N: inout bit;
        ABB_N: inout bit;
        AP: inout bit_vector(0 to 3);
        ARTRY_N: inout bit;
        BG_N: inout bit;
        BR_N: out bit;                 -- was inout AGP
        CHECKSTOP_N: out bit;          -- was inout AGP
        CI_N: out bit;                 -- was inout AGP
        CKSTP_N: in bit;               -- was inout AGP
        CLK_OUT: out bit;              -- was inout AGP
        DBB_N: inout bit;
        DBDIS_N: in bit;               -- was inout AGP
        DBG_N: in bit;                 -- was inout AGP
        DBWO_N: in bit;                -- was inout AGP
        DH: inout bit_vector(0 to 31);
        DL: inout bit_vector(0 to 31);
        DP: inout bit_vector(0 to 7);
        DRTRY_N: in bit;               -- was inout AGP
        GBL_N: inout bit;
        HRESET_N: in bit;              -- was inout AGP
        INT_N: in bit;                 -- was inout AGP
        MCP_N: in bit;                 -- was inout AGP
        PLL_CFG: in bit_vector(0 to 4);  -- was inout AGP
        PLL_RANGE: in bit_vector(0 to 1);-- was inout AGP
        QACK_N: in bit;             -- was inout AGP
        QREQ_N: out bit;            -- was inout AGP
        RSRV_N: out bit;            -- was inout AGP
        SMI_N: in bit;              -- was inout AGP
        SRESET_N: in bit;           -- was inout AGP
        SYSCLK: in bit;             -- was inout AGP
        AGND:  linkage bit;   -- AGP missing from the original bsdl
        A1VDD: linkage bit;   -- AGP missing from the original bsdl
        A2VDD: linkage bit;   -- AGP missing from the original bsdl
        GND:  linkage bit_vector (0 to 59); -- AGP missing from the orig bsdl
        OVDD:  linkage bit_vector (0 to 31);-- AGP missing from the orig bsdl
        VDD:  linkage bit_vector (0 to 31); -- AGP missing from the orig bsdl
        TA_N: in bit;              -- was inout AGP
        TBEN: in bit;              -- was inout AGP
        TBST_N: inout bit;
        TDO: out bit;            -- AGP was inout
        TEA_N: in bit;           -- was inout AGP
        TLBISYNC_N: in bit;   -- was inout AGP
        TSIZ: out bit_vector(0 to 2);   -- was inout AGP
        TS_N: inout bit;
        TT: inout bit_vector(0 to 4);
        WT_N: out bit);    -- was inout AGP

  use STD_1149_1_1994.all;

  attribute COMPONENT_CONFORMANCE of top_750fx:
  entity is "STD_1149_1_1993";
-- the following PIN_MAP statement was generated
  attribute PIN_MAP of top_750fx : entity is PHYSICAL_PIN_MAP;

  constant CBGA292:PIN_MAP_STRING:=

  "AACK_N:A8     ," &
  "ABB_N:Y6    ," &
  "BLANK1:Y1    ," &    --AGP  not in the original BSDL
  "BLANK2:Y2    ," &    --AGP  not in the original BSDL
  "AGND:Y14    ," &
  "ARTRY_N:W7    ," &
  "A1VDD:Y15    ," &
  "A2VDD:Y16    ," &
  "BG_N:W4    ," &
  "BR_N:Y3    ," &
  "BVSEL:W9    ," &
  "CHECKSTOP_N:Y12    ," &
  "CI_N:T4    ," &
  "CKSTP_N:Y10    ," &
  "DBB_N:U7    ," &
  "DBDIS_N:A10    ," &
  "DBG_N:Y5    ," &
  "DBWO_N:A6    ," &
  "DRTRY_N:W3    ," &
  "GBL_N:W1    ," &
  "HRESET_N:Y11    ," &
  "INT_N:Y9    ," &
  "L1_TSTCLK:Y13    ," &
  "L2_TSTCLK:W13    ," &
  "LSSD_MODE_N:U13    ," &
  "MCP_N:W12    ," &
  "PLL_CFG:(Y18, W17, Y17, U16, W14)    ," &
  "PLL_RANGE:(W15, U14)    ," &
  "QACK_N:Y8    ," &
  "QREQ_N:U8    ,"&
  "RSRV_N:Y4    ," &
  "SMI_N:W10    ," &
  "SRESET_N:Y7    ," &
  "SYSCLK:W16    ," &
  "TA_N:A12    ," &
  "TBEN:W8    ," &
  "TBST_N:A11    ," &
  "TCK:T2    ," &
  "TDI:V2    ," &
  "TDO:W5    ," &
  "TEA_N:W6    ," &
  "TLBISYNC_N:W11    ," &
  "TMS:V1    ," &
  "TRST_N:U1    ," &
  "TS_N:B15    ," &
  "TSIZ:(A14, B12, B11)    ," &
  "TT:(D14, B17, B14, A15, B13)    ," &
  "WT_N:U5    ," &
  "A : (E20    ," &
  "E19," &
  "D20," &
  "C20," &
  "D19," &
  "C19," &
  "A20," &
  "E16," &
  "B20," &
  "E17," &
  "B18," &
  "A18," &
  "A17," &
  "A19," &
  "A16," &
  "B16," &
  "B10," &
  "B9 ," &
  "A9," &
  "B7," &
  "A7," &
  "D8," &
  "A5," &
  "B6," &
  "D7," &
  "D5," &
  "B5," &
  "B4," &
  "A4," &
  "A3," &
  "B3," &
  "E5)," &
  "DL:(A2," &
  "A1," &
  "C2," &
  "E4," &
  "C1," &
  "E2," &
  "D2," &
  "E1," &
  "D1," &
  "F1," &
  "G2," &
  "F2," &
  "H2," &
  "H4," &
  "G1," &
  "K2," &
  "J2," &
  "K1," &
  "J1," &
  "L2," &
  "M2," &
  "L1," &
  "N2," &
  "N4," &
  "N1," &
  "P1," &
  "P4," &
  "P2," &
  "R2," &
  "R1," &
  "U2," &
  "T1)," &
  "DP:(T20,"&       -- AGP missing from the original
  "N19," &          -- AGP missing from the original
  "J20," &          -- AGP missing from the original
  "G19," &          -- AGP missing from the original
  "B1," &          -- AGP missing from the original
  "G4," &          -- AGP missing from the original
  "H1 ," &          -- AGP missing from the original
  "M1 )," &         -- AGP missing from the original
  "CLK_OUT:T5    ," & -- AGP missing from the original
  "AP:(D16,"&       -- AGP missing from the original
  "D13," &          -- AGP missing from the original
  "A13 ," &          -- AGP missing from the original
  "B8 )," &         -- AGP missing from the original




  "DH:(W18,"&
  "T17," &
  "Y20," &
  "Y19," &
  "W20," &
  "V19," &
  "U19," &
  "T16," &
  "T19," &
  "U20," &
  "V20," &
  "R19," &
  "N17," &
  "P17," &
  "R20," &
  "P20," &
  "N20," &
  "P19," &
  "M20," &
  "L20," &
  "M19," &
  "L19," &
  "K20," &
  "J19," &
  "K19," &
  "G20," &
  "H20," &
  "H17," &
  "H19," &
  "F19," &
  "G17," &
  "F20)," &
  "GND:(B2," &
  "C5," &
  "C13," &
  "D10," &
  "E3," &
  "E14," &
  "F10," &
  "G5," &
  "G13," &
  "H3," &
  "H9," &
  "H13," &
  "J12," &
  "K7," &
  "K14," &
  "L4," &
  "L10," &
  "L17," &
  "N3," &
  "N9," &
  "N13," &
  "P5," &
  "P13," &
  "R10," &
  "T3," &
  "T14," &
  "U10," &
  "V5," &
  "V13," &
  "W2," &
  "B19," &
  "C8," &
  "C16," &
  "D11," &
  "E7," &
  "E18," &
  "F11," &
  "G8," &
  "G16," &
  "H8," &
  "H12," &
  "H18," &
  "K4," &
  "K10," &
  "K17," &
  "L7," &
  "L14," &
  "M12," &
  "N8," &
  "N12," &
  "N18," &
  "P8," &
  "P16," &
  "R11," &
  "T7," &
  "T18," &
  "U11," &
  "V8," &
  "V16," &
  "W19)," &
"OVDD:(C4," &
  "C14," &
  "D3," &
  "E10," &
  "G3," &
  "G14," &
  "H5," &
  "K5," &
  "L5," &
  "N5," &
  "P3," &
  "P14," &
  "T10," &
  "U3," &
  "V4," &
  "V14," &
  "C7," &
  "C17," &
  "D18," &
  "E11," &
  "G7," &
  "G18," &
  "H16," &
  "K16," &
  "L16," &
  "N16," &
  "P7," &
  "P18," &
  "T11," &
  "U18," &
  "V7," &
  "V17)," &
"VDD:(C10," &
  "E8," &
  "F6," &
  "F12," &
  "J8," &
  "J13," &
  "K8," &
  "K13," &
  "L3," &
  "L11," &
  "L18," &
  "M9," &
  "R6," &
  "R12," &
  "T8," &
  "V10," &
  "C11," &
  "E13," &
  "F9," &
  "F15," &
  "J9," &
  "K3," &
  "K11," &
  "K18," &
  "L8," &
  "L13," &
  "M8," &
  "M13," &
  "R9," &
  "R15," &
--"T13," &        -- redundant AGP
  "T13,"&
  "V11) " ;

  attribute TAP_SCAN_IN of TDI: signal is true;
  attribute TAP_SCAN_MODE of TMS: signal is true;
  attribute TAP_SCAN_OUT of TDO: signal is true;
--  attribute TAP_SCAN_CLOCK of TCK: signal is (1.0e1,LOW); --AGP time is too hi
  attribute TAP_SCAN_CLOCK of TCK: signal is (20.0e6,LOW);
  attribute TAP_SCAN_RESET of TRST_N: signal is true;

-- OPTION: User-Selectable Options for COMPLIANCE_PATTERNS (Voltage Settings)
--  This section provides support for 1.8V, 2.5V and 3.3V.
--
--
-- How to enable:
--  To enable a COMPLIANCE_PATTERNS voltage setting you are testing,
--  remove the comment marks (two dashes, "--") from the beginning
--  of the attribute COMPLIANCE_PATTERNS command you want to enable.  
--
-- Note: Only one COMPLIANCE_PATTERNS voltage setting 
--       can be activate per execution of this file.
--
-- How to disable:  
--  To disable the COMPLIANCE_PATTERNS voltage settings you 
--  are not testing, insert comment marks (two dashes, "--")
--  at the beginning of each line of the attribute statement.  
--
-- Default COMPLIANCE_PATTERNS Voltage setting:
--  This file is shipped with the 1.8V COMPLIANCE_PATTERN as active.
--  The 2.5V and 3.3V COMPLIANCE_PATTERNS are commented, and
--  are therefore inactive.
--
--
-- 1.8V COMPLIANCE_PATTERNS:
--  Use this setting when running board signals at 1.8V. 
--
    attribute COMPLIANCE_PATTERNS of top_750fx: entity is
     "(BVSEL, L1_TSTCLK,  L2_TSTCLK, LSSD_MODE_N)"  &
     "(0111)";
--
--
--  2.5V COMPLIANCE_PATTERNS:
--   Use this setting when running board signals at 2.5V.
--
--  attribute COMPLIANCE_PATTERNS of top_750fx: entity is
--     "(BVSEL, L1_TSTCLK,  L2_TSTCLK, LSSD_MODE_N)"  &
--     "(1111)";
--
--  3.3V COMPLIANCE_PATTERNS:
--   Use this setting when running board signals at 3.3V.
-- 
--   attribute COMPLIANCE_PATTERNS of top_750fx: entity is
--     "(BVSEL, L1_TSTCLK,  L2_TSTCLK, LSSD_MODE_N)"  &
--     "(1011)";
--

  attribute INSTRUCTION_LENGTH of top_750fx: entity is 8;

--  attribute INSTRUCTION_OPCODE of top_750fx: entity is
--      "BYPASS (11111111)," &
--      "EXTEST (00000000)";

  attribute INSTRUCTION_OPCODE of top_750fx: entity is

-- Standard instructions:
       "EXTEST (00000000), "&     -- Hex 00
       "SAMPLE (11000000), "&     -- Hex C0
       "BYPASS (11111111), "&     -- Hex FF
       "HIGHZ  (11110000), "&     -- Hex F0
       "CLAMP  (11110001), "&     -- Hex F1

-- Public instruction:

       "READ_PVR (01111100)";      -- Hex 7C


  attribute INSTRUCTION_CAPTURE of top_750fx: entity is "XXXXXX01";

-- AGP this section added
--
-- OPTION: User-Selectable Options for PVR
--  This section provides support for DD1.X and DD2.X PVRs.
--
-- How to enable:
--  To enable a REGISTER_ACCESS PVR setting you are testing, remove
--  the comment marks (two dashes, "--") from the beginning of the 
--  "PVR[32](READ_PVR CAPTURES..." statement you want to enable.  
--
-- Note: Only one REGISTER_ACCESS PVR setting  
--       can be activate per execution of this file.
--
-- How to disable:  
--  To disable the REGISTER_ACCESS PVR setting you 
--  are not testing, insert comment marks (two dashes, "--")
--  at the beginning of the "PVR[32](READ_PVR CAPTURES..." 
--  statement you want to disable.  
--
-- Default REGISTER_ACCESS PVR setting:
--  This file is shipped with the DD2.X REGISTER_ACCESS PVR setting 
--  as active.  The DD1.X REGISTER_ACCESS PVR setting is commented,
--  and is therefore inactive.

  attribute REGISTER_ACCESS of top_750fx : entity is
         "BYPASS(BYPASS),   " &

-- PVR for DD2.X
--     Add or remove the comment marks from the proceeding line to disable or enable the DD2.X PVR.
         "PVR[32](READ_PVR CAPTURES 011100000000000000000010XXXXXXXX) ";
--       Capture Value = Hex"0x 7000 02xx" where xx = minor chip revision level 
--       DD2.X has a PVR above Hex "x700002xx" 
--
-- PVR for DD1.X
--    Add or remove the comment marks from the proceeding line to disable or enable the DD1.X PVR.
--      "PVR[32](READ_PVR CAPTURES 011100000000000000000001XXXXXXXX) ";
--       Capture Value = Hex"0x 7000 01xx" where XX = minor chip revision level 
--       DD1.X has a PVR above Hex "x700001xx"


-- End of section added

  attribute BOUNDARY_LENGTH of top_750fx: entity is 187;

  attribute BOUNDARY_REGISTER of top_750fx: entity is
    "0 (BC_7, A(5),bidir,X,181,0,Z),"  &
    "1 (BC_7, A(6),bidir,X,181,0,Z),"  &
    "2 (BC_7, A(7),bidir,X,10,0,Z),"  &
    "3 (BC_7, A(8),bidir,X,181,0,Z),"  &
    "4 (BC_7, A(9),bidir,X,10,0,Z),"  &
    "5 (BC_7, A(10),bidir,X,181,0,Z),"  &
    "6 (BC_7, A(11),bidir,X,181,0,Z),"  &
    "7 (BC_7, AP(0),bidir,X,10,0,Z),"  &
    "8 (BC_7, A(12),bidir,X,10,0,Z),"  &
    "9 (BC_7, A(13),bidir,X,10,0,Z),"  &
    "10 (BC_1,*,control,0),"  &
    "11 (BC_7, A(14),bidir,X,16,0,Z),"  &
    "12 (BC_7, A(15),bidir,X,16,0,Z),"  &
    "13 (BC_7, TT(0),bidir,X,16,0,Z),"  &
    "14 (BC_7, TT(1),bidir,X,16,0,Z),"  &
    "15 (BC_7, TT(2),bidir,X,16,0,Z),"  &
    "16 (BC_1,*,control,0),"  &
    "17 (BC_1,*,control,0),"  &
    "18 (BC_7, TT(3),bidir,X,17,0,Z),"  &
    "19 (BC_7, AP(1),bidir,X,20,0,Z),"  &
    "20 (BC_1,*,control,0),"  &
    "21 (BC_7, TS_N,bidir,X,20,0,Z),"  &
    "22 (BC_7, TT(4),bidir,X,17,0,Z),"  &
    "23 (BC_1, TSIZ(0),output3,X,17,0,Z),"  &
    "24 (BC_1, TSIZ(1),output3,X,17,0,Z),"  &
    "25 (BC_7, AP(2),bidir,X,20,0,Z),"  &
    "26 (BC_1, TSIZ(2),output3,X,17,0,Z),"  &
    "27 (BC_1,*,control,0),"  &
    "28 (BC_1, DBDIS_N,input,X),"  &
    "29 (BC_1, TA_N,input,X),"  &
    "30 (BC_7, TBST_N,bidir,X,17,0,Z),"  &
    "31 (BC_7, AACK_N,bidir,X,27,0,Z),"  &
    "32 (BC_1,*,control,0),"  &
    "33 (BC_7, A(16),bidir,X,32,0,Z),"  &
    "34 (BC_7, A(17),bidir,X,32,0,Z),"  &
    "35 (BC_7, A(18),bidir,X,32,0,Z),"  &
    "36 (BC_7, A(19),bidir,X,32,0,Z),"  &
    "37 (BC_7, AP(3),bidir,X,32,0,Z),"  &
    "38 (BC_1,*,control,0),"  &
    "39 (BC_7, A(20),bidir,X,38,0,Z),"  &
    "40 (BC_7, A(21),bidir,X,41,0,Z),"  &
    "41 (BC_1,*,control,0),"  &
    "42 (BC_7, A(22),bidir,X,41,0,Z),"  &
    "43 (BC_1, DBWO_N,input,X),"  &
    "44 (BC_7, A(23),bidir,X,41,0,Z),"  &
    "45 (BC_7, A(24),bidir,X,38,0,Z),"  &
    "46 (BC_7, A(25),bidir,X,38,0,Z),"  &
    "47 (BC_7, A(26),bidir,X,41,0,Z),"  &
    "48 (BC_7, A(27),bidir,X,38,0,Z),"  &
    "49 (BC_7, A(28),bidir,X,53,0,Z),"  &
    "50 (BC_7, A(29),bidir,X,53,0,Z),"  &
    "51 (BC_7, A(30),bidir,X,53,0,Z),"  &
    "52 (BC_7, A(31),bidir,X,53,0,Z),"  &
    "53 (BC_1,*,control,0),"  &
    "54 (BC_7, DL(0),bidir,X,59,0,Z),"  &
    "55 (BC_7, DL(1),bidir,X,59,0,Z),"  &
    "56 (BC_7, DP(4),bidir,X,59,0,Z),"  &
    "57 (BC_7, DL(2),bidir,X,59,0,Z),"  &
    "58 (BC_7, DL(3),bidir,X,59,0,Z),"  &
    "59 (BC_1,*,control,0),"  &
    "60 (BC_7, DL(4),bidir,X,64,0,Z),"  &
    "61 (BC_7, DL(5),bidir,X,64,0,Z),"  &
    "62 (BC_7, DL(6),bidir,X,64,0,Z),"  &
    "63 (BC_7, DL(7),bidir,X,64,0,Z),"  &
    "64 (BC_1,*,control,0),"  &
    "65 (BC_7, DL(8),bidir,X,71,0,Z),"  &
    "66 (BC_7, DL(9),bidir,X,71,0,Z),"  &
    "67 (BC_7, DP(5),bidir,X,71,0,Z),"  &
    "68 (BC_7, DL(10),bidir,X,71,0,Z),"  &
    "69 (BC_7, DL(11),bidir,X,71,0,Z),"  &
    "70 (BC_7, DL(12),bidir,X,71,0,Z),"  &
    "71 (BC_1,*,control,0),"  &
    "72 (BC_1,*,control,0),"  &
    "73 (BC_7, DL(13),bidir,X,72,0,Z),"  &
    "74 (BC_7, DP(6),bidir,X,72,0,Z),"  &
    "75 (BC_7, DL(14),bidir,X,72,0,Z),"  &
    "76 (BC_7, DL(15),bidir,X,72,0,Z),"  &
    "77 (BC_7, DL(16),bidir,X,72,0,Z),"  &
    "78 (BC_7, DL(17),bidir,X,72,0,Z),"  &
    "79 (BC_1,*,control,0),"  &
    "80 (BC_7, DL(18),bidir,X,79,0,Z),"  &
    "81 (BC_7, DL(19),bidir,X,79,0,Z),"  &
    "82 (BC_7, DL(20),bidir,X,79,0,Z),"  &
    "83 (BC_7, DL(21),bidir,X,79,0,Z),"  &
    "84 (BC_7, DP(7),bidir,X,79,0,Z),"  &
    "85 (BC_7, DL(22),bidir,X,79,0,Z),"  &
    "86 (BC_1,*,control,0),"  &
    "87 (BC_7, DL(23),bidir,X,86,0,Z),"  &
    "88 (BC_7, DL(24),bidir,X,86,0,Z),"  &
    "89 (BC_7, DL(25),bidir,X,86,0,Z),"  &
    "90 (BC_1,*,control,0),"  &
    "91 (BC_7, DL(26),bidir,X,90,0,Z),"  &
    "92 (BC_7, DL(27),bidir,X,90,0,Z),"  &
    "93 (BC_7, DL(28),bidir,X,90,0,Z),"  &
    "94 (BC_1,*,control,0),"  &
    "95 (BC_7, DL(29),bidir,X,94,0,Z),"  &
    "96 (BC_7, DL(30),bidir,X,94,0,Z),"  &
    "97 (BC_1,*,control,0),"  &
    "98 (BC_1, CI_N,output3,X,97,0,Z),"  &
    "99 (BC_7, GBL_N,bidir,X,97,0,Z),"  &
    "100 (BC_7, DL(31),bidir,X,94,0,Z),"  &
    "101 (BC_1, RSRV_N,output3,X,107,0,Z),"  &
    "102 (BC_1, WT_N,output3,X,97,0,Z),"  &
    "103 (BC_1, DRTRY_N,input,X),"  &
    "104 (BC_1,*,control,0),"  &
    "105 (BC_1, CLK_OUT,output3,X,104,0,Z),"  &
    "106 (BC_7, BG_N,bidir,X,27,0,Z),"  &
    "107 (BC_1,*,control,0),"  &
    "108 (BC_1, BR_N,output3,X,107,0,Z),"  &
    "109 (BC_1, DBG_N,input,X),"  &
    "110 (BC_1,*,control,0),"  &
    "111 (BC_7, ABB_N,bidir,X,110,0,Z),"  &
    "112 (BC_1,*,control,0),"  &
    "113 (BC_7, DBB_N,bidir,X,112,0,Z),"  &
    "114 (BC_1,*,control,0),"  &
    "115 (BC_7, ARTRY_N,bidir,X,114,0,Z),"  &
    "116 (BC_1, TBEN,input,X),"  &
    "117 (BC_1, TLBISYNC_N,input,X),"  &
    "118 (BC_1, TEA_N,input,X),"  &
    "119 (BC_1, QREQ_N,output3,X,107,0,Z),"  &
    "120 (BC_1, QACK_N,input,X),"  &
    "121 (BC_1, SRESET_N,input,X),"  &
    "122 (BC_1, SMI_N,input,X),"  &
    "123 (BC_1, INT_N,input,X),"  &
    "124 (BC_1, CKSTP_N,input,X),"  &
    "125 (BC_1, PLL_RANGE(0),input,X),"  &
    "126 (BC_1, PLL_RANGE(1),input,X),"  &
    "127 (BC_1, PLL_CFG(4),input,X),"  &
    "128 (BC_1, PLL_CFG(3),input,X),"  &
    "129 (BC_1, PLL_CFG(2),input,X),"  &
    "130 (BC_1, PLL_CFG(1),input,X),"  &
    "131 (BC_1,*,control,0),"  &
    "132 (BC_1, CHECKSTOP_N,output3,X,131,0,Z),"  &
    "133 (BC_1, PLL_CFG(0),input,X),"  &
    "134 (BC_1, SYSCLK,input,X),"  &
    "135 (BC_1, HRESET_N,input,X),"  &
    "136 (BC_1, MCP_N,input,X),"  &
    "137 (BC_1,*,control,0),"  &
    "138 (BC_7, DH(0),bidir,X,137,0,Z),"  &
    "139 (BC_7, DH(1),bidir,X,137,0,Z),"  &
    "140 (BC_7, DH(2),bidir,X,137,0,Z),"  &
    "141 (BC_7, DH(3),bidir,X,137,0,Z),"  &
    "142 (BC_7, DH(4),bidir,X,137,0,Z),"  &
    "143 (BC_7, DH(5),bidir,X,148,0,Z),"  &
    "144 (BC_7, DH(6),bidir,X,148,0,Z),"  &
    "145 (BC_7, DH(7),bidir,X,148,0,Z),"  &
    "146 (BC_7, DH(8),bidir,X,148,0,Z),"  &
    "147 (BC_7, DH(9),bidir,X,148,0,Z),"  &
    "148 (BC_1,*,control,0),"  &
    "149 (BC_7, DP(0),bidir,X,154,0,Z),"  &
    "150 (BC_7, DH(10),bidir,X,154,0,Z),"  &
    "151 (BC_7, DH(11),bidir,X,154,0,Z),"  &
    "152 (BC_7, DH(12),bidir,X,154,0,Z),"  &
    "153 (BC_7, DH(13),bidir,X,154,0,Z),"  &
    "154 (BC_1,*,control,0),"  &
    "155 (BC_7, DH(14),bidir,X,160,0,Z),"  &
    "156 (BC_7, DH(15),bidir,X,160,0,Z),"  &
    "157 (BC_7, DH(16),bidir,X,160,0,Z),"  &
    "158 (BC_7, DH(17),bidir,X,160,0,Z),"  &
    "159 (BC_7, DP(1),bidir,X,160,0,Z),"  &
    "160 (BC_1,*,control,0),"  &
    "161 (BC_1,*,control,0),"  &
    "162 (BC_7, DH(18),bidir,X,161,0,Z),"  &
    "163 (BC_7, DH(19),bidir,X,161,0,Z),"  &
    "164 (BC_7, DH(20),bidir,X,161,0,Z),"  &
    "165 (BC_1,*,control,0),"  &
    "166 (BC_7, DH(21),bidir,X,161,0,Z),"  &
    "167 (BC_7, DP(2),bidir,X,161,0,Z),"  &
    "168 (BC_7, DH(22),bidir,X,165,0,Z),"  &
    "169 (BC_7, DH(23),bidir,X,165,0,Z),"  &
    "170 (BC_7, DH(24),bidir,X,165,0,Z),"  &
    "171 (BC_7, DH(25),bidir,X,165,0,Z),"  &
    "172 (BC_7, DH(26),bidir,X,165,0,Z),"  &
    "173 (BC_7, DH(27),bidir,X,165,0,Z),"  &
    "174 (BC_1,*,control,0),"  &
    "175 (BC_7, DH(28),bidir,X,174,0,Z),"  &
    "176 (BC_7, DH(29),bidir,X,174,0,Z),"  &
    "177 (BC_7, DP(3),bidir,X,174,0,Z),"  &
    "178 (BC_7, DH(30),bidir,X,174,0,Z),"  &
    "179 (BC_7, DH(31),bidir,X,174,0,Z),"  &
    "180 (BC_7, A(0),bidir,X,183,0,Z),"  &
    "181 (BC_1,*,control,0),"  &
    "182 (BC_7, A(1),bidir,X,183,0,Z),"  &
    "183 (BC_1,*,control,0),"  &
    "184 (BC_7, A(2),bidir,X,183,0,Z),"  &
    "185 (BC_7, A(3),bidir,X,183,0,Z),"  &
    "186 (BC_7, A(4),bidir,X,183,0,Z)";

  attribute TestBench_Time_Date: BSDL_EXTENSION;
  attribute TestBench_Port_Alias: BSDL_EXTENSION;

  attribute TestBench_Time_Date of top_750fx: entity is
  "BSDL was generated on Wed Oct 10 14:56:39 2001";

  attribute TestBench_Port_Alias of top_750fx: entity is
-- Changed pin_PINNAME to  PINNAME  AGP

  "LSSD_MODE_N:LSSD_MODE_,"  &
  "TRST_N:TRST_,"  &
  "AACK_N:AACK_,"  &
  "ABB_N:ABB_,"  &
  "ARTRY_N:ARTRY_,"  &
  "BG_N:BG_,"  &
  "BR_N:BR_,"  &
  "CHECKSTOP_N:CHECKSTOP_,"  &
  "CI_N:CI_,"  &
  "CKSTP_N:CKSTP_,"  &
  "DBB_N:DBB_,"  &
  "DBDIS_N:DBDIS_,"  &
  "DBG_N:DBG_,"  &
  "DBWO_N:DBWO_,"  &
  "DRTRY_N:DRTRY_,"  &
  "GBL_N:GBL_,"  &
  "HRESET_N:HRESET_,"  &
  "INT_N:INT_,"  &
  "MCP_N:MCP_,"  &
  "QACK_N:QACK_,"  &
  "QREQ_N:QREQ_,"  &
  "RSRV_N:RSRV_,"  &
  "SMI_N:SMI_,"  &
  "SRESET_N:SRESET_,"  &
  "TA_N:TA_,"  &
  "TBST_N:TBST_,"  &
  "TEA_N:TEA_,"  &
  "TLBISYNC_N:TLBISYNC_,"  &
  "TS_N:TS_,"  &
  "WT_N:WT_";


end top_750fx;