-- *********************************************************************
-- * *
-- * ispLSI2128E 176 pin TQFP BSDL Model *
-- * copyright 1996-1999, Lattice Semiconductor Corporation *
-- * IEEE 1149.1b-1994 *
-- * Standard Test Access Port and Boundary-Scan Architecture *
-- * VHDL Description File *
-- * *
-- * Date: Jul 22 1999 *
-- * File Version: v2.0-00 *
-- * *
-- * This BSDL file has been syntaxed checked with: *
-- * - Teradyne VICTORY *
-- * - Assett Intertech *
-- * *
-- *********************************************************************
-- * *
-- * E2CMOS, GAL, ispGAL, pDS, pLSI, Silicon Forest and UltraMOS are *
-- * registered trademarks of Lattice Semiconductor Corporation *
-- * *
-- * Generic Array Logic, ISP, ispCODE, ispDOWNLOAD, ispGDS, ispLSI *
-- * ispSTREAM, Latch-Lock, pDS+ and RFT are trademarks of Lattice *
-- * Semiconductor Corporation. *
-- * *
-- *********************************************************************
-- * *
-- * IMPORTANT *
-- * *
-- * This device does not include a BSCAN register and does not *
-- * directly support pin continuing testing. The BSDL file is *
-- * is provided to define the devices in a scan chain where the *
-- * Instruction Register and Bypass isntruction must be known *
-- * *
-- *********************************************************************
-- The Overall Structute of the Entity Description
entity ispLSI2128E is
-- Generic Parameter Statement
generic (PHYSICAL_PIN_MAP : string := "TQFP_176");
-- Logical Port Description Statement
port ( TDI: in bit; -- JTAG input pin
TMS: in bit; -- JTAG input pin
TCK: in bit; -- JTAG input pin
TDO: out bit; -- JTAG output pin
ispEN: linkage bit; -- ispEN pin
RESET: linkage bit; -- Active low RESET pin
GOE: linkage bit_vector (0 to 1); -- Global Output Enable
Clk: linkage bit_vector (0 to 2); -- Clock input pins
DIn: linkage bit_vector (0 to 3); -- Clock input pins
NoC: linkage bit; -- No connect pin
BIp: linkage bit_vector (0 to 127); -- Bi-Directional pins
VCC: linkage bit_vector (0 to 15); -- VCC pins
GND: linkage bit_vector (0 to 15) -- GND pins
);
-- Version Control
use STD_1149_1_1994.all; -- 1149.1-1994 attributes
-- Component Conformance Statement
attribute COMPONENT_CONFORMANCE of ispLSI2128E : entity is
"STD_1149_1_1993";
-- Device Pacakge Pin Mapping
attribute PIN_MAP of ispLSI2128E : entity is PHYSICAL_PIN_MAP;
constant TQFP_176: PIN_MAP_STRING:=
"TDI:24," & -- JTAG (TDI) input pin
"TMS:26," & -- JTAG (TMS) input pin
"TCK:25," & -- JTAG (TCK) input pin
"TDO:114," & -- JTAG (TDO) output pin
"RESET:22," & -- RESET input pin
"ispEN:23," & -- ispEN control pin
"GOE:( 110, 109), " & -- Global OE pins
"Clk:( 19, 21, 111), " & -- Clock pins
"DIn:( 106, 107, 112, 113), " & -- Dedicated Input pins
"NoC:20," & -- No Connect pin
"BIp:( 27, 28, 31, 32, 33, 35, 36, " & -- I/O pins
" 37, 38, 39, 41, 42, 43, 44, " & -- I/O pins
" 45, 46, 47, 48, 50, 51, 52, " & -- I/O pins
" 53, 55, 57, 58, 59, 60, 61, " & -- I/O pins
" 62, 63, 65, 66, 67, 68, 70, " & -- I/O pins
" 71, 72, 73, 75, 76, 77, 79, " & -- I/O pins
" 80, 81, 82, 83, 85, 86, 87, " & -- I/O pins
" 88, 90, 91, 92, 93, 94, 95, " & -- I/O pins
" 96, 97, 99, 101, 102, 103, 104, " & -- I/O pins
" 105, 115, 116, 119, 120, 121, 123, " & -- I/O pins
" 124, 125, 126, 127, 129, 130, 131, " & -- I/O pins
" 132, 133, 134, 135, 136, 138, 139, " & -- I/O pins
" 140, 141, 143, 145, 146, 147, 148, " & -- I/O pins
" 149, 150, 151, 153, 154, 155, 156, " & -- I/O pins
" 158, 159, 160, 161, 163, 164, 165, " & -- I/O pins
" 167, 168, 169, 170, 171, 173, 174, " & -- I/O pins
" 175, 176, 2, 3, 4, 5, 6, " & -- I/O pins
" 7, 8, 9, 12, 14, 15, 16, " & -- I/O pins
" 17, 18), " & -- I/O pins
"VCC:( 13, 34, 56, 78, 100, 122, 144, " & -- VCC pins
" 166, 10, 30, 54, 74, 98, 118, " & -- VCC pins
" 142, 162), " & -- VCC pins
"GND:( 1, 11, 29, 40, 49, 64, 69, " & -- GND pins
" 84, 89, 108, 117, 128, 137, 152, " & -- GND pins
" 157, 172) " ; -- GND pins
-- Scan Port Identification
attribute TAP_SCAN_CLOCK of TCK : Signal is (5.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : Signal is True;
attribute TAP_SCAN_OUT of TDO : Signal is True;
attribute TAP_SCAN_MODE of TMS : Signal is True;
-- Instruction Register Description
attribute INSTRUCTION_LENGTH of ispLSI2128E : entity is 5;
attribute INSTRUCTION_OPCODE of ispLSI2128E : entity is
"BYPASS (11111), " &
"SAMPLE (11100), " &
"EXTEST (00000), " &
"IDCODE (10110), " &
"USERCODE (10111), " &
"HIGHZ (11000), " &
"ADDSHFT (00001), " &
"DATASHFT (00010), " &
"UBE (10000), " &
"PRGM (00111), " &
"VFY (10010), " &
"PRGMSC (01001), " &
"PRIVATE (00011,00100,00101,00110,01000,01010, " &
"01011,01100,01110,01111,10001,10011, " &
"10100,10101,11001,11010,11011,11101, " &
"11110)" ;
attribute INSTRUCTION_CAPTURE of ispLSI2128E : entity is "11001";
attribute INSTRUCTION_PRIVATE of ispLSI2128E : entity is "PRIVATE";
-- IDCODE Defintion
attribute IDCODE_REGISTER of ispLSI2128E: entity is
"0000" & -- version
"0000010100101111" & -- part number (052F)
"00000100001" & -- manufacturer's identity
"1" ; -- required by 1149.1
-- USERCODE Defintion
attribute USERCODE_REGISTER of ispLSI2128E: entity is
"11111111111111111111111111111111";
-- Register Access Description
attribute REGISTER_ACCESS of ispLSI2128E : entity is
"BOUNDARY (SAMPLE), " &
"BYPASS (BYPASS), " &
"ADDREG[150] (ADDSHFT), " &
"DATAREG[320] (DATASHFT), " &
"UBEREG[1] (UBE), " &
"PRGREG[150] (PRGM), " &
"VFYREG[320] (VFY), " &
"SECREG[1] (PRGMSC) " ;
-- **********************************************************************
-- Boundary Scan Register Description, Cell 0 is the closest to TDO
-- **********************************************************************
attribute BOUNDARY_LENGTH of ispLSI2128E : entity is 1;
attribute BOUNDARY_REGISTER of ispLSI2128E : entity is
-- num cell port function safe [ccell disval rslt]
" 0 (BC_1, *, internal, x) ";
attribute DESIGN_WARNING of ispLSI2128E : entity is
"The ispLSI2128E 176 pin TQFP device includes a TAP controller to "&
"perform ISP programming. This device does not include Boundary Scan "&
"Cells and does not support BSCAN test. The BSDL file includes the "&
"SAMPLE/PRELOAD and EXTEST instructions so this device may be included "&
"in the SCAN chain, if these instructions are executed the Bypass "&
"register is selected.";
end ispLSI2128E;
