BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: IDT72V3680BB

	---------------------------------------------------------------------------
-- This model was created at IDT's SYDNEY DESIGN CENTER
-- Part: IDT72V3680BB (SSII+  16384 words x 36bits)
-- Ver: 0.0   Created by:   DSG   Date: 4/3/02
-- Ver: 1.0   Created by:   DJR   Date: 27th June 2002
-- Ver: 2.0   Corrected by: DJR   Date: 9th March 2004
-- Ver: 3.0   Corrected by: DJR   Date: 8th March 2005
-- Customization created on: Tue Dec 13 10:11:19 2005      
---------------------------------------------------------------------------


entity IDT72V3680BB is


  -- Generic parameter

  generic (PHYSICAL_PIN_MAP: string := "BB144");


  -- Logical port description

  port (
    D         :    in      bit_vector(0 to 35);
    IW        :    in      bit;
    SENB      :    in      bit;
    WENB      :    in      bit;
    WCLK      :    in      bit;
    PRSB      :    in      bit;
    MRSB      :    in      bit;
    RM        :    in      bit;
    ASYRB     :    in      bit;
    ASYWB     :    in      bit;
    LDB       :    in      bit;
    FWFTSI    :    in      bit;
    FF        :    buffer  bit;
    PAF       :    buffer  bit;
    OW        :    in      bit;
    FSEL      :    in      bit_vector(0 to 1);
    HF        :    buffer  bit;
    BEB       :    in      bit;
    IP        :    in      bit;
    BM        :    in      bit;
    PAE       :    buffer  bit;
    PFM       :    in      bit;
    EF        :    buffer  bit;
    RCLK      :    in      bit;
    RENB      :    in      bit;
    RTB       :    in      bit;
    OEB       :    in      bit;
    Q         :    buffer  bit_vector(0 to 35);
    TCK       :    in      bit;
    TMS       :    in      bit;
    TDI       :    in      bit;
    TRSTB     :    in      bit;
    TDO       :    out     bit;
    GND       :    linkage bit_vector(0 to 19);
    VCC       :    linkage bit_vector(0 to 19)
	);


  -- Standard

  use STD_1149_1_1994.all;


  -- Component conformance

  attribute COMPONENT_CONFORMANCE of IDT72V3680BB: entity is "STD_1149_1_1993";


  -- Device package pin mappings

  attribute PIN_MAP of IDT72V3680BB: entity is PHYSICAL_PIN_MAP;


  -- Pin-port map for package BB144

  constant BB144: PIN_MAP_STRING :=
    "D       : (K5,  L5,  M5,  K4,  L4,  M4,  L3,  M3,  M2,  " &
               "M1,  L1,  L2,  K1,  K2,  K3,  J1,  J2,  J3,  " &
               "H1,  H2,  H3,  G1,  G2,  G3,  F3,  F2,  F1,  " &
               "E3,  E2,  E1,  D3,  D2,  D1,  C3,  C2,  C1), " &
    "IW      : B2, " &
    "SENB    : B1, " &
    "WENB    : A2, " &
    "WCLK    : A3, " &
    "PRSB    : B3, " &
    "MRSB    : B5, " &
    "RM      : C10, " &
    "ASYRB   : B8, " &
    "ASYWB   : A1, " &
    "LDB     : B4, " &
    "FWFTSI  : C4, " &
    "FF      : A5, " &
    "PAF     : A4, " &
    "OW      : C5, " &
    "FSEL    : (B6,  B7), " &
    "HF      : A6, " &
    "BEB     : C8, " &
    "IP      : B9, " &
    "BM      : A7, " &
    "PAE     : C9, " &
    "PFM     : B10, " &
    "EF      : A8, " &
    "RCLK    : A9, " &
    "RENB    : A10, " &
    "RTB     : B11, " &
    "OEB     : A11, " &
    "Q       : (L8,  M8,  K9,  L9,  M9,  L10, M10, M11, M12, " &
               "L12, L11, K12, K11, K10, J12, J11, J10, H12, " &
               "H11, H10, G12, G11, G10, F10, F11, F12, E10, " &
               "E11, E12, D10, D11, D12, C11, C12, B12, A12), " &
    "TCK     : L7, " &
    "TMS     : L6, " &
    "TDI     : M7, " &
    "TRSTB   : M6, " &
    "TDO     : K8, " &
    "GND     : (D6,  D7,  E5,  E6,  E7,  E8,  F5,  F6, " &
               "F7,  F8,  G5,  G6,  G7,  G8,  H5,  H6, " &
               "H7,  H8,  J6,  J7), " &
    "VCC     : (C6,  C7,  D4,  D5,  D8,  D9,  E4,  E9, " &
               "F4,  F9,  G4,  G9,  H4,  H9,  J4,  J5, " &
               "J8,  J9,  K6,  K7) ";

  -- Scan port identification

  attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, LOW);
  attribute TAP_SCAN_MODE of TMS : signal is true;
  attribute TAP_SCAN_IN of TDI : signal is true;
  attribute TAP_SCAN_RESET of TRSTB : signal is true;
  attribute TAP_SCAN_OUT of TDO : signal is true;


  -- Compliance patterns

  attribute COMPLIANCE_PATTERNS of IDT72V3680BB: entity is "(OEB, IW, OW) (000)";

  -- Instruction register description

  attribute INSTRUCTION_LENGTH of IDT72V3680BB: entity is 4;

  attribute INSTRUCTION_OPCODE of IDT72V3680BB: entity is
    "EXTEST     (0000)," &
    "SAMPLE     (0001)," &
    "IDCODE     (0010)," &
    "HIGHZ      (0011)," &
    "BYPASS     (1111)," &
    "PRIVATE    (0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110)";

  attribute INSTRUCTION_CAPTURE of IDT72V3680BB: entity is "1101";

  attribute INSTRUCTION_PRIVATE of IDT72V3680BB: entity is "PRIVATE";


  -- Optional register description

  attribute IDCODE_REGISTER of IDT72V3680BB: entity is
    "0001" &                -- version
    "0000010011100001" &    -- part number
    "00000110011" &         -- manufacturer's identity
    "1";                    -- required by 1149.1


  -- Register access description

  attribute REGISTER_ACCESS of IDT72V3680BB: entity is
    "BYPASS     (BYPASS, HIGHZ), " &
    "BOUNDARY   (SAMPLE, EXTEST), " &
    "DEVICE_ID  (IDCODE)";


  -- Boundary-Scan register description

  attribute BOUNDARY_LENGTH of IDT72V3680BB: entity is 99;

  attribute BOUNDARY_REGISTER of IDT72V3680BB: entity is
  --
  -- num    cell   port        function  safe [ccell disval rslt]
  --
      "0   (BC_1,  Q(0),        output2,  X), " &
      "1   (BC_1,  Q(1),        output2,  X), " &
      "2   (BC_1,  Q(2),        output2,  X), " &
      "3   (BC_1,  Q(3),        output2,  X), " &
      "4   (BC_1,  Q(4),        output2,  X), " &
      "5   (BC_1,  Q(5),        output2,  X), " &
      "6   (BC_1,  Q(6),        output2,  X), " &
      "7   (BC_1,  Q(7),        output2,  X), " &
      "8   (BC_1,  Q(8),        output2,  X), " &
      "9   (BC_1,  Q(9),        output2,  X), " &
     "10   (BC_1,  Q(10),       output2,  X), " &
     "11   (BC_1,  Q(11),       output2,  X), " &
     "12   (BC_1,  Q(12),       output2,  X), " &
     "13   (BC_1,  Q(13),       output2,  X), " &
     "14   (BC_1,  Q(14),       output2,  X), " &
     "15   (BC_1,  Q(15),       output2,  X), " &
     "16   (BC_1,  Q(16),       output2,  X), " &
     "17   (BC_1,  Q(17),       output2,  X), " &
     "18   (BC_1,  Q(18),       output2,  X), " &
     "19   (BC_1,  Q(19),       output2,  X), " &
     "20   (BC_1,  Q(20),       output2,  X), " &
     "21   (BC_1,  Q(21),       output2,  X), " &
     "22   (BC_1,  Q(22),       output2,  X), " &
     "23   (BC_1,  Q(23),       output2,  X), " &
     "24   (BC_1,  Q(24),       output2,  X), " &
     "25   (BC_1,  Q(25),       output2,  X), " &
     "26   (BC_1,  Q(26),       output2,  X), " &
     "27   (BC_1,  Q(27),       output2,  X), " &
     "28   (BC_1,  Q(28),       output2,  X), " &
     "29   (BC_1,  Q(29),       output2,  X), " &
     "30   (BC_1,  Q(30),       output2,  X), " &
     "31   (BC_1,  Q(31),       output2,  X), " &
     "32   (BC_1,  Q(32),       output2,  X), " &
     "33   (BC_1,  Q(33),       output2,  X), " &
     "34   (BC_1,  Q(34),       output2,  X), " &
     "35   (BC_1,  Q(35),       output2,  X), " &
  -- "36   (BC_4,  OEB,         input,    X), " &
     "36   (BC_4,  *,           internal, X), " &
     "37   (BC_4,  RTB,         input,    X), " &
     "38   (BC_4,  RENB,        input,    X), " &
     "39   (BC_4,  RCLK,        clock,    X), " &
     "40   (BC_4,  RM,          input,    X), " &
     "41   (BC_1,  EF,          output2,  X), " &
     "42   (BC_4,  PFM,         input,    X), " &
     "43   (BC_1,  PAE,         output2,  X), " &
     "44   (BC_4,  ASYRB,       input,    X), " &
     "45   (BC_4,  BM,          input,    X), " &
     "46   (BC_4,  IP,          input,    X), " &
     "47   (BC_4,  BEB,         input,    X), " &
     "48   (BC_4,  FSEL(1),     input,    X), " &
     "49   (BC_1,  HF,          output2,  X), " &
     "50   (BC_4,  FSEL(0),     input,    X), " &
  -- "51   (BC_4,  OW,          input,    X), " &
     "51   (BC_4,  *,           internal, X), " &
     "52   (BC_1,  PAF,         output2,  X), " &
     "53   (BC_1,  FF,          output2,  X), " &
     "54   (BC_4,  FWFTSI,      input,    X), " &
     "55   (BC_4,  LDB,         input,    X), " &
     "56   (BC_4,  MRSB,        input,    X), " &
     "57   (BC_4,  PRSB,        input,    X), " &
     "58   (BC_4,  WCLK,        clock,    X), " &
     "59   (BC_4,  WENB,        input,    X), " &
     "60   (BC_4,  ASYWB,       input,    X), " &
     "61   (BC_4,  SENB,        input,    X), " &
  -- "62   (BC_4,  IW,          input,    X), " &
     "62   (BC_4,  *,           internal, X), " &
     "63   (BC_4,  D(35),       input,    X), " &
     "64   (BC_4,  D(34),       input,    X), " &
     "65   (BC_4,  D(33),       input,    X), " &
     "66   (BC_4,  D(32),       input,    X), " &
     "67   (BC_4,  D(31),       input,    X), " &
     "68   (BC_4,  D(30),       input,    X), " &
     "69   (BC_4,  D(29),       input,    X), " &
     "70   (BC_4,  D(28),       input,    X), " &
     "71   (BC_4,  D(27),       input,    X), " &
     "72   (BC_4,  D(26),       input,    X), " &
     "73   (BC_4,  D(25),       input,    X), " &
     "74   (BC_4,  D(24),       input,    X), " &
     "75   (BC_4,  D(23),       input,    X), " &
     "76   (BC_4,  D(22),       input,    X), " &
     "77   (BC_4,  D(21),       input,    X), " &
     "78   (BC_4,  D(20),       input,    X), " &
     "79   (BC_4,  D(19),       input,    X), " &
     "80   (BC_4,  D(18),       input,    X), " &
     "81   (BC_4,  D(17),       input,    X), " &
     "82   (BC_4,  D(16),       input,    X), " &
     "83   (BC_4,  D(15),       input,    X), " &
     "84   (BC_4,  D(14),       input,    X), " &
     "85   (BC_4,  D(13),       input,    X), " &
     "86   (BC_4,  D(12),       input,    X), " &
     "87   (BC_4,  D(11),       input,    X), " &
     "88   (BC_4,  D(10),       input,    X), " &
     "89   (BC_4,  D(9),        input,    X), " &
     "90   (BC_4,  D(8),        input,    X), " &
     "91   (BC_4,  D(7),        input,    X), " &
     "92   (BC_4,  D(6),        input,    X), " &
     "93   (BC_4,  D(5),        input,    X), " &
     "94   (BC_4,  D(4),        input,    X), " &
     "95   (BC_4,  D(3),        input,    X), " &
     "96   (BC_4,  D(2),        input,    X), " &
     "97   (BC_4,  D(1),        input,    X), " &
     "98   (BC_4,  D(0),        input,    X)";
 
end IDT72V3680BB;