BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: TMS320TCI6618

-- ------------------------------------------------------------------------- --
-- BSDL Description for TMS320TCI6618 PG2.0                                  --
-- Revised 26 July 2012                                                     --
-- ------------------------------------------------------------------------- --
--                          IMPORTANT NOTICE                                 --
--  Texas Instruments and its subsidiaries (TI) reserve the right to make    --
--  changes to their products or to discontinue any product or service       --
--  without notice, and advise customers to obtain the latest version of     --
--  relevant information to verify, before placing orders, that information  --
--  being relied on is current and complete. All products are sold subject   --
--  to the terms and conditions of sale supplied at the time of order        --
--  acknowledgment, including those pertaining to warranty, patent infringe- --
--  ment, and limitation of liability.                                       --
--                                                                           --
--  TI warrants performance of its products to the specifications applicable --
--  at the time of sale in accordance with TI's standard warranty. Testing   --
--  and other quality control techniques are utilized to the extent TI deems --
--  necessary to support this warranty. Specific testing of all parameters   --
--  of each device is not necessarily performed, except those mandated by    --
--  government requirements.                                                 --
--                                                                           --
--  Customers are responsible for their applications using TI components.    --
--  In order to minimize risks associated with the customer's applications,  --
--  adequate design and operating safeguards must be provided by the         --
--  customer to minimize inherent or procedural hazards.                     --
--                                                                           --
--  TI assumes no liability for applications assistance or customer product  --
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--  express or implied, is granted under any patent right, copyright, mask   --
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--  beyond the parameters stated by TI for that product or service voids     --
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--                                                                           --
--  Also see: Standard Terms and Conditions of Sale for Semiconductor        --
--  Products. www.ti.com/sc/docs/stdterms.htm                                --
--                                                                           --
--  Mailing Address:                                                         --
--                                                                           --
--             Texas Instruments                                             --
--             Post Office Box 655303                                        --
--             Dallas, Texas 75265                                           --
--                                                                           --
--             Copyright � 2007, Texas Instruments Incorporated              --
-- ------------------------------------------------------------------------- --

entity TMS320TCI6618 is

  generic( PHYSICAL_PIN_MAP : string :=   "CYP" );

   PORT (
   ddrdqm0        	: INOUT    BIT;
   ddrdqm1        	: INOUT    BIT;
   ddrdqm2        	: INOUT    BIT;
   ddrdqm3        	: INOUT    BIT;
   ddrdqm4        	: INOUT    BIT;
   ddrdqm5        	: INOUT    BIT;
   ddrdqm6        	: INOUT    BIT;
   ddrdqm7        	: INOUT    BIT;
   ddrdqm8        	: INOUT    BIT;
   ddrdqs0p        	: INOUT    BIT;
   ddrdqs0n        	: INOUT    BIT;
   ddrdqs1p        	: INOUT    BIT;
   ddrdqs1n        	: INOUT    BIT;
   ddrdqs2p        	: INOUT    BIT;
   ddrdqs2n        	: INOUT    BIT;
   ddrdqs3p        	: INOUT    BIT;
   ddrdqs3n        	: INOUT    BIT;
   ddrdqs4p        	: INOUT    BIT;
   ddrdqs4n        	: INOUT    BIT;
   ddrdqs5p        	: INOUT    BIT;
   ddrdqs5n        	: INOUT    BIT;
   ddrdqs6p        	: INOUT    BIT;
   ddrdqs6n        	: INOUT    BIT;
   ddrdqs7p        	: INOUT    BIT;
   ddrdqs7n        	: INOUT    BIT;
   ddrdqs8p        	: INOUT    BIT;
   ddrdqs8n        	: INOUT    BIT;
   ddrcb00        	: INOUT    BIT;
   ddrcb01        	: INOUT    BIT;
   ddrcb02        	: INOUT    BIT;
   ddrcb03        	: INOUT    BIT;
   ddrcb04        	: INOUT    BIT;
   ddrcb05        	: INOUT    BIT;
   ddrcb06        	: INOUT    BIT;
   ddrcb07        	: INOUT    BIT;
   ddrd00        	: INOUT    BIT;
   ddrd01        	: INOUT    BIT;
   ddrd02        	: INOUT    BIT;
   ddrd03        	: INOUT    BIT;
   ddrd04        	: INOUT    BIT;
   ddrd05        	: INOUT    BIT;
   ddrd06        	: INOUT    BIT;
   ddrd07        	: INOUT    BIT;
   ddrd08        	: INOUT    BIT;
   ddrd09        	: INOUT    BIT;
   ddrd10        	: INOUT    BIT;
   ddrd11        	: INOUT    BIT;
   ddrd12        	: INOUT    BIT;
   ddrd13        	: INOUT    BIT;
   ddrd14        	: INOUT    BIT;
   ddrd15        	: INOUT    BIT;
   ddrd16        	: INOUT    BIT;
   ddrd17        	: INOUT    BIT;
   ddrd18        	: INOUT    BIT;
   ddrd19        	: INOUT    BIT;
   ddrd20        	: INOUT    BIT;
   ddrd21        	: INOUT    BIT;
   ddrd22        	: INOUT    BIT;
   ddrd23        	: INOUT    BIT;
   ddrd24        	: INOUT    BIT;
   ddrd25        	: INOUT    BIT;
   ddrd26        	: INOUT    BIT;
   ddrd27        	: INOUT    BIT;
   ddrd28        	: INOUT    BIT;
   ddrd29        	: INOUT    BIT;
   ddrd30        	: INOUT    BIT;
   ddrd31        	: INOUT    BIT;
   ddrd32        	: INOUT    BIT;
   ddrd33        	: INOUT    BIT;
   ddrd34        	: INOUT    BIT;
   ddrd35        	: INOUT    BIT;
   ddrd36        	: INOUT    BIT;
   ddrd37        	: INOUT    BIT;
   ddrd38        	: INOUT    BIT;
   ddrd39        	: INOUT    BIT;
   ddrd40        	: INOUT    BIT;
   ddrd41        	: INOUT    BIT;
   ddrd42        	: INOUT    BIT;
   ddrd43        	: INOUT    BIT;
   ddrd44        	: INOUT    BIT;
   ddrd45        	: INOUT    BIT;
   ddrd46        	: INOUT    BIT;
   ddrd47        	: INOUT    BIT;
   ddrd48        	: INOUT    BIT;
   ddrd49        	: INOUT    BIT;
   ddrd50        	: INOUT    BIT;
   ddrd51        	: INOUT    BIT;
   ddrd52        	: INOUT    BIT;
   ddrd53        	: INOUT    BIT;
   ddrd54        	: INOUT    BIT;
   ddrd55        	: INOUT    BIT;
   ddrd56        	: INOUT    BIT;
   ddrd57        	: INOUT    BIT;
   ddrd58        	: INOUT    BIT;
   ddrd59        	: INOUT    BIT;
   ddrd60        	: INOUT    BIT;
   ddrd61        	: INOUT    BIT;
   ddrd62        	: INOUT    BIT;
   ddrd63        	: INOUT    BIT;
   ddrce0z        	: INOUT    BIT;
   ddrce1z        	: INOUT    BIT;
   ddrba0        	: INOUT    BIT;
   ddrba1        	: INOUT    BIT;
   ddrba2        	: INOUT    BIT;
   ddra00        	: INOUT    BIT;
   ddra01        	: INOUT    BIT;
   ddra02        	: INOUT    BIT;
   ddra03        	: INOUT    BIT;
   ddra04        	: INOUT    BIT;
   ddra05        	: INOUT    BIT;
   ddra06        	: INOUT    BIT;
   ddra07        	: INOUT    BIT;
   ddra08        	: INOUT    BIT;
   ddra09        	: INOUT    BIT;
   ddra10        	: INOUT    BIT;
   ddra11        	: INOUT    BIT;
   ddra12        	: INOUT    BIT;
   ddra13        	: INOUT    BIT;
   ddra14        	: INOUT    BIT;
   ddra15        	: INOUT    BIT;
   ddrcasz        	: INOUT    BIT;
   ddrrasz        	: INOUT    BIT;
   ddrwez        	: INOUT    BIT;
   ddrcke0       	: INOUT    BIT;
   ddrcke1       	: INOUT    BIT;
   ddrclkoutp0        	: INOUT    BIT;
   ddrclkoutn0        	: INOUT    BIT;
   ddrclkoutp1        	: INOUT    BIT;
   ddrclkoutn1        	: INOUT    BIT;
   ddrodt0        	: INOUT    BIT;
   ddrodt1        	: INOUT    BIT;
   ddrresetz        	: INOUT    BIT;
   ddrslrate0        	: INOUT    BIT;
   ddrslrate1        	: INOUT    BIT;
   vrefsstl        	: LINKAGE  BIT;
   gpio00        	: INOUT    BIT;
   gpio01        	: INOUT    BIT;
   gpio02        	: INOUT    BIT;
   gpio03        	: INOUT    BIT;
   gpio04        	: INOUT    BIT;
   gpio05        	: INOUT    BIT;
   gpio06        	: INOUT    BIT;
   gpio07        	: INOUT    BIT;
   gpio08        	: INOUT    BIT;
   gpio09        	: INOUT    BIT;
   gpio10        	: INOUT    BIT;
   gpio11        	: INOUT    BIT;
   gpio12        	: INOUT    BIT;
   gpio13        	: INOUT    BIT;
   gpio14        	: INOUT    BIT;
   gpio15        	: INOUT    BIT;
   tck        		: IN       BIT;
   tdi        		: IN       BIT;
   tdo        		: OUT      BIT;
   tms        		: IN       BIT;
   trstz        	: IN       BIT;
   emu00        	: INOUT    BIT;
   emu01        	: INOUT    BIT;
   emu02        	: INOUT    BIT;
   emu03        	: INOUT    BIT;
   emu04        	: INOUT    BIT;
   emu05        	: INOUT    BIT;
   emu06        	: INOUT    BIT;
   emu07        	: INOUT    BIT;
   emu08        	: INOUT    BIT;
   emu09        	: INOUT    BIT;
   emu10        	: INOUT    BIT;
   emu11        	: INOUT    BIT;
   emu12        	: INOUT    BIT;
   emu13        	: INOUT    BIT;
   emu14        	: INOUT    BIT;
   emu15        	: INOUT    BIT;
   emu16        	: INOUT    BIT;
   emu17        	: INOUT    BIT;
   emu18        	: INOUT    BIT;
   paclksel    		: INOUT    BIT;
   scl        		: INOUT    BIT;
   sda        		: INOUT    BIT;
   timi0        	: INOUT    BIT;
   timi1        	: INOUT    BIT;
   timo0        	: INOUT    BIT;
   timo1        	: INOUT    BIT;
   spiscs0        	: INOUT    BIT;
   spiscs1        	: INOUT    BIT;
   spiclk        	: INOUT    BIT;
   spidin        	: INOUT    BIT;
   spidout        	: INOUT    BIT;
   sysclkp        	: IN       BIT;
   sysclkn        	: IN       BIT;
   passclkp        	: IN       BIT;
   passclkn        	: IN       BIT;
   altcoreclkp        	: IN       BIT;
   altcoreclkn        	: IN       BIT;
   sriosgmiiclkp        : IN       BIT;
   sriosgmiiclkn        : IN       BIT;
   ddrclkp        	: IN       BIT;
   ddrclkn        	: IN       BIT;
   pcieclkp        	: IN       BIT;
   pcieclkn        	: IN       BIT;
   mcmclkp        	: IN       BIT;
   mcmclkn        	: IN       BIT;
   avdda1        	: LINKAGE  BIT;
   avdda2        	: LINKAGE  BIT;
   avdda3        	: LINKAGE  BIT;
   sysclkout        	: INOUT    BIT;
   coreclksel        	: INOUT    BIT;
   hout        		: INOUT    BIT;
   nmiz        		: INOUT    BIT;
   lresetz        	: INOUT    BIT;
   lresetnmienz        	: INOUT    BIT;
   coresel0        	: INOUT    BIT;
   coresel1        	: INOUT    BIT;
   coresel2        	: INOUT    BIT;
   resetfullz        	: IN       BIT;
   resetz        	: IN       BIT;
   porz        		: IN       BIT;
   resetstatz        	: INOUT    BIT;
   bootcomplete        	: INOUT    BIT;
   ptv15        	: LINKAGE  BIT;
   vcl        		: INOUT    BIT;
   vd        		: INOUT    BIT;
   vcntl0        	: OUT      BIT;
   vcntl1        	: OUT      BIT;
   vcntl2        	: OUT      BIT;
   vcntl3        	: OUT      BIT;
   mcmrxn0        	: IN       BIT;
   mcmrxp0        	: IN       BIT;
   mcmrxn1        	: IN       BIT;
   mcmrxp1        	: IN       BIT;
   mcmrxn2        	: IN       BIT;
   mcmrxp2        	: IN       BIT;
   mcmrxn3        	: IN       BIT;
   mcmrxp3        	: IN       BIT;
   mcmtxn0        	: BUFFER   BIT;
   mcmtxp0        	: BUFFER   BIT;
   mcmtxn1        	: BUFFER   BIT;
   mcmtxp1        	: BUFFER   BIT;
   mcmtxn2        	: BUFFER   BIT;
   mcmtxp2        	: BUFFER   BIT;
   mcmtxn3        	: BUFFER   BIT;
   mcmtxp3        	: BUFFER   BIT;
   mcmrxflclk        	: INOUT    BIT;
   mcmrxfldat        	: INOUT    BIT;
   mcmtxflclk        	: INOUT    BIT;
   mcmtxfldat        	: INOUT    BIT;
   mcmrxpmclk        	: INOUT    BIT;
   mcmrxpmdat        	: INOUT    BIT;
   mcmtxpmclk        	: INOUT    BIT;
   mcmtxpmdat        	: INOUT    BIT;
   mcmrefclkoutp        : LINKAGE  BIT;
   mcmrefclkoutn        : LINKAGE  BIT;
   riorxn0        	: IN       BIT;
   riorxp0        	: IN       BIT;
   riorxn1        	: IN       BIT;
   riorxp1        	: IN       BIT;
   riorxn2        	: IN       BIT;
   riorxp2        	: IN       BIT;
   riorxn3        	: IN       BIT;
   riorxp3        	: IN       BIT;
   riotxn0        	: BUFFER   BIT;
   riotxp0        	: BUFFER   BIT;
   riotxn1        	: BUFFER   BIT;
   riotxp1        	: BUFFER   BIT;
   riotxn2        	: BUFFER   BIT;
   riotxp2        	: BUFFER   BIT;
   riotxn3        	: BUFFER   BIT;
   riotxp3        	: BUFFER   BIT;
   pcierxn0        	: IN       BIT;
   pcierxp0        	: IN       BIT;
   pcierxn1        	: IN       BIT;
   pcierxp1        	: IN       BIT;
   pcietxn0        	: BUFFER   BIT;
   pcietxp0        	: BUFFER   BIT;
   pcietxn1        	: BUFFER   BIT;
   pcietxp1        	: BUFFER   BIT;
   mdio        		: INOUT    BIT;
   mdclk        	: INOUT    BIT;
   sgmii0rxn        	: IN       BIT;
   sgmii0rxp        	: IN       BIT;
   sgmii0txn        	: BUFFER   BIT;
   sgmii0txp        	: BUFFER   BIT;
   sgmii1rxn        	: IN       BIT;
   sgmii1rxp        	: IN       BIT;
   sgmii1txn        	: BUFFER   BIT;
   sgmii1txp        	: BUFFER   BIT;
   uartrxd        	: INOUT    BIT;
   uarttxd        	: INOUT    BIT;
   uartcts        	: INOUT    BIT;
   uartrts        	: INOUT    BIT;
   aifrxn0        	: IN       BIT;
   aifrxp0        	: IN       BIT;
   aifrxn1        	: IN       BIT;
   aifrxp1        	: IN       BIT;
   aifrxn2        	: IN       BIT;
   aifrxp2        	: IN       BIT;
   aifrxn3        	: IN       BIT;
   aifrxp3        	: IN       BIT;
   aifrxn4        	: IN       BIT;
   aifrxp4        	: IN       BIT;
   aifrxn5        	: IN       BIT;
   aifrxp5        	: IN       BIT;
   aiftxn0        	: BUFFER   BIT;
   aiftxp0        	: BUFFER   BIT;
   aiftxn1        	: BUFFER   BIT;
   aiftxp1        	: BUFFER   BIT;
   aiftxn2        	: BUFFER   BIT;
   aiftxp2        	: BUFFER   BIT;
   aiftxn3        	: BUFFER   BIT;
   aiftxp3        	: BUFFER   BIT;
   aiftxn4        	: BUFFER   BIT;
   aiftxp4        	: BUFFER   BIT;
   aiftxn5        	: BUFFER   BIT;
   aiftxp5        	: BUFFER   BIT;
   rp1clkp        	: IN       BIT;
   rp1clkn        	: IN       BIT;
   extframeevent        : INOUT    BIT;
   rp1fbp        	: IN       BIT;
   rp1fbn        	: IN       BIT;
   physync        	: INOUT    BIT;
   radsync        	: INOUT    BIT;
   rsv01                : INOUT    BIT;
   rsv03                : INOUT    BIT;
   rsv04                : BUFFER   BIT;
   rsv05                : BUFFER   BIT;
   rsv06                : BUFFER   BIT;
   rsv07                : BUFFER   BIT;
   rsv08                : LINKAGE  BIT;
   rsv09                : LINKAGE  BIT;
   rsv0a                : LINKAGE  BIT;
   rsv0b                : LINKAGE  BIT;
   rsv10                : LINKAGE  BIT;
   rsv11                : LINKAGE  BIT;
   rsv12                : LINKAGE  BIT;
   rsv13                : LINKAGE  BIT;
   rsv14                : LINKAGE  BIT;
   rsv15                : LINKAGE  BIT;
   rsv16                : LINKAGE  BIT;
   rsv17                : LINKAGE  BIT;
   rsv18                : LINKAGE  BIT;
   rsv19                : LINKAGE  BIT;
   rsv20                : INOUT    BIT;
   rsv21                : INOUT    BIT;
   rsv22                : INOUT    BIT;
   rsv23                : LINKAGE  BIT;
   rsv24                : BUFFER   BIT;
   rsv25                : BUFFER   BIT;
   rsv26                : LINKAGE  BIT;
   rsv27                : LINKAGE  BIT;
   vddr1                : LINKAGE  BIT;
   vddr2                : LINKAGE  BIT;
   vddr3                : LINKAGE  BIT;
   vddr4                : LINKAGE  BIT;
   vddr5                : LINKAGE  BIT;
   vddr6                : LINKAGE  BIT;
   vddt1                : LINKAGE  BIT_VECTOR(7   downto 0);
   vddt2                : LINKAGE  BIT_VECTOR(12  downto 0);
   vddt3                : LINKAGE  BIT_VECTOR(11  downto 0);
   cvdd                 : LINKAGE  BIT_VECTOR(80  downto 0);
   cvdd1                : LINKAGE  BIT_VECTOR(42  downto 0);
   dvdd15               : LINKAGE  BIT_VECTOR(30  downto 0);
   dvdd18               : LINKAGE  BIT_VECTOR(17  downto 0);
   vss                  : LINKAGE  BIT_VECTOR(280 downto 0) 
  );
 use STD_1149_1_2001.all;           -- Standard 'use' statement
 use STD_1149_6_2003.all;           -- BSDL Extension for AIO
-- comments were added above on 16Feb2012

 attribute COMPONENT_CONFORMANCE of TMS320TCI6618 : entity is "STD_1149_1_2001";

 attribute      PIN_MAP          of TMS320TCI6618 : entity is PHYSICAL_PIN_MAP;
 constant CYP : PIN_MAP_STRING :=      
   "ddrdqm0                     : E29   ,"&
   "ddrdqm1                     : C27   ,"&
   "ddrdqm2                     : A25   ,"&
   "ddrdqm3                     : A22   ,"&
   "ddrdqm4                     : A10   ,"&
   "ddrdqm5                     : A8    ,"&
   "ddrdqm6                     : B5    ,"&
   "ddrdqm7                     : B2    ,"&
   "ddrdqm8                     : A20   ,"&
   "ddrdqs0p                    : C28   ,"&
   "ddrdqs0n                    : C29   ,"&
   "ddrdqs1p                    : A27   ,"&
   "ddrdqs1n                    : B27   ,"&
   "ddrdqs2p                    : A24   ,"&
   "ddrdqs2n                    : B24   ,"&
   "ddrdqs3p                    : A21   ,"&
   "ddrdqs3n                    : B21   ,"&
   "ddrdqs4p                    : A9    ,"&
   "ddrdqs4n                    : B9    ,"&
   "ddrdqs5p                    : B6    ,"&
   "ddrdqs5n                    : A6    ,"&
   "ddrdqs6p                    : B3    ,"&
   "ddrdqs6n                    : A3    ,"&
   "ddrdqs7p                    : D1    ,"&
   "ddrdqs7n                    : C1    ,"&
   "ddrdqs8p                    : A19   ,"&
   "ddrdqs8n                    : B19   ,"&
   "ddrcb00                     : E19   ,"&
   "ddrcb01                     : C20   ,"&
   "ddrcb02                     : D19   ,"&
   "ddrcb03                     : B20   ,"&
   "ddrcb04                     : C19   ,"&
   "ddrcb05                     : C18   ,"&
   "ddrcb06                     : B18   ,"&
   "ddrcb07                     : A18   ,"&
   "ddrd00                      : E28   ,"&
   "ddrd01                      : D29   ,"&
   "ddrd02                      : E27   ,"&
   "ddrd03                      : D28   ,"&
   "ddrd04                      : D27   ,"&
   "ddrd05                      : B28   ,"&
   "ddrd06                      : E26   ,"&
   "ddrd07                      : F25   ,"&
   "ddrd08                      : F24   ,"&
   "ddrd09                      : E24   ,"&
   "ddrd10                      : E25   ,"&
   "ddrd11                      : D25   ,"&
   "ddrd12                      : D26   ,"&
   "ddrd13                      : C26   ,"&
   "ddrd14                      : B26   ,"&
   "ddrd15                      : A26   ,"&
   "ddrd16                      : F23   ,"&
   "ddrd17                      : F22   ,"&
   "ddrd18                      : D24   ,"&
   "ddrd19                      : E23   ,"&
   "ddrd20                      : A23   ,"&
   "ddrd21                      : B23   ,"&
   "ddrd22                      : C24   ,"&
   "ddrd23                      : E22   ,"&
   "ddrd24                      : D21   ,"&
   "ddrd25                      : F20   ,"&
   "ddrd26                      : E21   ,"&
   "ddrd27                      : F21   ,"&
   "ddrd28                      : D22   ,"&
   "ddrd29                      : C21   ,"&
   "ddrd30                      : B22   ,"&
   "ddrd31                      : C22   ,"&
   "ddrd32                      : E10   ,"&
   "ddrd33                      : D10   ,"&
   "ddrd34                      : B10   ,"&
   "ddrd35                      : D9    ,"&
   "ddrd36                      : E9    ,"&
   "ddrd37                      : C9    ,"&
   "ddrd38                      : B8    ,"&
   "ddrd39                      : E8    ,"&
   "ddrd40                      : A7    ,"&
   "ddrd41                      : D7    ,"&
   "ddrd42                      : E7    ,"&
   "ddrd43                      : C7    ,"&
   "ddrd44                      : B7    ,"&
   "ddrd45                      : E6    ,"&
   "ddrd46                      : D6    ,"&
   "ddrd47                      : C6    ,"&
   "ddrd48                      : C5    ,"&
   "ddrd49                      : A5    ,"&
   "ddrd50                      : B4    ,"&
   "ddrd51                      : A4    ,"&
   "ddrd52                      : D4    ,"&
   "ddrd53                      : E4    ,"&
   "ddrd54                      : C4    ,"&
   "ddrd55                      : C3    ,"&
   "ddrd56                      : F4    ,"&
   "ddrd57                      : D2    ,"&
   "ddrd58                      : E2    ,"&
   "ddrd59                      : C2    ,"&
   "ddrd60                      : F2    ,"&
   "ddrd61                      : F3    ,"&
   "ddrd62                      : E1    ,"&
   "ddrd63                      : F1    ,"&
   "ddrce0z                     : C11   ,"&
   "ddrce1z                     : C12   ,"&
   "ddrba0                      : A13   ,"&
   "ddrba1                      : B13   ,"&
   "ddrba2                      : C13   ,"&
   "ddra00                      : A14   ,"&
   "ddra01                      : B14   ,"&
   "ddra02                      : F14   ,"&
   "ddra03                      : F13   ,"&
   "ddra04                      : A15   ,"&
   "ddra05                      : C15   ,"&
   "ddra06                      : B15   ,"&
   "ddra07                      : D15   ,"&
   "ddra08                      : F15   ,"&
   "ddra09                      : E15   ,"&
   "ddra10                      : E16   ,"&
   "ddra11                      : D16   ,"&
   "ddra12                      : E17   ,"&
   "ddra13                      : C16   ,"&
   "ddra14                      : D17   ,"&
   "ddra15                      : C17   ,"&
   "ddrcasz                     : D12   ,"&
   "ddrrasz                     : C10   ,"&
   "ddrwez                      : E12   ,"&
   "ddrcke0                     : D11   ,"&
   "ddrcke1                     : E18   ,"&
   "ddrclkoutp0                 : A12   ,"&
   "ddrclkoutn0                 : B12   ,"&
   "ddrclkoutp1                 : A16   ,"&
   "ddrclkoutn1                 : B16   ,"&
   "ddrodt0                     : D13   ,"&
   "ddrodt1                     : E13   ,"&
   "ddrresetz                   : E11   ,"&
   "ddrslrate0                  : H27   ,"&
   "ddrslrate1                  : H26   ,"&
   "vrefsstl                    : E14   ,"&
   "gpio00                      : AJ20  ,"&
   "gpio01                      : AG18  ,"&
   "gpio02                      : AD19  ,"&
   "gpio03                      : AE19  ,"&
   "gpio04                      : AF18  ,"&
   "gpio05                      : AE18  ,"&
   "gpio06                      : AG20  ,"&
   "gpio07                      : AH19  ,"&
   "gpio08                      : AJ19  ,"&
   "gpio09                      : AE21  ,"&
   "gpio10                      : AG19  ,"&
   "gpio11                      : AD20  ,"&
   "gpio12                      : AE20  ,"&
   "gpio13                      : AF21  ,"&
   "gpio14                      : AH20  ,"&
   "gpio15                      : AD21  ,"&
   "tck                         : AD29  ,"&
   "tdi                         : AD28  ,"&
   "tdo                         : AC27  ,"&
   "tms                         : AC26  ,"&
   "trstz                       : AD26  ,"&
   "emu00                       : AE29  ,"&
   "emu01                       : AF29  ,"&
   "emu02                       : AE28  ,"&
   "emu03                       : AF28  ,"&
   "emu04                       : AE26  ,"&
   "emu05                       : AD25  ,"&
   "emu06                       : AF25  ,"&
   "emu07                       : AE25  ,"&
   "emu08                       : AF27  ,"&
   "emu09                       : AG29  ,"&
   "emu10                       : AF26  ,"&
   "emu11                       : AG28  ,"&
   "emu12                       : AG27  ,"&
   "emu13                       : AG25  ,"&
   "emu14                       : AH28  ,"&
   "emu15                       : AJ27  ,"&
   "emu16                       : AH27  ,"&
   "emu17                       : AJ26  ,"&
   "emu18                       : AH25  ,"&
   "paclksel                    : AD23  ,"&
   "scl                         : AC17  ,"&
   "sda                         : AD17  ,"&
   "timi0                       : AJ23  ,"&
   "timi1                       : AG23  ,"&
   "timo0                       : AH23  ,"&
   "timo1                       : AF23  ,"&
   "spiscs0                     : AH21  ,"&
   "spiscs1                     : AJ22  ,"&
   "spiclk                      : AG21  ,"&
   "spidin                      : AH22  ,"&
   "spidout                     : AJ21  ,"&
   "sysclkp                     : AC29  ,"&
   "sysclkn                     : AC28  ,"&
   "passclkp                    : AJ18  ,"&
   "passclkn                    : AH18  ,"&
   "altcoreclkp                 : AB29  ,"&
   "altcoreclkn                 : AB28  ,"&
   "sriosgmiiclkn               : AH16  ,"&
   "sriosgmiiclkp               : AJ16  ,"&
   "ddrclkp                     : G29   ,"&
   "ddrclkn                     : H29   ,"&
   "pcieclkp                    : AH17  ,"&
   "pcieclkn                    : AJ17  ,"&
   "mcmclkp                     : W1    ,"&
   "mcmclkn                     : W2    ,"&
   "avdda1                      : W24   ,"&
   "avdda2                      : J26   ,"&
   "avdda3                      : AB15  ,"&
   "sysclkout                   : AA26  ,"&
   "coreclksel                  : AB25  ,"&
   "hout                        : AC18  ,"&
   "nmiz                        : AC25  ,"&
   "lresetz                     : AE22  ,"&
   "lresetnmienz                : AC20  ,"&
   "coresel0                    : AH15  ,"&
   "coresel1                    : AC16  ,"&
   "coresel2                    : AD15  ,"&
   "resetfullz                  : AE23  ,"&
   "resetz                      : AC24  ,"&
   "porz                        : AC19  ,"&
   "resetstatz                  : AD18  ,"&
   "bootcomplete                : AC21  ,"&
   "ptv15                       : H24   ,"&
   "vcl                         : Y4    ,"&
   "vd                          : W4    ,"&
   "vcntl0                      : AB4   ,"&
   "vcntl1                      : AB3   ,"&
   "vcntl2                      : AA4   ,"&
   "vcntl3                      : AB1   ,"&
   "mcmrxp0                     : R2    ,"&
   "mcmrxn0                     : T2    ,"&
   "mcmrxp1                     : R1    ,"&
   "mcmrxn1                     : P1    ,"&
   "mcmrxp2                     : M1    ,"&
   "mcmrxn2                     : L1    ,"&
   "mcmrxp3                     : M2    ,"&
   "mcmrxn3                     : N2    ,"&
   "mcmtxn0                     : T5    ,"&
   "mcmtxn1                     : R4    ,"&
   "mcmtxn2                     : L4    ,"&
   "mcmtxn3                     : M5    ,"&
   "mcmtxp0                     : R5    ,"&
   "mcmtxp1                     : P4    ,"&
   "mcmtxp2                     : M4    ,"&
   "mcmtxp3                     : N5    ,"&
   "mcmrxflclk                  : V3    ,"&
   "mcmrxfldat                  : W3    ,"&
   "mcmtxflclk                  : Y1    ,"&
   "mcmtxfldat                  : Y2    ,"&
   "mcmrxpmclk                  : AA3   ,"&
   "mcmrxpmdat                  : Y3    ,"&
   "mcmtxpmclk                  : AA2   ,"&
   "mcmtxpmdat                  : AA1   ,"&
   "mcmrefclkoutp               : V2    ,"&
   "mcmrefclkoutn               : V1    ,"&
   "riorxp0                     : AJ10  ,"&
   "riorxn0                     : AJ11  ,"&
   "riorxp1                     : AH9   ,"&
   "riorxn1                     : AH10  ,"&
   "riorxp2                     : AJ8   ,"&
   "riorxn2                     : AJ7   ,"&
   "riorxp3                     : AH7   ,"&
   "riorxn3                     : AH6   ,"&
   "riotxp0                     : AG10  ,"&
   "riotxn0                     : AG11  ,"&
   "riotxp1                     : AF10  ,"&
   "riotxn1                     : AF9   ,"&
   "riotxp2                     : AG8   ,"&
   "riotxn2                     : AG7   ,"&
   "riotxp3                     : AF7   ,"&
   "riotxn3                     : AF6   ,"&
   "pcierxp0                    : AJ13  ,"&
   "pcierxn0                    : AJ14  ,"&
   "pcierxp1                    : AH13  ,"&
   "pcierxn1                    : AH12  ,"&
   "pcietxp0                    : AG13  ,"&
   "pcietxn0                    : AG14  ,"&
   "pcietxp1                    : AF13  ,"&
   "pcietxn1                    : AF12  ,"&
   "mdio                        : AG16  ,"&
   "mdclk                       : AF16  ,"&
   "sgmii0rxn                   : AH3   ,"&
   "sgmii0rxp                   : AH4   ,"&
   "sgmii0txn                   : AF3   ,"&
   "sgmii0txp                   : AF4   ,"&
   "sgmii1rxn                   : AJ4   ,"&
   "sgmii1rxp                   : AJ5   ,"&
   "sgmii1txn                   : AG4   ,"&
   "sgmii1txp                   : AG5   ,"&
   "uartrxd                     : AF24  ,"&
   "uarttxd                     : AJ24  ,"&
   "uartcts                     : AH24  ,"&
   "uartrts                     : AG24  ,"&
   "aifrxp0                     : M28   ,"&
   "aifrxn0                     : L28   ,"&
   "aifrxp1                     : L29   ,"&
   "aifrxn1                     : K29   ,"&
   "aifrxp2                     : P28   ,"&
   "aifrxn2                     : R28   ,"&
   "aifrxp3                     : N29   ,"&
   "aifrxn3                     : P29   ,"&
   "aifrxp4                     : U29   ,"&
   "aifrxn4                     : T29   ,"&
   "aifrxp5                     : V28   ,"&
   "aifrxn5                     : U28   ,"&
   "aiftxp0                     : M26   ,"&
   "aiftxn0                     : L26   ,"&
   "aiftxp1                     : K27   ,"&
   "aiftxn1                     : L27   ,"&
   "aiftxp2                     : P26   ,"&
   "aiftxn2                     : R26   ,"&
   "aiftxp3                     : N27   ,"&
   "aiftxn3                     : P27   ,"&
   "aiftxp4                     : T27   ,"&
   "aiftxn4                     : U27   ,"&
   "aiftxp5                     : V26   ,"&
   "aiftxn5                     : U26   ,"&
   "rp1clkp                     : Y28   ,"&
   "rp1clkn                     : AA28  ,"&
   "extframeevent               : AE17  ,"&
   "rp1fbp                      : Y29   ,"&
   "rp1fbn                      : AA29  ,"&
   "physync                     : AB27  ,"&
   "radsync                     : AA27  ,"&
   "rsv01                       : AJ25  ,"&
   "rsv03                       : AC23  ,"&
   "rsv04                       : Y27   ,"&
   "rsv05                       : W27   ,"&
   "rsv06                       : J28   ,"&
   "rsv07                       : H28   ,"&
   "rsv08                       : J24   ,"&
   "rsv09                       : J25   ,"&
   "rsv0a                       : K24   ,"&
   "rsv0b                       : K23   ,"&
   "rsv10                       : H23   ,"&
   "rsv11                       : J23   ,"&
   "rsv12                       : AD22  ,"&
   "rsv13                       : AC22  ,"&
   "rsv14                       : V4    ,"&
   "rsv15                       : AE8   ,"&
   "rsv16                       : AE14  ,"&
   "rsv17                       : AE5   ,"&
   "rsv18                       : AA24  ,"&
   "rsv19                       : G27   ,"&
   "rsv20                       : AB26  ,"&
   "rsv21                       : G26   ,"&
   "rsv22                       : AE16  ,"&
   "rsv23                       : AD16  ,"&
   "rsv24                       : AG17  ,"&
   "rsv25                       : AF17  ,"&
   "rsv26                       : U25   ,"&
   "rsv27                       : L25   ,"&
   "vddr1                       : K6    ,"&
   "vddr2                       : AE15  ,"&
   "vddr3                       : AE6   ,"&
   "vddr4                       : AE11  ,"&
   "vddr5                       : R25   ,"&
   "vddr6                       : N25   ,"&
   "vddt1                       : ( M7  , N6  , P7  , R6  , T7  , V7  , W6  , Y7  ),    "&
   "vddt2                       : ( AC6 , AC8 , AC10, AC12, AC14, AD5 , AD7 , AD9 ,     "&
                                   "AD11, AD13, AE4 , AE10, AE12),                      "&
   "vddt3                       : ( K25 , L24 , M23 , M25 , N24 , P23 , P25 , R24 ,     "&
                                   "T23 , T25 , U24 , V25),                             "&
   "cvdd                        : ( H11 , H13 , H15 , H17 , H19 , H21 , J12 , J18 ,     "&
                                   "K11 , K19 , L12 , L18 , M11 , M13 , M15 , M17 ,     "&
                                   "M19 , N8  , N10 , N12 , N14 , N16 , N18 , N20 ,     "&
                                   "N22 , P9  , P11 , P13 , P15 , P17 , P19 , P21 ,     "&
                                   "R8  , R10 , R12 , R14 , R16 , R18 , R20 , R22 ,     "&
                                   "T9  , T11 , T13 , T15 , T17 , T19 , T21 , U8  ,     "&
                                   "U10 , U12 , U14 , U16 , U18 , U20 , U22 , V9  ,     "&
                                   "V11 , V13 , V15 , V17 , V19 , V21 , V23 , W8  ,     "&
                                   "W10 , W18 , W20 , W22 , Y9  , Y19 , Y21 , Y23 ,     "&
                                   "AA8 , AA10, AA12, AA14, AA16, AA18, AA20, AA22,     "&
                                   "AB23),                                              "&
   "cvdd1                       : ( G6  , H1  , H3  , H5  , H7  , H9  , J2  , J4  ,     "&
                                   "J6  , J8  , J10 , J14 , J16 , J20 , J22 , K7  ,     "&
                                   "K9  , K13 , K15 , K17 , K21 , L8  , L10 , L14 ,     "&
                                   "L16 , L20 , L22 , M9  , M21 , W12 , W14 , W16 ,     "&
                                   "Y11 , Y13 , Y15 , Y17 , AD1 , AD3 , AE2 , AF1 ,     "&
                                   "AG2 , AH1 , AJ2),                                   "&
   "dvdd15                      : ( A2  , A11 , A17 , A28 , B1  , B29 , C14 , C25 ,     "&
                                   "D5  , D8  , D20 , D23 , E3  , F5  , F7  , F9  ,     "&
                                   "F11 , F17 , F19 , F27 , G2  , G4  , G8  , G10 ,     "&
                                   "G12 , G14 , G16 , G18 , G20 , G22 , G24),           "&
   "dvdd18                      : ( G28 , H25 , V5  , Y5  , Y25 , AB5 , AB17, AB19,     "&
                                   "AB21, AC2 , AC4 , AE24, AE27, AF19, AF22, AH26,     "&
                                   "AH29, AJ28),                                        "&
   "vss                         : ( A1  , A29 , B11 , B17 , B25 , C8  , C23 , D3  ,     "&
                                   "D14 , D18 , E5  , E20 , F6  , F8  , F10 , F12 ,     "&
                                   "F16 , F18 , F26 , F28 , F29 , G1  , G3  , G5  ,     "&
                                   "G7  , G9  , G11 , G13 , G15 , G17 , G19 , G21 ,     "&
                                   "G23 , G25 , H2  , H4  , H6  , H8  , H10 , H12 ,     "&
                                   "H14 , H16 , H18 , H20 , H22 , J1  , J3  , J5  ,     "&
                                   "J7  , J9  , J11 , J13 , J15 , J17 , J19 , J21 ,     "&
                                   "J27 , J29 , K1  , K2  , K3  , K4  , K5  , K8  ,     "&
                                   "K10 , K12 , K14 , K16 , K18 , K20 , K22 , K26 ,     "&
                                   "K28 , L2  , L3  , L5  , L6  , L7  , L9  , L11 ,     "&
                                   "L13 , L15 , L17 , L19 , L21 , L23 , M3  , M6  ,     "&
                                   "M8  , M10 , M12 , M14 , M16 , M18 , M20 , M22 ,     "&
                                   "M24 , M27 , M29 , N1  , N3  , N4  , N7  , N9  ,     "&
                                   "N11 , N13 , N15 , N17 , N19 , N21 , N23 , N26 ,     "&
                                   "N28 , P2  , P3  , P5  , P6  , P8  , P10 , P12 ,     "&
                                   "P14 , P16 , P18 , P20 , P22 , P24 , R3  , R7  ,     "&
                                   "R9  , R11 , R13 , R15 , R17 , R19 , R21 , R23 ,     "&
                                   "R27 , R29 , T1  , T3  , T4  , T6  , T8  , T10 ,     "&
                                   "T12 , T14 , T16 , T18 , T20 , T22 , T24 , T26 ,     "&
                                   "T28 , U1  , U2  , U3  , U4  , U5  , U6  , U7  ,     "&
                                   "U9  , U11 , U13 , U15 , U17 , U19 , U21 , U23 ,     "&
                                   "V6  , V8  , V10 , V12 , V14 , V16 , V18 , V20 ,     "&
                                   "V22 , V24 , V27 , V29 , W5  , W7  , W9  , W11 ,     "&
                                   "W13 , W15 , W17 , W19 , W21 , W23 , W25 , W26 ,     "&
                                   "W28 , W29 , Y6  , Y8  , Y10 , Y12 , Y14 , Y16 ,     "&
                                   "Y18 , Y20 , Y22 , Y24 , Y26 , AA5 , AA6 , AA7 ,     "&
                                   "AA9 , AA11, AA13, AA15, AA17, AA19, AA21, AA23,     "&
                                   "AA25, AB2 , AB6 , AB7 , AB8 , AB9 , AB10, AB11,     "&
                                   "AB12, AB13, AB14, AB16, AB18, AB20, AB22, AB24,     "&
                                   "AC1 , AC3 , AC5 , AC7 , AC9 , AC11, AC13, AC15,     "&
                                   "AD2 , AD4 , AD6 , AD8 , AD10, AD12, AD14, AD24,     "&
                                   "AD27, AE1 , AE3 , AE7 , AE9 , AE13, AF2 , AF5 ,     "&
                                   "AF8 , AF11, AF14, AF15, AF20, AG1 , AG3 , AG6 ,     "&
                                   "AG9 , AG12, AG15, AG22, AG26, AH2 , AH5 , AH8 ,     "&
                                   "AH11, AH14, AJ1 , AJ3 , AJ6 , AJ9 , AJ12, AJ15,     "&
                                   "AJ29)                                               ";

 attribute PORT_GROUPING of TMS320TCI6618 : entity is
    "Differential_Voltage  (            "&
    "(mcmrxp0, mcmrxn0),   	        "&
    "(mcmrxp1, mcmrxn1),   	        "&
    "(mcmrxp2, mcmrxn2),   	        "&
    "(mcmrxp3, mcmrxn3),   	        "&
    "(mcmtxp0, mcmtxn0),   	        "&
    "(mcmtxp1, mcmtxn1),   	        "&
    "(mcmtxp2, mcmtxn2),   	        "&
    "(mcmtxp3, mcmtxn3),   	        "&
    "(riorxp0, riorxn0),   	        "&
    "(riorxp1, riorxn1),   	        "&
    "(riorxp2, riorxn2),   	        "&
    "(riorxp3, riorxn3),   	        "&
    "(riotxp0, riotxn0),   	        "&
    "(riotxp1, riotxn1),   	        "&
    "(riotxp2, riotxn2),   	        "&
    "(riotxp3, riotxn3),   	        "&
    "(pcierxp0, pcierxn0),   	        "&
    "(pcierxp1, pcierxn1),   	        "&
    "(pcietxp0, pcietxn0),   	        "&
    "(pcietxp1, pcietxn1),   	        "&
    "(sgmii0rxp, sgmii0rxn),   	        "&
    "(sgmii1rxp, sgmii1rxn),   	        "&
    "(sgmii0txp, sgmii0txn),   	        "&
    "(sgmii1txp, sgmii1txn),   	        "&
    "(aifrxp0, aifrxn0),   	        "&
    "(aifrxp1, aifrxn1),   	        "&
    "(aifrxp2, aifrxn2),   	        "&
    "(aifrxp3, aifrxn3),   	        "&
    "(aifrxp4, aifrxn4),   	        "&
    "(aifrxp5, aifrxn5),   	        "&
    "(aiftxp0, aiftxn0),   	        "&
    "(aiftxp1, aiftxn1),   	        "&
    "(aiftxp2, aiftxn2),   	        "&
    "(aiftxp3, aiftxn3),   	        "&
    "(aiftxp4, aiftxn4),   	        "&
    "(aiftxp5, aiftxn5),   	        "&
    "(rp1clkp, rp1clkn),   	        "&
    "(rp1fbp, rp1fbn),   	        "&
    "(sysclkp, sysclkn),   	        "&
    "(passclkp, passclkn),   	        "&
    "(altcoreclkp, altcoreclkn),        "&
    "(sriosgmiiclkp, sriosgmiiclkn),    "&
    "(ddrclkp, ddrclkn),   	        "&
    "(pcieclkp, pcieclkn),   	        "&
    "(mcmclkp, mcmclkn),   	        "&
    "(ddrdqs8p, ddrdqs8n),   	        "&
    "(ddrdqs7p, ddrdqs7n),   	        "&
    "(ddrdqs6p, ddrdqs6n),   	        "&
    "(ddrdqs5p, ddrdqs5n),   	        "&
    "(ddrdqs4p, ddrdqs4n),   	        "&
    "(ddrdqs3p, ddrdqs3n),   	        "&
    "(ddrdqs2p, ddrdqs2n),   	        "&
    "(ddrdqs1p, ddrdqs1n),   	        "&
    "(ddrdqs0p, ddrdqs0n),   	        "&
    "(rsv04, rsv05),                    "&
    "(rsv06, rsv07),                    "&
    "(rsv24, rsv25))                    "; 

attribute TAP_SCAN_IN    of tdi    : signal is true;
attribute TAP_SCAN_MODE  of tms    : signal is true;
attribute TAP_SCAN_OUT   of tdo    : signal is true;
attribute TAP_SCAN_CLOCK of tck    : signal is (20.0e6,BOTH);
attribute TAP_SCAN_RESET of trstz  : signal is true;

attribute COMPLIANCE_PATTERNS of TMS320TCI6618 : entity is "(porz, resetfullz)(11)";
attribute INSTRUCTION_LENGTH  of TMS320TCI6618 : entity is 6;
attribute INSTRUCTION_OPCODE  of TMS320TCI6618 : entity is 
      "private_0       (000010),      "&
      "IDCODE          (000100),      "&
      "private_1       (000101),      "&
      "private_2       (000111),      "&
      "private_3       (001000),      "&
      "private_4       (010111),      "&
      "EXTEST          (011000),      "&
      "private_5       (011001),      "&
      "private_6       (011010),      "&
      "SAMPLE          (011011),      "&
      "PRELOAD         (011100),      "&
      "private_7       (011101),      "&
      "private_8       (011110),      "&
      "private_9       (011111),      "&
      "EXTEST_PULSE    (100100),      "&
      "EXTEST_TRAIN    (100101),      "&
      "private_a       (110001),      "&
      "BYPASS          (000000,111111)";   

 attribute INSTRUCTION_CAPTURE of TMS320TCI6618 : entity is "000001";

 attribute INSTRUCTION_PRIVATE of TMS320TCI6618 : entity is
      "private_0,   " &
      "private_1,   " &
      "private_2,   " &
      "private_3,   " &
      "private_4,   " &
      "private_5,   " &
      "private_6,   " &
      "private_7,   " &
      "private_8,   " &
      "private_9,   " &
      "private_a    ";

 attribute IDCODE_REGISTER     of TMS320TCI6618 : entity is
      "0001" &
      "1011100101000001" &
      "00000010111" &
      "1";

 attribute REGISTER_ACCESS of TMS320TCI6618 : entity is
      "BOUNDARY      (EXTEST),        "&
      "BOUNDARY      (SAMPLE),        "&
      "BOUNDARY      (PRELOAD),       "&
      "DEVICE_ID     (IDCODE),        "&
      "GEN_REG32[32] (private_1),     "&
      "GEN_REG1[1]   (private_0),     "&
      "GEN_REG8[8]   (private_2),     "&
      "GEN_REG32[32] (private_3),     "&
      "GEN_REG1[1]   (private_4),     "&
      "GEN_REG1[1]   (private_5),     "&
      "GEN_REG1[1]   (private_6),     "&
      "GEN_REG1[1]   (private_7),     "&
      "GEN_REG1[1]   (private_8),     "&
      "GEN_REG1[1]   (private_9),     "&
      "BOUNDARY      (EXTEST_PULSE),  "&
      "BOUNDARY      (EXTEST_TRAIN),  "&
      "GEN_REG1[1]   (private_a),     "&
      "BYPASS        (BYPASS)         ";

  attribute BOUNDARY_LENGTH of TMS320TCI6618 : entity is 468;

attribute BOUNDARY_REGISTER of TMS320TCI6618 : entity is
     " 467 (AC_SELU, *          ,  internal       , 0                  ),"&
     " 466 (BC_4, aifrxn4       ,  observe_only   , X                  ),"&
     " 465 (BC_4, aifrxp4       ,  observe_only   , X                  ),"&
     " 464 (BC_4, aifrxn5       ,  observe_only   , X                  ),"&
     " 463 (BC_4, aifrxp5       ,  observe_only   , X                  ),"&
     " 462 (AC_1, aiftxp4       ,  output2        , X                  ),"&
     " 461 (AC_1, aiftxp5       ,  output2        , X                  ),"&
     " 460 (BC_4, aifrxn0       ,  observe_only   , X                  ),"&
     " 459 (BC_4, aifrxp0       ,  observe_only   , X                  ),"&
     " 458 (BC_4, aifrxn1       ,  observe_only   , X                  ),"&
     " 457 (BC_4, aifrxp1       ,  observe_only   , X                  ),"&
     " 456 (BC_4, aifrxn2       ,  observe_only   , X                  ),"&
     " 455 (BC_4, aifrxp2       ,  observe_only   , X                  ),"&
     " 454 (BC_4, aifrxn3       ,  observe_only   , X                  ),"&
     " 453 (BC_4, aifrxp3       ,  observe_only   , X                  ),"&
     " 452 (AC_1, aiftxp0       ,  output2        , X                  ),"&
     " 451 (AC_1, aiftxp1       ,  output2        , X                  ),"&
     " 450 (AC_1, aiftxp2       ,  output2        , X                  ),"&
     " 449 (AC_1, aiftxp3       ,  output2        , X                  ),"&
     " 448 (BC_4, pcierxn0      ,  observe_only   , X                  ),"&
     " 447 (BC_4, pcierxp0      ,  observe_only   , X                  ),"&
     " 446 (BC_4, pcierxn1      ,  observe_only   , X                  ),"&
     " 445 (BC_4, pcierxp1      ,  observe_only   , X                  ),"&
     " 444 (AC_1, pcietxp0      ,  output2        , X                  ),"&
     " 443 (AC_1, pcietxp1      ,  output2        , X                  ),"&
     " 442 (BC_4, sgmii0rxn     ,  observe_only   , X                  ),"&
     " 441 (BC_4, sgmii0rxp     ,  observe_only   , X                  ),"&
     " 440 (BC_4, sgmii1rxn     ,  observe_only   , X                  ),"&
     " 439 (BC_4, sgmii1rxp     ,  observe_only   , X                  ),"&
     " 438 (AC_1, sgmii0txp     ,  output2        , X                  ),"&
     " 437 (AC_1, sgmii1txp     ,  output2        , X                  ),"&
     " 436 (BC_4, riorxn0       ,  observe_only   , X                  ),"&
     " 435 (BC_4, riorxp0       ,  observe_only   , X                  ),"&
     " 434 (BC_4, riorxn1       ,  observe_only   , X                  ),"&
     " 433 (BC_4, riorxp1       ,  observe_only   , X                  ),"&
     " 432 (BC_4, riorxn2       ,  observe_only   , X                  ),"&
     " 431 (BC_4, riorxp2       ,  observe_only   , X                  ),"&
     " 430 (BC_4, riorxn3       ,  observe_only   , X                  ),"&
     " 429 (BC_4, riorxp3       ,  observe_only   , X                  ),"&
     " 428 (AC_1, riotxp0       ,  output2        , X                  ),"&
     " 427 (AC_1, riotxp1       ,  output2        , X                  ),"&
     " 426 (AC_1, riotxp2       ,  output2        , X                  ),"&
     " 425 (AC_1, riotxp3       ,  output2        , X                  ),"&
     " 424 (BC_4, mcmrxn0       ,  observe_only   , X                  ),"&
     " 423 (BC_4, mcmrxp0       ,  observe_only   , X                  ),"&
     " 422 (BC_4, mcmrxn1       ,  observe_only   , X                  ),"&
     " 421 (BC_4, mcmrxp1       ,  observe_only   , X                  ),"&
     " 420 (BC_4, mcmrxn2       ,  observe_only   , X                  ),"&
     " 419 (BC_4, mcmrxp2       ,  observe_only   , X                  ),"&
     " 418 (BC_4, mcmrxn3       ,  observe_only   , X                  ),"&
     " 417 (BC_4, mcmrxp3       ,  observe_only   , X                  ),"&
     " 416 (AC_1, mcmtxp0       ,  output2        , X                  ),"&
     " 415 (AC_1, mcmtxp1       ,  output2        , X                  ),"&
     " 414 (AC_1, mcmtxp2       ,  output2        , X                  ),"&
     " 413 (AC_1, mcmtxp3       ,  output2        , X                  ),"&
     " 412 (BC_7, ddrslrate0    ,  bidir          , X,  411, 1, PULL0  ),"&
     " 411 (BC_2, *             ,  control        , 1                  ),"&
     " 410 (BC_7, ddrslrate1    ,  bidir          , X,  409, 1, PULL0  ),"&
     " 409 (BC_2, *             ,  control        , 1                  ),"&
     " 408 (BC_7, gpio00        ,  bidir          , X,  407, 1, PULL1  ),"&
     " 407 (BC_2, *             ,  control        , 1                  ),"&
     " 406 (BC_7, gpio01        ,  bidir          , X,  405, 1, PULL0  ),"&
     " 405 (BC_2, *             ,  control        , 1                  ),"&
     " 404 (BC_7, gpio02        ,  bidir          , X,  403, 1, PULL0  ),"&
     " 403 (BC_2, *             ,  control        , 1                  ),"&
     " 402 (BC_7, gpio03        ,  bidir          , X,  401, 1, PULL0  ),"&
     " 401 (BC_2, *             ,  control        , 1                  ),"&
     " 400 (BC_7, gpio04        ,  bidir          , X,  399, 1, PULL0  ),"&
     " 399 (BC_2, *             ,  control        , 1                  ),"&
     " 398 (BC_7, gpio05        ,  bidir          , X,  397, 1, PULL0  ),"&
     " 397 (BC_2, *             ,  control        , 1                  ),"&
     " 396 (BC_7, gpio06        ,  bidir          , X,  395, 1, PULL0  ),"&
     " 395 (BC_2, *             ,  control        , 1                  ),"&
     " 394 (BC_7, gpio07        ,  bidir          , X,  393, 1, PULL0  ),"&
     " 393 (BC_2, *             ,  control        , 1                  ),"&
     " 392 (BC_7, gpio08        ,  bidir          , X,  391, 1, PULL0  ),"&
     " 391 (BC_2, *             ,  control        , 1                  ),"&
     " 390 (BC_7, gpio09        ,  bidir          , X,  389, 1, PULL0  ),"&
     " 389 (BC_2, *             ,  control        , 1                  ),"&
     " 388 (BC_7, gpio10        ,  bidir          , X,  387, 1, PULL0  ),"&
     " 387 (BC_2, *             ,  control        , 1                  ),"&
     " 386 (BC_7, gpio11        ,  bidir          , X,  385, 1, PULL0  ),"&
     " 385 (BC_2, *             ,  control        , 1                  ),"&
     " 384 (BC_7, gpio12        ,  bidir          , X,  383, 1, PULL0  ),"&
     " 383 (BC_2, *             ,  control        , 1                  ),"&
     " 382 (BC_7, gpio13        ,  bidir          , X,  381, 1, PULL0  ),"&
     " 381 (BC_2, *             ,  control        , 1                  ),"&
     " 380 (BC_7, gpio14        ,  bidir          , X,  379, 1, PULL0  ),"&
     " 379 (BC_2, *             ,  control        , 1                  ),"&
     " 378 (BC_7, gpio15        ,  bidir          , X,  377, 1, PULL0  ),"&
     " 377 (BC_2, *             ,  control        , 1                  ),"&
     " 376 (BC_7, emu00         ,  bidir          , X,  375, 1, PULL1  ),"&
     " 375 (BC_2, *             ,  control        , 1                  ),"&
     " 374 (BC_7, emu01         ,  bidir          , X,  373, 1, PULL1  ),"&
     " 373 (BC_2, *             ,  control        , 1                  ),"&
     " 372 (BC_7, emu02         ,  bidir          , X,  371, 1, PULL1  ),"&
     " 371 (BC_2, *             ,  control        , 1                  ),"&
     " 370 (BC_7, emu03         ,  bidir          , X,  369, 1, PULL1  ),"&
     " 369 (BC_2, *             ,  control        , 1                  ),"&
     " 368 (BC_7, emu04         ,  bidir          , X,  367, 1, PULL1  ),"&
     " 367 (BC_2, *             ,  control        , 1                  ),"&
     " 366 (BC_7, emu05         ,  bidir          , X,  365, 1, PULL1  ),"&
     " 365 (BC_2, *             ,  control        , 1                  ),"&
     " 364 (BC_7, emu06         ,  bidir          , X,  363, 1, PULL1  ),"&
     " 363 (BC_2, *             ,  control        , 1                  ),"&
     " 362 (BC_7, emu07         ,  bidir          , X,  361, 1, PULL1  ),"&
     " 361 (BC_2, *             ,  control        , 1                  ),"&
     " 360 (BC_7, emu08         ,  bidir          , X,  359, 1, PULL1  ),"&
     " 359 (BC_2, *             ,  control        , 1                  ),"&
     " 358 (BC_7, emu09         ,  bidir          , X,  357, 1, PULL1  ),"&
     " 357 (BC_2, *             ,  control        , 1                  ),"&
     " 356 (BC_7, emu10         ,  bidir          , X,  355, 1, PULL1  ),"&
     " 355 (BC_2, *             ,  control        , 1                  ),"&
     " 354 (BC_7, emu11         ,  bidir          , X,  353, 1, PULL1  ),"&
     " 353 (BC_2, *             ,  control        , 1                  ),"&
     " 352 (BC_7, emu12         ,  bidir          , X,  351, 1, PULL1  ),"&
     " 351 (BC_2, *             ,  control        , 1                  ),"&
     " 350 (BC_7, emu13         ,  bidir          , X,  349, 1, PULL1  ),"&
     " 349 (BC_2, *             ,  control        , 1                  ),"&
     " 348 (BC_7, emu14         ,  bidir          , X,  347, 1, PULL1  ),"&
     " 347 (BC_2, *             ,  control        , 1                  ),"&
     " 346 (BC_7, emu15         ,  bidir          , X,  345, 1, PULL1  ),"&
     " 345 (BC_2, *             ,  control        , 1                  ),"&
     " 344 (BC_7, emu16         ,  bidir          , X,  343, 1, PULL1  ),"&
     " 343 (BC_2, *             ,  control        , 1                  ),"&
     " 342 (BC_7, emu17         ,  bidir          , X,  341, 1, PULL1  ),"&
     " 341 (BC_2, *             ,  control        , 1                  ),"&
     " 340 (BC_7, emu18         ,  bidir          , X,  339, 1, PULL1  ),"&
     " 339 (BC_2, *             ,  control        , 1                  ),"&
     " 338 (BC_7, rsv01         ,  bidir          , X,  337, 1, PULL0  ),"&
     " 337 (BC_2, *             ,  control        , 1                  ),"&
     " 336 (BC_7, paclksel      ,  bidir          , X,  335, 1, PULL0  ),"&
     " 335 (BC_2, *             ,  control        , 1                  ),"&
     " 334 (BC_7, rsv03         ,  bidir          , X,  333, 1, PULL0  ),"&
     " 333 (BC_2, *             ,  control        , 1                  ),"&
     " 332 (BC_1, scl           ,  output2        , 1,  332, 1, WEAK1  ),"&
     " 331 (BC_1, *             ,  internal       , 0                  ),"&
     " 330 (BC_3, scl           ,  input          , X                  ),"&
     " 329 (BC_1, sda           ,  output2        , 1,  329, 1, WEAK1  ),"&
     " 328 (BC_1, *             ,  internal       , 0                  ),"&
     " 327 (BC_3, sda           ,  input          , X                  ),"&
     " 326 (BC_7, timi0         ,  bidir          , X,  325, 1, PULL0  ),"&
     " 325 (BC_2, *             ,  control        , 1                  ),"&
     " 324 (BC_7, timi1         ,  bidir          , X,  323, 1, PULL0  ),"&
     " 323 (BC_2, *             ,  control        , 1                  ),"&
     " 322 (BC_7, timo0         ,  bidir          , X,  321, 1, PULL0  ),"&
     " 321 (BC_2, *             ,  control        , 1                  ),"&
     " 320 (BC_7, timo1         ,  bidir          , X,  319, 1, PULL0  ),"&
     " 319 (BC_2, *             ,  control        , 1                  ),"&
     " 318 (BC_7, spiscs0       ,  bidir          , X,  317, 1, PULL1  ),"&
     " 317 (BC_2, *             ,  control        , 1                  ),"&
     " 316 (BC_7, spiscs1       ,  bidir          , X,  315, 1, PULL1  ),"&
     " 315 (BC_2, *             ,  control        , 1                  ),"&
     " 314 (BC_7, spiclk        ,  bidir          , X,  313, 1, PULL0  ),"&
     " 313 (BC_2, *             ,  control        , 1                  ),"&
     " 312 (BC_7, spidin        ,  bidir          , X,  311, 1, PULL0  ),"&
     " 311 (BC_2, *             ,  control        , 1                  ),"&
     " 310 (BC_7, spidout       ,  bidir          , X,  309, 1, PULL0  ),"&
     " 309 (BC_2, *             ,  control        , 1                  ),"&
     " 308 (BC_1, sysclkp       ,  input          , X                  ),"&
     " 307 (BC_1, passclkp      ,  input          , X                  ),"&
     " 306 (BC_1, altcoreclkp   ,  input          , X                  ),"&
     " 305 (BC_1, sriosgmiiclkp ,  input          , X                  ),"&
     " 304 (BC_1, ddrclkp       ,  input          , X                  ),"&
     " 303 (BC_1, pcieclkp      ,  input          , X                  ),"&
     " 302 (BC_1, mcmclkp       ,  input          , X                  ),"&
     " 301 (BC_7, sysclkout     ,  bidir          , X,  300, 1, PULL0  ),"&
     " 300 (BC_2, *             ,  control        , 1                  ),"&
     " 299 (BC_7, coreclksel    ,  bidir          , X,  298, 1, PULL0  ),"&
     " 298 (BC_2, *             ,  control        , 1                  ),"&
     " 297 (BC_7, hout          ,  bidir          , X,  296, 1, PULL1  ),"&
     " 296 (BC_2, *             ,  control        , 1                  ),"&
     " 295 (BC_7, nmiz          ,  bidir          , X,  294, 1, PULL1  ),"&
     " 294 (BC_2, *             ,  control        , 1                  ),"&
     " 293 (BC_7, lresetz       ,  bidir          , X,  292, 1, PULL1  ),"&
     " 292 (BC_2, *             ,  control        , 1                  ),"&
     " 291 (BC_7, lresetnmienz  ,  bidir          , X,  290, 1, PULL1  ),"&
     " 290 (BC_2, *             ,  control        , 1                  ),"&
     " 289 (BC_7, coresel0      ,  bidir          , X,  288, 1, PULL0  ),"&
     " 288 (BC_2, *             ,  control        , 1                  ),"&
     " 287 (BC_7, coresel1      ,  bidir          , X,  286, 1, PULL0  ),"&
     " 286 (BC_2, *             ,  control        , 1                  ),"&
     " 285 (BC_7, coresel2      ,  bidir          , X,  284, 1, PULL0  ),"&
     " 284 (BC_2, *             ,  control        , 1                  ),"&
     " 283 (BC_1, resetz        ,  input          , X                  ),"&
     " 282 (BC_7, resetstatz    ,  bidir          , X,  281, 1, PULL1  ),"&
     " 281 (BC_2, *             ,  control        , 1                  ),"&
     " 280 (BC_7, bootcomplete  ,  bidir          , X,  279, 1, PULL0  ),"&
     " 279 (BC_2, *             ,  control        , 1                  ),"&
     " 278 (BC_1, rsv04         ,  output2        , X                  ),"&
     " 277 (BC_1, rsv06         ,  output2        , X                  ),"&
     " 276 (BC_1, rsv24         ,  output2        , X                  ),"&
     " 275 (BC_7, rsv20         ,  bidir          , X,  274, 1, PULL0  ),"&
     " 274 (BC_2, *             ,  control        , 1                  ),"&
     " 273 (BC_7, rsv21         ,  bidir          , X,  272, 1, PULL0  ),"&
     " 272 (BC_2, *             ,  control        , 1                  ),"&
     " 271 (BC_7, rsv22         ,  bidir          , X,  270, 1, PULL0  ),"&
     " 270 (BC_2, *             ,  control        , 1                  ),"&
     " 269 (BC_1, vcl           ,  output2        , 1,  269, 1, WEAK1  ),"&
     " 268 (BC_1, *             ,  internal       , 0                  ),"&
     " 267 (BC_3, vcl           ,  input          , X                  ),"&
     " 266 (BC_1, vd            ,  output2        , 1,  266, 1, WEAK1  ),"&
     " 265 (BC_1, *             ,  internal       , 0                  ),"&
     " 264 (BC_3, vd            ,  input          , X                  ),"&
     " 263 (BC_1, vcntl0        ,  output2        , 1,  263, 1, WEAK1  ),"&
     " 262 (BC_1, *             ,  internal       , 0                  ),"&
     " 261 (BC_4, vcntl0        ,  observe_only   , X                  ),"&
     " 260 (BC_1, vcntl1        ,  output2        , 1,  260, 1, WEAK1  ),"&
     " 259 (BC_1, *             ,  internal       , 0                  ),"&
     " 258 (BC_4, vcntl1        ,  observe_only   , X                  ),"&
     " 257 (BC_1, vcntl2        ,  output2        , 1,  257, 1, WEAK1  ),"&
     " 256 (BC_1, *             ,  internal       , 0                  ),"&
     " 255 (BC_4, vcntl2        ,  observe_only   , X                  ),"&
     " 254 (BC_1, vcntl3        ,  output2        , 1,  254, 1, WEAK1  ),"&
     " 253 (BC_1, *             ,  internal       , 0                  ),"&
     " 252 (BC_4, vcntl3        ,  observe_only   , X                  ),"&
     " 251 (BC_7, mcmrxflclk    ,  bidir          , X,  250 , 1, PULL0 ),"&
     " 250 (BC_2, *             ,  control        , 1                  ),"&
     " 249 (BC_7, mcmrxfldat    ,  bidir          , X,  248 , 1, PULL0 ),"&
     " 248 (BC_2, *             ,  control        , 1                  ),"&
     " 247 (BC_7, mcmtxflclk    ,  bidir          , X,  246 , 1, PULL0 ),"&
     " 246 (BC_2, *             ,  control        , 1                  ),"&
     " 245 (BC_7, mcmtxfldat    ,  bidir          , X,  244 , 1, PULL0 ),"&
     " 244 (BC_2, *             ,  control        , 1                  ),"&
     " 243 (BC_7, mcmrxpmclk    ,  bidir          , X,  242 , 1, PULL0 ),"&
     " 242 (BC_2, *             ,  control        , 1                  ),"&
     " 241 (BC_7, mcmrxpmdat    ,  bidir          , X,  240 , 1, PULL0 ),"&
     " 240 (BC_2, *             ,  control        , 1                  ),"&
     " 239 (BC_7, mcmtxpmclk    ,  bidir          , X,  238 , 1, PULL0 ),"&
     " 238 (BC_2, *             ,  control        , 1                  ),"&
     " 237 (BC_7, mcmtxpmdat    ,  bidir          , X,  236 , 1, PULL0 ),"&
     " 236 (BC_2, *             ,  control        , 1                  ),"&
     " 235 (BC_7, mdio          ,  bidir          , X,  234 , 1, PULL1 ),"&
     " 234 (BC_2, *             ,  control        , 1                  ),"&
     " 233 (BC_7, mdclk         ,  bidir          , X,  232 , 1, PULL0 ),"&
     " 232 (BC_2, *             ,  control        , 1                  ),"&
     " 231 (BC_7, uartrxd       ,  bidir          , X,  230 , 1, PULL0 ),"&
     " 230 (BC_2, *             ,  control        , 1                  ),"&
     " 229 (BC_7, uarttxd       ,  bidir          , X,  228 , 1, PULL0 ),"&
     " 228 (BC_2, *             ,  control        , 1                  ),"&
     " 227 (BC_7, uartcts       ,  bidir          , X,  226 , 1, PULL0 ),"&
     " 226 (BC_2, *             ,  control        , 1                  ),"&
     " 225 (BC_7, uartrts       ,  bidir          , X,  224 , 1, PULL0 ),"&
     " 224 (BC_2, *             ,  control        , 1                  ),"&
     " 223 (BC_1, rp1clkp       ,  input          , X                  ),"&
     " 222 (BC_7, extframeevent ,  bidir          , X,  221 , 1, PULL0 ),"&
     " 221 (BC_2, *             ,  control        , 1                  ),"&
     " 220 (BC_1, rp1fbp        ,  input          , X                  ),"&
     " 219 (BC_7, physync       ,  bidir          , X,  218 , 1, PULL0 ),"&
     " 218 (BC_2, *             ,  control        , 1                  ),"&
     " 217 (BC_7, radsync       ,  bidir          , X,  216 , 1, PULL0 ),"&
     " 216 (BC_2, *             ,  control        , 1                  ),"&
     " 215 (BC_7, ddrresetz     ,  bidir          , X,  214 , 1, Z     ),"&
     " 214 (BC_2, *             ,  control        , 1                  ),"&
     " 213 (BC_7, ddrcke0       ,  bidir          , X,  214 , 1, Z     ),"&
     " 212 (BC_7, ddrce0z       ,  bidir          , X,  214 , 1, Z     ),"&
     " 211 (BC_7, ddrce1z       ,  bidir          , X,  214 , 1, Z     ),"&
     " 210 (BC_7, ddrclkoutp0   ,  bidir          , X,  214 , 1, Z     ),"&
     " 209 (BC_7, ddrclkoutn0   ,  bidir          , X,  214 , 1, Z     ),"&
     " 208 (BC_7, ddrrasz       ,  bidir          , X,  214 , 1, Z     ),"&
     " 207 (BC_7, ddrcasz       ,  bidir          , X,  214 , 1, Z     ),"&
     " 206 (BC_7, ddrwez        ,  bidir          , X,  214 , 1, Z     ),"&
     " 205 (BC_7, ddrodt0       ,  bidir          , X,  214 , 1, Z     ),"&
     " 204 (BC_7, ddrodt1       ,  bidir          , X,  214 , 1, Z     ),"&
     " 203 (BC_7, ddrba0        ,  bidir          , X,  202 , 1, Z     ),"&
     " 202 (BC_2, *             ,  control        , 1                  ),"&
     " 201 (BC_7, ddrba1        ,  bidir          , X,  202 , 1, Z     ),"&
     " 200 (BC_7, ddrba2        ,  bidir          , X,  202 , 1, Z     ),"&
     " 199 (BC_7, ddra00        ,  bidir          , X,  202 , 1, Z     ),"&
     " 198 (BC_7, ddra01        ,  bidir          , X,  202 , 1, Z     ),"&
     " 197 (BC_7, ddra02        ,  bidir          , X,  202 , 1, Z     ),"&
     " 196 (BC_7, ddra03        ,  bidir          , X,  202 , 1, Z     ),"&
     " 195 (BC_7, ddra04        ,  bidir          , X,  202 , 1, Z     ),"&
     " 194 (BC_7, ddra05        ,  bidir          , X,  202 , 1, Z     ),"&
     " 193 (BC_7, ddra06        ,  bidir          , X,  202 , 1, Z     ),"&
     " 192 (BC_7, ddra07        ,  bidir          , X,  202 , 1, Z     ),"&
     " 191 (BC_7, ddra08        ,  bidir          , X,  190 , 1, Z     ),"&
     " 190 (BC_2, *             ,  control        , 1                  ),"&
     " 189 (BC_7, ddra09        ,  bidir          , X,  190 , 1, Z     ),"&
     " 188 (BC_7, ddra10        ,  bidir          , X,  190 , 1, Z     ),"&
     " 187 (BC_7, ddra11        ,  bidir          , X,  190 , 1, Z     ),"&
     " 186 (BC_7, ddrclkoutp1   ,  bidir          , X,  190 , 1, Z     ),"&
     " 185 (BC_7, ddrclkoutn1   ,  bidir          , X,  190 , 1, Z     ),"&
     " 184 (BC_7, ddra12        ,  bidir          , X,  190 , 1, Z     ),"&
     " 183 (BC_7, ddra13        ,  bidir          , X,  190 , 1, Z     ),"&
     " 182 (BC_7, ddra14        ,  bidir          , X,  190 , 1, Z     ),"&
     " 181 (BC_7, ddra15        ,  bidir          , X,  190 , 1, Z     ),"&
     " 180 (BC_7, ddrcke1       ,  bidir          , X,  190 , 1, Z     ),"&
     " 179 (BC_7, ddrd56        ,  bidir          , X,  178 , 1, Z     ),"&
     " 178 (BC_2, *             ,  control        , 1                  ),"&
     " 177 (BC_7, ddrd57        ,  bidir          , X,  176 , 1, Z     ),"&
     " 176 (BC_2, *             ,  control        , 1                  ),"&
     " 175 (BC_7, ddrd58        ,  bidir          , X,  174 , 1, Z     ),"&
     " 174 (BC_2, *             ,  control        , 1                  ),"&
     " 173 (BC_7, ddrd59        ,  bidir          , X,  172 , 1, Z     ),"&
     " 172 (BC_2, *             ,  control        , 1                  ),"&
     " 171 (BC_7, ddrd60        ,  bidir          , X,  170 , 1, Z     ),"&
     " 170 (BC_2, *             ,  control        , 1                  ),"&
     " 169 (BC_7, ddrd61        ,  bidir          , X,  168 , 1, Z     ),"&
     " 168 (BC_2, *             ,  control        , 1                  ),"&
     " 167 (BC_7, ddrd62        ,  bidir          , X,  166 , 1, Z     ),"&
     " 166 (BC_2, *             ,  control        , 1                  ),"&
     " 165 (BC_7, ddrd63        ,  bidir          , X,  164 , 1, Z     ),"&
     " 164 (BC_2, *             ,  control        , 1                  ),"&
     " 163 (BC_7, ddrdqs7p      ,  bidir          , X,  162 , 1, Z     ),"&
     " 162 (BC_2, *             ,  control        , 1                  ),"&
     " 161 (BC_7, ddrdqm7       ,  bidir          , X,  160 , 1, Z     ),"&
     " 160 (BC_2, *             ,  control        , 1                  ),"&
     " 159 (BC_7, ddrd48        ,  bidir          , X,  158 , 1, Z     ),"&
     " 158 (BC_2, *             ,  control        , 1                  ),"&
     " 157 (BC_7, ddrd49        ,  bidir          , X,  156 , 1, Z     ),"&
     " 156 (BC_2, *             ,  control        , 1                  ),"&
     " 155 (BC_7, ddrd50        ,  bidir          , X,  154 , 1, Z     ),"&
     " 154 (BC_2, *             ,  control        , 1                  ),"&
     " 153 (BC_7, ddrd51        ,  bidir          , X,  152 , 1, Z     ),"&
     " 152 (BC_2, *             ,  control        , 1                  ),"&
     " 151 (BC_7, ddrd52        ,  bidir          , X,  150 , 1, Z     ),"&
     " 150 (BC_2, *             ,  control        , 1                  ),"&
     " 149 (BC_7, ddrd53        ,  bidir          , X,  148 , 1, Z     ),"&
     " 148 (BC_2, *             ,  control        , 1                  ),"&
     " 147 (BC_7, ddrd54        ,  bidir          , X,  146 , 1, Z     ),"&
     " 146 (BC_2, *             ,  control        , 1                  ),"&
     " 145 (BC_7, ddrd55        ,  bidir          , X,  144 , 1, Z     ),"&
     " 144 (BC_2, *             ,  control        , 1                  ),"&
     " 143 (BC_7, ddrdqs6p      ,  bidir          , X,  142 , 1, Z     ),"&
     " 142 (BC_2, *             ,  control        , 1                  ),"&
     " 141 (BC_7, ddrdqm6       ,  bidir          , X,  140 , 1, Z     ),"&
     " 140 (BC_2, *             ,  control        , 1                  ),"&
     " 139 (BC_7, ddrd40        ,  bidir          , X,  138 , 1, Z     ),"&
     " 138 (BC_2, *             ,  control        , 1                  ),"&
     " 137 (BC_7, ddrd41        ,  bidir          , X,  136 , 1, Z     ),"&
     " 136 (BC_2, *             ,  control        , 1                  ),"&
     " 135 (BC_7, ddrd42        ,  bidir          , X,  134 , 1, Z     ),"&
     " 134 (BC_2, *             ,  control        , 1                  ),"&
     " 133 (BC_7, ddrd43        ,  bidir          , X,  132 , 1, Z     ),"&
     " 132 (BC_2, *             ,  control        , 1                  ),"&
     " 131 (BC_7, ddrd44        ,  bidir          , X,  130 , 1, Z     ),"&
     " 130 (BC_2, *             ,  control        , 1                  ),"&
     " 129 (BC_7, ddrd45        ,  bidir          , X,  128 , 1, Z     ),"&
     " 128 (BC_2, *             ,  control        , 1                  ),"&
     " 127 (BC_7, ddrd46        ,  bidir          , X,  126 , 1, Z     ),"&
     " 126 (BC_2, *             ,  control        , 1                  ),"&
     " 125 (BC_7, ddrd47        ,  bidir          , X,  124 , 1, Z     ),"&
     " 124 (BC_2, *             ,  control        , 1                  ),"&
     " 123 (BC_7, ddrdqs5p      ,  bidir          , X,  122 , 1, Z     ),"&
     " 122 (BC_2, *             ,  control        , 1                  ),"&
     " 121 (BC_7, ddrdqm5       ,  bidir          , X,  120 , 1, Z     ),"&
     " 120 (BC_2, *             ,  control        , 1                  ),"&
     " 119 (BC_7, ddrd32        ,  bidir          , X,  118 , 1, Z     ),"&
     " 118 (BC_2, *             ,  control        , 1                  ),"&
     " 117 (BC_7, ddrd33        ,  bidir          , X,  116 , 1, Z     ),"&
     " 116 (BC_2, *             ,  control        , 1                  ),"&
     " 115 (BC_7, ddrd34        ,  bidir          , X,  114 , 1, Z     ),"&
     " 114 (BC_2, *             ,  control        , 1                  ),"&
     " 113 (BC_7, ddrd35        ,  bidir          , X,  112 , 1, Z     ),"&
     " 112 (BC_2, *             ,  control        , 1                  ),"&
     " 111 (BC_7, ddrd36        ,  bidir          , X,  110 , 1, Z     ),"&
     " 110 (BC_2, *             ,  control        , 1                  ),"&
     " 109 (BC_7, ddrd37        ,  bidir          , X,  108 , 1, Z     ),"&
     " 108 (BC_2, *             ,  control        , 1                  ),"&
     " 107 (BC_7, ddrd38        ,  bidir          , X,  106 , 1, Z     ),"&
     " 106 (BC_2, *             ,  control        , 1                  ),"&
     " 105 (BC_7, ddrd39        ,  bidir          , X,  104 , 1, Z     ),"&
     " 104 (BC_2, *             ,  control        , 1                  ),"&
     " 103 (BC_7, ddrdqs4p      ,  bidir          , X,  102 , 1, Z     ),"&
     " 102 (BC_2, *             ,  control        , 1                  ),"&
     " 101 (BC_7, ddrdqm4       ,  bidir          , X,  100 , 1, Z     ),"&
     " 100 (BC_2, *             ,  control        , 1                  ),"&
     "  99 (BC_7, ddrd24        ,  bidir          , X,   98 , 1, Z     ),"&
     "  98 (BC_2, *             ,  control        , 1                  ),"&
     "  97 (BC_7, ddrd25        ,  bidir          , X,   96 , 1, Z     ),"&
     "  96 (BC_2, *             ,  control        , 1                  ),"&
     "  95 (BC_7, ddrd26        ,  bidir          , X,   94 , 1, Z     ),"&
     "  94 (BC_2, *             ,  control        , 1                  ),"&
     "  93 (BC_7, ddrd27        ,  bidir          , X,   92 , 1, Z     ),"&
     "  92 (BC_2, *             ,  control        , 1                  ),"&
     "  91 (BC_7, ddrd28        ,  bidir          , X,   90 , 1, Z     ),"&
     "  90 (BC_2, *             ,  control        , 1                  ),"&
     "  89 (BC_7, ddrd29        ,  bidir          , X,   88 , 1, Z     ),"&
     "  88 (BC_2, *             ,  control        , 1                  ),"&
     "  87 (BC_7, ddrd30        ,  bidir          , X,   86 , 1, Z     ),"&
     "  86 (BC_2, *             ,  control        , 1                  ),"&
     "  85 (BC_7, ddrd31        ,  bidir          , X,   84 , 1, Z     ),"&
     "  84 (BC_2, *             ,  control        , 1                  ),"&
     "  83 (BC_7, ddrdqs3p      ,  bidir          , X,   82 , 1, Z     ),"&
     "  82 (BC_2, *             ,  control        , 1                  ),"&
     "  81 (BC_7, ddrdqm3       ,  bidir          , X,   80 , 1, Z     ),"&
     "  80 (BC_2, *             ,  control        , 1                  ),"&
     "  79 (BC_7, ddrd16        ,  bidir          , X,   78 , 1, Z     ),"&
     "  78 (BC_2, *             ,  control        , 1                  ),"&
     "  77 (BC_7, ddrd17        ,  bidir          , X,   76 , 1, Z     ),"&
     "  76 (BC_2, *             ,  control        , 1                  ),"&
     "  75 (BC_7, ddrd18        ,  bidir          , X,   74 , 1, Z     ),"&
     "  74 (BC_2, *             ,  control        , 1                  ),"&
     "  73 (BC_7, ddrd19        ,  bidir          , X,   72 , 1, Z     ),"&
     "  72 (BC_2, *             ,  control        , 1                  ),"&
     "  71 (BC_7, ddrd20        ,  bidir          , X,   70 , 1, Z     ),"&
     "  70 (BC_2, *             ,  control        , 1                  ),"&
     "  69 (BC_7, ddrd21        ,  bidir          , X,   68 , 1, Z     ),"&
     "  68 (BC_2, *             ,  control        , 1                  ),"&
     "  67 (BC_7, ddrd22        ,  bidir          , X,   66 , 1, Z     ),"&
     "  66 (BC_2, *             ,  control        , 1                  ),"&
     "  65 (BC_7, ddrd23        ,  bidir          , X,   64 , 1, Z     ),"&
     "  64 (BC_2, *             ,  control        , 1                  ),"&
     "  63 (BC_7, ddrdqs2p      ,  bidir          , X,   62 , 1, Z     ),"&
     "  62 (BC_2, *             ,  control        , 1                  ),"&
     "  61 (BC_7, ddrdqm2       ,  bidir          , X,   60 , 1, Z     ),"&
     "  60 (BC_2, *             ,  control        , 1                  ),"&
     "  59 (BC_7, ddrd08        ,  bidir          , X,   58 , 1, Z     ),"&
     "  58 (BC_2, *             ,  control        , 1                  ),"&
     "  57 (BC_7, ddrd09        ,  bidir          , X,   56 , 1, Z     ),"&
     "  56 (BC_2, *             ,  control        , 1                  ),"&
     "  55 (BC_7, ddrd10        ,  bidir          , X,   54 , 1, Z     ),"&
     "  54 (BC_2, *             ,  control        , 1                  ),"&
     "  53 (BC_7, ddrd11        ,  bidir          , X,   52 , 1, Z     ),"&
     "  52 (BC_2, *             ,  control        , 1                  ),"&
     "  51 (BC_7, ddrd12        ,  bidir          , X,   50 , 1, Z     ),"&
     "  50 (BC_2, *             ,  control        , 1                  ),"&
     "  49 (BC_7, ddrd13        ,  bidir          , X,   48 , 1, Z     ),"&
     "  48 (BC_2, *             ,  control        , 1                  ),"&
     "  47 (BC_7, ddrd14        ,  bidir          , X,   46 , 1, Z     ),"&
     "  46 (BC_2, *             ,  control        , 1                  ),"&
     "  45 (BC_7, ddrd15        ,  bidir          , X,   44 , 1, Z     ),"&
     "  44 (BC_2, *             ,  control        , 1                  ),"&
     "  43 (BC_7, ddrdqs1p      ,  bidir          , X,   42 , 1, Z     ),"&
     "  42 (BC_2, *             ,  control        , 1                  ),"&
     "  41 (BC_7, ddrdqm1       ,  bidir          , X,   40 , 1, Z     ),"&
     "  40 (BC_2, *             ,  control        , 1                  ),"&
     "  39 (BC_7, ddrd00        ,  bidir          , X,   38 , 1, Z     ),"&
     "  38 (BC_2, *             ,  control        , 1                  ),"&
     "  37 (BC_7, ddrd01        ,  bidir          , X,   36 , 1, Z     ),"&
     "  36 (BC_2, *             ,  control        , 1                  ),"&
     "  35 (BC_7, ddrd02        ,  bidir          , X,   34 , 1, Z     ),"&
     "  34 (BC_2, *             ,  control        , 1                  ),"&
     "  33 (BC_7, ddrd03        ,  bidir          , X,   32 , 1, Z     ),"&
     "  32 (BC_2, *             ,  control        , 1                  ),"&
     "  31 (BC_7, ddrd04        ,  bidir          , X,   30 , 1, Z     ),"&
     "  30 (BC_2, *             ,  control        , 1                  ),"&
     "  29 (BC_7, ddrd05        ,  bidir          , X,   28 , 1, Z     ),"&
     "  28 (BC_2, *             ,  control        , 1                  ),"&
     "  27 (BC_7, ddrd06        ,  bidir          , X,   26 , 1, Z     ),"&
     "  26 (BC_2, *             ,  control        , 1                  ),"&
     "  25 (BC_7, ddrd07        ,  bidir          , X,   24 , 1, Z     ),"&
     "  24 (BC_2, *             ,  control        , 1                  ),"&
     "  23 (BC_7, ddrdqs0p      ,  bidir          , X,   22 , 1, Z     ),"&
     "  22 (BC_2, *             ,  control        , 1                  ),"&
     "  21 (BC_7, ddrdqm0       ,  bidir          , X,   20 , 1, Z     ),"&
     "  20 (BC_2, *             ,  control        , 1                  ),"&
     "  19 (BC_7, ddrcb00       ,  bidir          , X,   18 , 1, Z     ),"&
     "  18 (BC_2, *             ,  control        , 1                  ),"&
     "  17 (BC_7, ddrcb01       ,  bidir          , X,   16 , 1, Z     ),"&
     "  16 (BC_2, *             ,  control        , 1                  ),"&
     "  15 (BC_7, ddrcb02       ,  bidir          , X,   14 , 1, Z     ),"&
     "  14 (BC_2, *             ,  control        , 1                  ),"&
     "  13 (BC_7, ddrcb03       ,  bidir          , X,   12 , 1, Z     ),"&
     "  12 (BC_2, *             ,  control        , 1                  ),"&
     "  11 (BC_7, ddrcb04       ,  bidir          , X,   10 , 1, Z     ),"&
     "  10 (BC_2, *             ,  control        , 1                  ),"&
     "   9 (BC_7, ddrcb05       ,  bidir          , X,    8 , 1, Z     ),"&
     "   8 (BC_2, *             ,  control        , 1                  ),"&
     "   7 (BC_7, ddrcb06       ,  bidir          , X,    6 , 1, Z     ),"&
     "   6 (BC_2, *             ,  control        , 1                  ),"&
     "   5 (BC_7, ddrcb07       ,  bidir          , X,    4 , 1, Z     ),"&
     "   4 (BC_2, *             ,  control        , 1                  ),"&
     "   3 (BC_7, ddrdqs8p      ,  bidir          , X,    2 , 1, Z     ),"&
     "   2 (BC_2, *             ,  control        , 1                  ),"&
     "   1 (BC_7, ddrdqm8       ,  bidir          , X,    0 , 1, Z     ),"&
     "   0 (BC_2, *             ,  control        , 1                  )";

 attribute AIO_COMPONENT_CONFORMANCE  of TMS320TCI6618 : entity is "STD_1149_6_2003";
 attribute AIO_EXTEST_Pulse_Execution of TMS320TCI6618 : entity is "Wait_Duration tck 15";
 attribute AIO_EXTEST_Train_Execution of TMS320TCI6618 : entity is "train 30, maximum_time 120.0e-6";
 attribute AIO_Pin_Behavior           of TMS320TCI6618 : entity is
        "aiftxp0, aiftxp1, aiftxp2, aiftxp3, aiftxp4, aiftxp5,                 "&
        "pcietxp0, pcietxp1, sgmii0txp, sgmii1txp,                             "&
        "riotxp0, riotxp1, riotxp2, riotxp3,                                   "&
        "mcmtxp0, mcmtxp1, mcmtxp2, mcmtxp3 : AC_Select = 467;                 "&
        "aifrxp0, aifrxp1, aifrxp2, aifrxp3, aifrxp4, aifrxp5,                 "&
        "pcierxp0, pcierxp1, sgmii0rxp, sgmii1rxp,                             "&
        "riorxp0, riorxp1, riorxp2, riorxp3,                                   "&
        "mcmrxp0, mcmrxp1, mcmrxp2, mcmrxp3 : LP_time=120.0e-9 HP_time=500.0e-9";

 attribute DESIGN_WARNING of TMS320TCI6618 : entity is
      "According to simulation, BSD JTAG TAP may not work correctly unless  "&
      " device has completed RESET sequence first.                          "&
      "                                                                     "&
      "Forcing PORz low then release (no clock pulses required) would meet  "&
      " the requirement.                                                    "&
      "                                                                     "&
      "In order to enter bscan mode correctly, TMS must be low at the       "&
      "rising edge of TRSTz and at least one cycle after TRSTz is high.     "&
      "                                                                     "&
      "Note that boundary scan registers with disable result WEAK1 are      "&
      "open drain type pins, which require exteral pull-ups for tests to    "&
      "perform correctly.                                                   "&
      "                                                                     "&
      "Once device is programmed for IEEE1149.6 operations, AC coupling RX  "&
      " pins' comparators become edge sensitive. Therefore their boundary   "&
      " scan captured values are indeterministic until an edge/transition   "&
      " is detected.                                                        ";

end TMS320TCI6618;