-- ***********************************************************************
-- BSDL file for design transceiver_top_test_4_transceiver_test_pattern
-- Created by Synopsys Version 1999.10 (Sep 02, 1999)
-- Designer:
-- Company:
-- Date: Tue Sep 2 11:17:17 2003
-- ***********************************************************************
entity transceiver_top_test_4_transceiver_test_pattern is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "PBGA208");
-- This section declares all the ports in the design.
port (
CSB : in bit;
DSB_RDB_SCLK : in bit;
MPM : in bit;
OSCI : in bit;
RESETB : in bit;
RWB_WRB_SDI : in bit;
SPIEN : in bit;
TCK : in bit;
TDI : in bit;
TEST0 : in bit;
TESTSE : in bit;
TEST_1544 : in bit;
TEST_2048 : in bit;
THZ : in bit;
TMS : in bit;
TRSTB : in bit;
A : in bit_vector (0 to 9);
CLK_SEL : in bit_vector (0 to 2);
RRING : in bit_vector (1 to 4);
RTIP : in bit_vector (1 to 4);
TSD : in bit_vector (1 to 4);
TSIG : in bit_vector (1 to 4);
D : inout bit_vector (0 to 7);
GPIO : inout bit_vector (0 to 1);
RSCK : inout bit_vector (1 to 4);
RSFS : inout bit_vector (1 to 4);
TSCK : inout bit_vector (1 to 4);
TSFS : inout bit_vector (1 to 4);
INTB : out bit;
TDO : out bit;
RSD : out bit_vector (1 to 4);
RSIG : out bit_vector (1 to 4);
CLK_GEN_1544 : buffer bit;
CLK_GEN_2048 : buffer bit;
REFA_OUT : buffer bit;
REFB_OUT : buffer bit;
REFR : linkage bit;
TEST1 : linkage bit;
VDDAB : linkage bit;
VDDAP : linkage bit;
VDDAR1 : linkage bit;
VDDAR2 : linkage bit;
VDDAR3 : linkage bit;
VDDAR4 : linkage bit;
VDDAT1 : linkage bit;
VDDAT2 : linkage bit;
VDDAT3 : linkage bit;
VDDAT4 : linkage bit;
VDDAX1 : linkage bit;
VDDAX2 : linkage bit;
VDDAX3 : linkage bit;
VDDAX4 : linkage bit;
GNDA : linkage bit_vector (1 to 14);
GNDD : linkage bit_vector (1 to 20);
NC : linkage bit_vector (1 to 51);
VDDDC : linkage bit_vector (1 to 10);
VDDIO : linkage bit_vector (1 to 12)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of
transceiver_top_test_4_transceiver_test_pattern: entity is
"STD_1149_1_1993";
attribute PIN_MAP of transceiver_top_test_4_transceiver_test_pattern
: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant PBGA208: PIN_MAP_STRING :=
"CSB : N10," &
"DSB_RDB_SCLK : R10," &
"MPM : P11," &
"OSCI : B13," &
"RESETB : A14," &
"RWB_WRB_SDI : P10," &
"SPIEN : R11," &
"TCK : T14," &
"TDI : R13," &
"TEST0 : N11," &
"TESTSE : P12," &
"TEST_1544 : C15," &
"TEST_2048 : D16," &
"THZ : B16," &
"TMS : R14," &
"TRSTB : N12," &
"A : (R5, T5, N6, P6, R6, T6, N7, P7, R7, T7)," &
"CLK_SEL : (D15, C14, B15)," &
"RRING : (D11, D9, D5, C4)," &
"RTIP : (C11, D8, D6, B4)," &
"TSD : (G2, F2, G3, F3)," &
"TSIG : (F1, E1, G4, F4)," &
"D : (T10, N9, P9, R9, T9, T8, R8, P8)," &
"GPIO : (E13, D13)," &
"RSCK : (P5, T4, P4, T3)," &
"RSFS : (N5, R4, N4, R3)," &
"TSCK : (L1, K1, J1, H2)," &
"TSFS : (K2, J2, H1, G1)," &
"INTB : T11," &
"TDO : T13," &
"RSD : (P3, R2, T1, P1)," &
"RSIG : (T2, P2, R1, N3)," &
"CLK_GEN_1544 : A16," &
"CLK_GEN_2048 : D14," &
"REFA_OUT : A15," &
"REFB_OUT : B14," &
"REFR : C16," &
"TEST1 : T12," &
"VDDAB : D12," &
"VDDAP : A13," &
"VDDAR1 : A10," &
"VDDAR2 : C9," &
"VDDAR3 : A5," &
"VDDAR4 : A4," &
"VDDAT1 : B12," &
"VDDAT2 : B9," &
"VDDAT3 : B5," &
"VDDAT4 : A3," &
"VDDAX1 : C12," &
"VDDAX2 : B8," &
"VDDAX3 : B7," &
"VDDAX4 : B2," &
"GNDA : (B11, B10, C10, D10, C8, C7, D7, B6, C6, C5, D4, B3" &
", C3, D3)," &
"GNDD : (F13, F15, G7, G8, G9, G10, G13, G15, H9, H10, J14, " &
"K13, K14, L14, L15, M14, N13, P13, P14, P15)," &
"NC : (C13, A12, A8, A7, A1, A11, A9, A6, A2, B1, C1, C2, " &
"D1, D2, E2, E3, E4, E16, F14, F16, G14, H3, H4, H13, H16, J3, J4, " &
"J13, J16, K3, K4, K16, L2, L3, L4, L13, L16, M1, M2, M3, M4, M13, " &
"N1, N2, N8, N14, N15, R12, R16, T15, T16)," &
"VDDDC : (H7, H8, J7, J8, J9, J10, K7, K8, K9, K10)," &
"VDDIO : (E14, E15, G16, H14, H15, J15, K15, M15, M16, N16, " &
"P16, R15)";
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRSTB: signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of
transceiver_top_test_4_transceiver_test_pattern: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of
transceiver_top_test_4_transceiver_test_pattern: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (010)," &
"CLAMP (011)," &
"HIGHZ (100)," &
"USER1 (110)," &
"IDCODE (001)," &
"USER2 (101)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of
transceiver_top_test_4_transceiver_test_pattern: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of
transceiver_top_test_4_transceiver_test_pattern: entity is
"0000" & -- 4-bit version number
"0000010011011000" & -- 16-bit part number
"00000110011" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of
transceiver_top_test_4_transceiver_test_pattern: entity is
"BYPASS (BYPASS, CLAMP, HIGHZ, USER1)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)," &
"UTDR1[20] (USER2)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of
transceiver_top_test_4_transceiver_test_pattern: entity is 173;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of
transceiver_top_test_4_transceiver_test_pattern: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"172 (BC_0, *, internal, X), " &
"171 (BC_4, A(9), observe_only, X), " &
"170 (BC_4, A(8), observe_only, X), " &
"169 (BC_4, A(7), observe_only, X), " &
"168 (BC_4, A(6), observe_only, X), " &
"167 (BC_4, A(5), observe_only, X), " &
"166 (BC_4, A(4), observe_only, X), " &
"165 (BC_4, A(3), observe_only, X), " &
"164 (BC_4, A(2), observe_only, X), " &
"163 (BC_4, A(1), observe_only, X), " &
"162 (BC_4, A(0), observe_only, X), " &
"161 (BC_1, *, control, 1), " &
"160 (BC_4, D(7), observe_only, X), " &
"159 (BC_1, D(7), output3, X, 161, 1, Z), " &
"158 (BC_4, D(6), observe_only, X), " &
"157 (BC_1, D(6), output3, X, 161, 1, Z), " &
"156 (BC_4, D(5), observe_only, X), " &
"155 (BC_1, D(5), output3, X, 161, 1, Z), " &
"154 (BC_4, D(4), observe_only, X), " &
"153 (BC_1, D(4), output3, X, 161, 1, Z), " &
"152 (BC_4, D(3), observe_only, X), " &
"151 (BC_1, D(3), output3, X, 161, 1, Z), " &
"150 (BC_4, D(2), observe_only, X), " &
"149 (BC_1, D(2), output3, X, 161, 1, Z), " &
"148 (BC_4, D(1), observe_only, X), " &
"147 (BC_1, D(1), output3, X, 161, 1, Z), " &
"146 (BC_4, D(0), observe_only, X), " &
"145 (BC_1, D(0), output3, X, 161, 1, Z), " &
"144 (BC_4, CSB, observe_only, X), " &
"143 (BC_4, RWB_WRB_SDI, observe_only, X), " &
"142 (BC_4, DSB_RDB_SCLK, observe_only, X), " &
"141 (BC_4, MPM, observe_only, X), " &
"140 (BC_4, SPIEN, observe_only, X), " &
"139 (BC_1, *, control, 1), " &
"138 (BC_1, INTB, output3, X, 139, 1, Z), " &
"137 (BC_1, *, controlr, 1), " &
"136 (BC_4, RSCK(1), observe_only, X), " &
"135 (BC_1, RSCK(1), output3, X, 137, 1, PULL1),"
&
"134 (BC_4, RSFS(1), observe_only, X), " &
"133 (BC_1, RSFS(1), output3, X, 137, 1, PULL1),"
&
"132 (BC_1, *, controlr, 1), " &
"131 (BC_4, RSCK(2), observe_only, X), " &
"130 (BC_1, RSCK(2), output3, X, 132, 1, PULL1),"
&
"129 (BC_4, RSFS(2), observe_only, X), " &
"128 (BC_1, RSFS(2), output3, X, 132, 1, PULL1),"
&
"127 (BC_1, *, controlr, 1), " &
"126 (BC_4, RSCK(3), observe_only, X), " &
"125 (BC_1, RSCK(3), output3, X, 127, 1, PULL1),"
&
"124 (BC_4, RSFS(3), observe_only, X), " &
"123 (BC_1, RSFS(3), output3, X, 127, 1, PULL1),"
&
"122 (BC_1, *, controlr, 1), " &
"121 (BC_4, RSCK(4), observe_only, X), " &
"120 (BC_1, RSCK(4), output3, X, 122, 1, PULL1),"
&
"119 (BC_4, RSFS(4), observe_only, X), " &
"118 (BC_1, RSFS(4), output3, X, 122, 1, PULL1),"
&
"117 (BC_0, *, internal, X), " &
"116 (BC_0, *, internal, X), " &
"115 (BC_0, *, internal, X), " &
"114 (BC_0, *, internal, X), " &
"113 (BC_0, *, internal, X), " &
"112 (BC_0, *, internal, X), " &
"111 (BC_0, *, internal, X), " &
"110 (BC_0, *, internal, X), " &
"109 (BC_0, *, internal, X), " &
"108 (BC_0, *, internal, X), " &
"107 (BC_0, *, internal, X), " &
"106 (BC_0, *, internal, X), " &
"105 (BC_0, *, internal, X), " &
"104 (BC_0, *, internal, X), " &
"103 (BC_0, *, internal, X), " &
"102 (BC_0, *, internal, X), " &
"101 (BC_0, *, internal, X), " &
"100 (BC_0, *, internal, X), " &
"99 (BC_0, *, internal, X), " &
"98 (BC_0, *, internal, X), " &
"97 (BC_1, *, controlr, 1), " &
"96 (BC_1, RSD(1), output3, X, 97, 1, Z), " &
"95 (BC_1, RSIG(1), output3, X, 97, 1, Z), " &
"94 (BC_1, *, controlr, 1), " &
"93 (BC_1, RSD(2), output3, X, 94, 1, Z), " &
"92 (BC_1, RSIG(2), output3, X, 94, 1, Z), " &
"91 (BC_1, *, controlr, 1), " &
"90 (BC_1, RSD(3), output3, X, 91, 1, Z), " &
"89 (BC_1, RSIG(3), output3, X, 91, 1, Z), " &
"88 (BC_1, *, controlr, 1), " &
"87 (BC_1, RSD(4), output3, X, 88, 1, Z), " &
"86 (BC_1, RSIG(4), output3, X, 88, 1, Z), " &
"85 (BC_0, *, internal, X), " &
"84 (BC_0, *, internal, X), " &
"83 (BC_0, *, internal, X), " &
"82 (BC_0, *, internal, X), " &
"81 (BC_0, *, internal, X), " &
"80 (BC_0, *, internal, X), " &
"79 (BC_0, *, internal, X), " &
"78 (BC_0, *, internal, X), " &
"77 (BC_0, *, internal, X), " &
"76 (BC_0, *, internal, X), " &
"75 (BC_0, *, internal, X), " &
"74 (BC_0, *, internal, X), " &
"73 (BC_1, *, controlr, 1), " &
"72 (BC_4, TSCK(1), observe_only, X), " &
"71 (BC_1, TSCK(1), output3, X, 73, 1, PULL1),"
&
"70 (BC_4, TSFS(1), observe_only, X), " &
"69 (BC_1, TSFS(1), output3, X, 73, 1, PULL1),"
&
"68 (BC_1, *, controlr, 1), " &
"67 (BC_4, TSCK(2), observe_only, X), " &
"66 (BC_1, TSCK(2), output3, X, 68, 1, PULL1),"
&
"65 (BC_4, TSFS(2), observe_only, X), " &
"64 (BC_1, TSFS(2), output3, X, 68, 1, PULL1),"
&
"63 (BC_1, *, controlr, 1), " &
"62 (BC_4, TSCK(3), observe_only, X), " &
"61 (BC_1, TSCK(3), output3, X, 63, 1, PULL1),"
&
"60 (BC_4, TSFS(3), observe_only, X), " &
"59 (BC_1, TSFS(3), output3, X, 63, 1, PULL1),"
&
"58 (BC_1, *, controlr, 1), " &
"57 (BC_4, TSCK(4), observe_only, X), " &
"56 (BC_1, TSCK(4), output3, X, 58, 1, PULL1),"
&
"55 (BC_4, TSFS(4), observe_only, X), " &
"54 (BC_1, TSFS(4), output3, X, 58, 1, PULL1),"
&
"53 (BC_0, *, internal, X), " &
"52 (BC_0, *, internal, X), " &
"51 (BC_0, *, internal, X), " &
"50 (BC_0, *, internal, X), " &
"49 (BC_0, *, internal, X), " &
"48 (BC_0, *, internal, X), " &
"47 (BC_0, *, internal, X), " &
"46 (BC_0, *, internal, X), " &
"45 (BC_0, *, internal, X), " &
"44 (BC_0, *, internal, X), " &
"43 (BC_0, *, internal, X), " &
"42 (BC_0, *, internal, X), " &
"41 (BC_0, *, internal, X), " &
"40 (BC_0, *, internal, X), " &
"39 (BC_0, *, internal, X), " &
"38 (BC_0, *, internal, X), " &
"37 (BC_0, *, internal, X), " &
"36 (BC_0, *, internal, X), " &
"35 (BC_0, *, internal, X), " &
"34 (BC_0, *, internal, X), " &
"33 (BC_4, TSD(1), observe_only, X), " &
"32 (BC_4, TSIG(1), observe_only, X), " &
"31 (BC_4, TSD(2), observe_only, X), " &
"30 (BC_4, TSIG(2), observe_only, X), " &
"29 (BC_4, TSD(3), observe_only, X), " &
"28 (BC_4, TSIG(3), observe_only, X), " &
"27 (BC_4, TSD(4), observe_only, X), " &
"26 (BC_4, TSIG(4), observe_only, X), " &
"25 (BC_0, *, internal, X), " &
"24 (BC_0, *, internal, X), " &
"23 (BC_0, *, internal, X), " &
"22 (BC_0, *, internal, X), " &
"21 (BC_0, *, internal, X), " &
"20 (BC_0, *, internal, X), " &
"19 (BC_0, *, internal, X), " &
"18 (BC_0, *, internal, X), " &
"17 (BC_4, OSCI, observe_only, X), " &
"16 (BC_4, RESETB, observe_only, X), " &
"15 (BC_1, *, control, 1), " &
"14 (BC_4, GPIO(1), observe_only, X), " &
"13 (BC_1, GPIO(1), output3, X, 15, 1, PULL1),"
&
"12 (BC_1, *, controlr, 1), " &
"11 (BC_4, GPIO(0), observe_only, X), " &
"10 (BC_1, GPIO(0), output3, X, 12, 1, PULL1),"
&
"9 (BC_4, CLK_SEL(2), observe_only, X), " &
"8 (BC_4, CLK_SEL(1), observe_only, X), " &
"7 (BC_4, CLK_SEL(0), observe_only, X), " &
"6 (BC_4, TEST_1544, observe_only, X), " &
"5 (BC_4, TEST_2048, observe_only, X), " &
"4 (BC_1, REFA_OUT, output2, X), " &
"3 (BC_1, REFB_OUT, output2, X), " &
"2 (BC_1, CLK_GEN_1544, output2, X), " &
"1 (BC_1, CLK_GEN_2048, output2, X), " &
"0 (BC_4, THZ, observe_only, X) ";
end transceiver_top_test_4_transceiver_test_pattern;
