-- *****************************************************************************
-- BSDL file for design altairxl_top
-- Company: PLX TECHNOLOGY
-- Date: 2006/11/21
-- Date: 10/1/07 removed DEVICE_ID settings for customer release BSDL
-- as these pins are tied in the package. Also added powers and grounds.
-- changed ball for PEX_PERST to G3.
-- *****************************************************************************
entity altairxl_top is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "PEX_8509AA");
-- This section declares all the ports in the design.
port (
EE_CS_P : out bit ;
EE_DI_P : out bit ;
EE_DO_P : inout bit ;
EE_SK_P : inout bit ;
FATAL_ERRn_P : inout bit ;
HP_ATNLEDn_P_1 : inout bit ;
HP_ATNLEDn_P_2 : out bit ;
HP_ATNLEDn_P_3 : out bit ;
HP_BUTTONn_P_1 : inout bit ;
HP_BUTTONn_P_2 : inout bit ;
HP_BUTTONn_P_3 : inout bit ;
HP_CLKENn_P_1 : out bit ;
HP_CLKENn_P_2 : out bit ;
HP_CLKENn_P_3 : out bit ;
HP_MRLn_P_1 : inout bit ;
HP_MRLn_P_2 : inout bit ;
HP_MRLn_P_3 : inout bit ;
HP_PERSTn_P_1 : out bit ;
HP_PERSTn_P_2 : out bit ;
HP_PERSTn_P_3 : out bit ;
HP_PRSNTn_P_1 : inout bit ;
HP_PRSNTn_P_2 : inout bit ;
HP_PRSNTn_P_3 : inout bit ;
HP_PWRENn_P_1 : out bit ;
HP_PWRENn_P_2 : out bit ;
HP_PWRENn_P_3 : out bit ;
HP_PWRFLTn_P_1 : inout bit ;
HP_PWRFLTn_P_2 : inout bit ;
HP_PWRFLTn_P_3 : inout bit ;
HP_PWRLEDn_P_1 : out bit ;
HP_PWRLEDn_P_2 : out bit ;
HP_PWRLEDn_P_3 : out bit ;
I2C_ADDR_P_0 : in bit ;
I2C_ADDR_P_1 : in bit ;
I2C_ADDR_P_2 : in bit ;
I2C_SCL_P : inout bit ;
I2C_SDA_P : inout bit ;
JTAG_TCK_P : in bit ;
JTAG_TDI_P : in bit ;
JTAG_TDO_P : out bit ;
JTAG_TMS_P : in bit ;
JTAG_TRSTn_P : in bit ;
PEX_HSIn_P_0 : in bit ;
PEX_HSIn_P_1 : in bit ;
PEX_HSIn_P_2 : in bit ;
PEX_HSIn_P_3 : in bit ;
PEX_HSIn_P_4 : in bit ;
PEX_HSIn_P_5 : in bit ;
PEX_HSIn_P_6 : in bit ;
PEX_HSIn_P_7 : in bit ;
PEX_HSIp_P_0 : in bit ;
PEX_HSIp_P_1 : in bit ;
PEX_HSIp_P_2 : in bit ;
PEX_HSIp_P_3 : in bit ;
PEX_HSIp_P_4 : in bit ;
PEX_HSIp_P_5 : in bit ;
PEX_HSIp_P_6 : in bit ;
PEX_HSIp_P_7 : in bit ;
PEX_INTAn_P : inout bit ;
PEX_LANE_GOOD_P_0 : inout bit ;
PEX_LANE_GOOD_P_1 : inout bit ;
PEX_LANE_GOOD_P_2 : inout bit ;
PEX_LANE_GOOD_P_3 : inout bit ;
PEX_LANE_GOOD_P_4 : inout bit ;
PEX_LANE_GOOD_P_5 : inout bit ;
PEX_LANE_GOOD_P_6 : inout bit ;
PEX_LANE_GOOD_P_7 : out bit ;
PROCMON_P : inout bit ;
SPARE0_P : inout bit ;
SPARE1_P : inout bit ;
SPARE2_P : inout bit ;
STN0_STRAP_PORTCFG_P_0 : in bit ;
STN0_STRAP_PORTCFG_P_1 : in bit ;
STRAP_DEBUG_SEL_P_0 : in bit ;
STRAP_DEBUG_SEL_P_1 : in bit ;
STRAP_FAST_BRINGUPn_P : in bit ;
STRAP_PLL_BYPASSn_P : in bit ;
STRAP_PROBE_MODEn_P : in bit ;
STRAP_SERDES_MODE_ENn_P : in bit ;
STRAP_TESTMODE_P_0 : in bit ;
STRAP_TESTMODE_P_1 : in bit ;
STRAP_TESTMODE_P_2 : in bit ;
STRAP_TESTMODE_P_3 : in bit ;
STRAP_UPSTRM_PORTSEL_P_0 : in bit ;
STRAP_UPSTRM_PORTSEL_P_1 : in bit ;
STRAP_UPSTRM_PORTSEL_P_2 : in bit ;
--
PEX_HSOn_P_0 : buffer bit ;
PEX_HSOn_P_1 : buffer bit ;
PEX_HSOn_P_2 : buffer bit ;
PEX_HSOn_P_3 : buffer bit ;
PEX_HSOn_P_4 : buffer bit ;
PEX_HSOn_P_5 : buffer bit ;
PEX_HSOn_P_6 : buffer bit ;
PEX_HSOn_P_7 : buffer bit ;
PEX_HSOp_P_0 : buffer bit ;
PEX_HSOp_P_1 : buffer bit ;
PEX_HSOp_P_2 : buffer bit ;
PEX_HSOp_P_3 : buffer bit ;
PEX_HSOp_P_4 : buffer bit ;
PEX_HSOp_P_5 : buffer bit ;
PEX_HSOp_P_6 : buffer bit ;
PEX_HSOp_P_7 : buffer bit ;
--
PEX_PERSTn_P : linkage bit ;
PEX_REFCLK_neg_P_0 : linkage bit ;
PEX_REFCLK_pos_P_0 : linkage bit ;
THERMAL_DIODEn : linkage bit ;
THERMAL_DIODEp : linkage bit ;
VDD10 : linkage bit_vector (0 to 10);
VDD10A : linkage bit_vector (0 to 2);
VDD10S : linkage bit_vector (0 to 10);
VDD33 : linkage bit_vector (0 to 14);
VDD33A : linkage bit ;
VSS : linkage bit_vector (0 to 42)
);
use STD_1149_1_2001.all;
use STD_1149_6_2003.all;
attribute COMPONENT_CONFORMANCE of altairxl_top: entity is "STD_1149_1_2001";
attribute PIN_MAP of altairxl_top: entity is PHYSICAL_PIN_MAP;
constant PEX_8509AA: PIN_MAP_STRING :=
-- the followings are still missing from the altairxl_pinout.8509 as of 2006/11/21
" STRAP_SERDES_MODE_ENn_P : A2 , " &
" HP_PWRLEDn_P_3 : E13 , " &
" PEX_LANE_GOOD_P_1 : A4 , " &
" THERMAL_DIODEp : A5 , " &
" STRAP_UPSTRM_PORTSEL_P_1 : A6 , " &
" STRAP_UPSTRM_PORTSEL_P_0 : A7 , " &
" HP_BUTTONn_P_3 : B13 , " &
" JTAG_TDI_P : A9 , " &
" JTAG_TDO_P : A10 , " &
" STRAP_TESTMODE_P_2 : A11 , " &
" STRAP_DEBUG_SEL_P_0 : A12 , " &
" STRAP_DEBUG_SEL_P_1 : A13 , " &
" HP_BUTTONn_P_2 : A8 , " &
" SPARE1_P : D14 , " &
" PEX_LANE_GOOD_P_3 : B3 , " &
" PEX_LANE_GOOD_P_2 : B4 , " &
" HP_PRSNTn_P_2 : B5 , " &
" HP_PRSNTn_P_3 : F11 , " &
" PEX_LANE_GOOD_P_0 : B6 , " &
" HP_PWRFLTn_P_3 : D12 , " &
" HP_MRLn_P_2 : B8 , " &
" JTAG_TRSTn_P : B9 , " &
" JTAG_TMS_P : B10 , " &
" STRAP_TESTMODE_P_1 : B11 , " &
" SPARE0_P : B12 , " &
" HP_BUTTONn_P_1 : B2 , " &
" HP_MRLn_P_3 : B14 , " &
" PEX_LANE_GOOD_P_4 : C2 , " &
" HP_ATNLEDn_P_2 : C9 , " &
" PEX_INTAn_P : C3 , " &
" HP_CLKENn_P_3 : F12 , " &
" HP_PERSTn_P_3 : E12 , " &
" THERMAL_DIODEn : C6 , " &
" HP_PWRENn_P_3 : C14 , " &
" STRAP_UPSTRM_PORTSEL_P_2 : C8 , " &
" HP_ATNLEDn_P_3 : D11 , " &
" JTAG_TCK_P : C10 , " &
" STRAP_TESTMODE_P_0 : C11 , " &
" STRAP_TESTMODE_P_3 : C12 , " &
--
" PEX_LANE_GOOD_P_7 : C13 , " &
" HP_PWRENn_P_1 : D1 , " &
" PEX_LANE_GOOD_P_6 : D13 , " &
" HP_MRLn_P_1 : C1 , " &
" HP_PWRFLTn_P_2 : B7 , " &
" HP_ATNLEDn_P_1 : B1 , " &
" HP_PWRFLTn_P_1 : D2 , " &
--
" PEX_LANE_GOOD_P_5 : D3 , " &
" HP_PERSTn_P_1 : E3 , " &
" HP_PWRLEDn_P_2 : A3 , " &
" HP_PWRENn_P_2 : C7 , " &
" HP_PERSTn_P_2 : C5 , " &
" HP_PRSNTn_P_1 : E2 , " &
" HP_PWRLEDn_P_1 : E1 , " &
" STN0_STRAP_PORTCFG_P_1 : E14 , " &
" STRAP_PLL_BYPASSn_P : F1 , " &
" HP_CLKENn_P_2 : C4 , " &
" PROCMON_P : F3 , " &
" HP_CLKENn_P_1 : F2 , " &
" EE_DO_P : G12 , " &
" EE_SK_P : G13 , " &
" STRAP_FAST_BRINGUPn_P : G2 , " &
" STN0_STRAP_PORTCFG_P_0 : F13 , " &
" EE_CS_P : F14 , " &
" STRAP_PROBE_MODEn_P : G14 , " &
" PEX_PERSTn_P : G3 , " &
" EE_DI_P : H12 , " &
" I2C_SDA_P : H13 , " &
" I2C_SCL_P : H14 , " &
" PEX_REFCLK_pos_P_0 : J1 , " &
" PEX_REFCLK_neg_P_0 : J2 , " &
" SPARE2_P : J12 , " &
" FATAL_ERRn_P : J13 , " &
" I2C_ADDR_P_0 : K11 , " &
" I2C_ADDR_P_1 : K12 , " &
" I2C_ADDR_P_2 : L12 , " &
" PEX_HSIn_P_7 : K14 , " &
" PEX_HSIn_P_0 : L1 , " &
" PEX_HSIp_P_7 : L14 , " &
" PEX_HSIp_P_0 : M1 , " &
" PEX_HSOp_P_0 : N1 , " &
" PEX_HSOn_P_1 : N2 , " &
" PEX_HSIp_P_1 : N3 , " &
" PEX_HSIn_P_2 : N4 , " &
" PEX_HSOp_P_2 : N5 , " &
" PEX_HSOn_P_3 : N6 , " &
" PEX_HSIp_P_3 : N7 , " &
" PEX_HSIp_P_4 : N8 , " &
" PEX_HSOn_P_4 : N9 , " &
" PEX_HSOp_P_5 : N10 , " &
" PEX_HSIn_P_5 : N11 , " &
" PEX_HSIp_P_6 : N12 , " &
" PEX_HSOn_P_6 : N13 , " &
" PEX_HSOp_P_7 : N14 , " &
" PEX_HSOn_P_0 : P1 , " &
" PEX_HSOp_P_1 : P2 , " &
" PEX_HSIn_P_1 : P3 , " &
" PEX_HSIp_P_2 : P4 , " &
" PEX_HSOn_P_2 : P5 , " &
" PEX_HSOp_P_3 : P6 , " &
" PEX_HSIn_P_3 : P7 , " &
" PEX_HSIn_P_4 : P8 , " &
" PEX_HSOp_P_4 : P9 , " &
" PEX_HSOn_P_5 : P10 , " &
" PEX_HSIp_P_5 : P11 , " &
" PEX_HSIn_P_6 : P12 , " &
" PEX_HSOp_P_6 : P13 , " &
" PEX_HSOn_P_7 : P14 , " &
" VDD10 : ( E5, E7, E9, F10, G5, H10, J5, K4, K6, K8, K10 ), " &
" VDD10A : ( J3, L5, L10 ), " &
" VDD10S : ( K2, L3, L7, L13, M2, M4, M6, M8, M10, M12, M14 ), " &
" VDD33 : ( D4, D5, D6, D7, D8, D9, D10, E4, E11, F4, G4, G11, H4, H11, J11 ), " &
" VDD33A : H3 , " &
" VSS : ( A1, A14, E6, E8, E10, F5, F6, F7, F8, F9, G6, G7, G8, G9, G10, H1, " &
" H2, H5, H6, H7, H8, H9, J4, J6, J7, J8, J9, J10, J14, K1, K3, K5, " &
" K7, K9, K13, L2, L8, M3, M5, M7, M9, M11, M13 ) " ;
-- This section specifies the differential IO port groupings.
attribute PORT_GROUPING of altairxl_top: entity is
" Differential_Voltage ( ( PEX_HSIp_P_0 , PEX_HSIn_P_0 ) , " &
" ( PEX_HSIp_P_1 , PEX_HSIn_P_1 ) , " &
" ( PEX_HSIp_P_2 , PEX_HSIn_P_2 ) , " &
" ( PEX_HSIp_P_3 , PEX_HSIn_P_3 ) , " &
" ( PEX_HSIp_P_4 , PEX_HSIn_P_4 ) , " &
" ( PEX_HSIp_P_5 , PEX_HSIn_P_5 ) , " &
" ( PEX_HSIp_P_6 , PEX_HSIn_P_6 ) , " &
" ( PEX_HSIp_P_7 , PEX_HSIn_P_7 ) , " &
" ( PEX_HSOp_P_0 , PEX_HSOn_P_0 ) , " &
" ( PEX_HSOp_P_1 , PEX_HSOn_P_1 ) , " &
" ( PEX_HSOp_P_2 , PEX_HSOn_P_2 ) , " &
" ( PEX_HSOp_P_3 , PEX_HSOn_P_3 ) , " &
" ( PEX_HSOp_P_4 , PEX_HSOn_P_4 ) , " &
" ( PEX_HSOp_P_5 , PEX_HSOn_P_5 ) , " &
" ( PEX_HSOp_P_6 , PEX_HSOn_P_6 ) , " &
" ( PEX_HSOp_P_7 , PEX_HSOn_P_7 ) ) " ;
-- This section specifies the TAP ports. For the TAP TCK port, the parameters in
-- the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of JTAG_TCK_P : signal is (20.0e6, BOTH) ;
attribute TAP_SCAN_IN of JTAG_TDI_P : signal is true ;
attribute TAP_SCAN_MODE of JTAG_TMS_P : signal is true ;
attribute TAP_SCAN_OUT of JTAG_TDO_P : signal is true ;
attribute TAP_SCAN_RESET of JTAG_TRSTn_P : signal is true ;
-- Specifies the compliance enable patterns for the design. It lists a set of
-- design ports and the values that they should be set to, in order to enable
-- compliance to IEEE Std 1149.1
attribute COMPLIANCE_PATTERNS of altairxl_top: entity is
" ( STRAP_TESTMODE_P_3 , STRAP_TESTMODE_P_2 , STRAP_TESTMODE_P_1 , " &
" STRAP_TESTMODE_P_0 ) ( 1111 ) " ;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of altairxl_top: entity is 28;
attribute INSTRUCTION_OPCODE of altairxl_top: entity is
"BYPASS (1111111111111111111111111111)," &
"EXTEST (1111111111111111111111101000)," &
"SAMPLE (1111111111111111111111111000)," &
"PRELOAD (1111111111111111111111111000)," &
"EXTEST_PULSE (1111111110111111111111101000)," &
"EXTEST_TRAIN (1111111010011111111111101000)," &
"CLAMP (1111111111111111111111101111)," &
"IDCODE (1111111111111111111111111110)";
-- Specifies the bit pattern that is loaded into the instruction register when
-- the TAP controller passes through the Capture-IR state. The standard mandates
-- that the two LSBs must be "01". The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of altairxl_top: entity is "0000000000000000000000000001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID register during
-- the IDCODE instruction when the TAP controller passes through the Capture-DR
-- state.
attribute IDCODE_REGISTER of altairxl_top: entity is
-- 4-bit version number
"0000" &
-- 16-bit part number
"1000010100001001" &
-- 11-bit identity of the manufacturer
"00111001101" &
-- Required by IEEE Std 1149.1
"1";
-- This section specifies the test data register placed between TDI and TDO for
-- each implemented instruction.
attribute REGISTER_ACCESS of altairxl_top: entity is
"BYPASS (BYPASS, CLAMP)," &
"BOUNDARY (EXTEST, SAMPLE, PRELOAD)," &
"DEVICE_ID (IDCODE)," &
"BOUNDARY (EXTEST_PULSE, EXTEST_TRAIN)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of altairxl_top: entity is 182;
-- The following list specifies the characteristics of each cell in the boundary
-- scan register from TDI to TDO. The following is a description of the label
-- fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not have a port
-- name.
-- function: Is the function of the cell as defined by the standard. Is one
-- of input, output2, output3, bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be loaded with
-- for safe operation when the software might otherwise choose a
-- random value.
-- ccell : The control cell number. Specifies the control cell that
-- drives the output enable for this port.
-- disval : Specifies the value that is loaded into the control cell to
-- disable the output enable for the corresponding port.
-- rslt : Resulting state. Shows the state of the driver when it is
-- disabled.
attribute BOUNDARY_REGISTER of altairxl_top: entity is
--num cell port function safe [ccell disval rslt]
" 181 ( BC_0 , HP_ATNLEDn_P_2 , output3 , X , 180 , 0 , PULL1 ) , " &
" 180 ( BC_0 , * , control , 0 ) , " &
" 179 ( BC_1 , HP_BUTTONn_P_2 , input , X ) , " &
" 178 ( BC_0 , HP_BUTTONn_P_2 , output3 , X , 177 , 0 , PULL1 ) , " &
" 177 ( BC_0 , * , control , 0 ) , " &
" 176 ( BC_1 , HP_MRLn_P_2 , input , X ) , " &
" 175 ( BC_0 , HP_MRLn_P_2 , output3 , X , 174 , 0 , PULL1 ) , " &
" 174 ( BC_0 , * , control , 0 ) , " &
" 173 ( BC_1 , STRAP_UPSTRM_PORTSEL_P_0 , input , X ) , " &
" 172 ( BC_1 , STRAP_UPSTRM_PORTSEL_P_2 , input , X ) , " &
" 171 ( BC_1 , HP_PWRFLTn_P_2 , input , X ) , " &
" 170 ( BC_0 , HP_PWRFLTn_P_2 , output3 , X , 169 , 0 , PULL1 ) , " &
" 169 ( BC_0 , * , control , 0 ) , " &
" 168 ( BC_1 , STRAP_UPSTRM_PORTSEL_P_1 , input , X ) , " &
" 167 ( BC_0 , HP_PWRENn_P_2 , output3 , X , 166 , 0 , PULL1 ) , " &
" 166 ( BC_0 , * , control , 0 ) , " &
" 165 ( BC_1 , PEX_LANE_GOOD_P_0 , input , X ) , " &
" 164 ( BC_0 , PEX_LANE_GOOD_P_0 , output3 , X , 163 , 0 , Z ) , " &
" 163 ( BC_0 , * , control , 0 ) , " &
" 162 ( BC_1 , HP_PRSNTn_P_2 , input , X ) , " &
" 161 ( BC_0 , HP_PRSNTn_P_2 , output3 , X , 160 , 0 , PULL1 ) , " &
" 160 ( BC_0 , * , control , 0 ) , " &
" 159 ( BC_1 , PEX_LANE_GOOD_P_1 , input , X ) , " &
" 158 ( BC_0 , PEX_LANE_GOOD_P_1 , output3 , X , 157 , 0 , Z ) , " &
" 157 ( BC_0 , * , control , 0 ) , " &
" 156 ( BC_0 , HP_PERSTn_P_2 , output3 , X , 155 , 0 , PULL1 ) , " &
" 155 ( BC_0 , * , control , 0 ) , " &
" 154 ( BC_1 , PEX_LANE_GOOD_P_2 , input , X ) , " &
" 153 ( BC_0 , PEX_LANE_GOOD_P_2 , output3 , X , 152 , 0 , Z ) , " &
" 152 ( BC_0 , * , control , 0 ) , " &
" 151 ( BC_0 , HP_PWRLEDn_P_2 , output3 , X , 150 , 0 , PULL1 ) , " &
" 150 ( BC_0 , * , control , 0 ) , " &
" 149 ( BC_0 , HP_CLKENn_P_2 , output3 , X , 148 , 0 , PULL1 ) , " &
" 148 ( BC_0 , * , control , 0 ) , " &
" 147 ( BC_1 , PEX_LANE_GOOD_P_3 , input , X ) , " &
" 146 ( BC_0 , PEX_LANE_GOOD_P_3 , output3 , X , 145 , 0 , Z ) , " &
" 145 ( BC_0 , * , control , 0 ) , " &
" 144 ( BC_1 , STRAP_SERDES_MODE_ENn_P , input , X ) , " &
" 143 ( BC_1 , PEX_INTAn_P , input , X ) , " &
" 142 ( BC_0 , PEX_INTAn_P , output3 , X , 141 , 0 , Z ) , " &
" 141 ( BC_0 , * , control , 0 ) , " &
" 140 ( BC_1 , HP_BUTTONn_P_1 , input , X ) , " &
" 139 ( BC_0 , HP_BUTTONn_P_1 , output3 , X , 138 , 0 , PULL1 ) , " &
" 138 ( BC_0 , * , control , 0 ) , " &
" 137 ( BC_1 , HP_ATNLEDn_P_1 , input , X ) , " &
" 136 ( BC_0 , HP_ATNLEDn_P_1 , output3 , X , 135 , 0 , PULL1 ) , " &
" 135 ( BC_0 , * , control , 0 ) , " &
" 134 ( BC_1 , PEX_LANE_GOOD_P_4 , input , X ) , " &
" 133 ( BC_0 , PEX_LANE_GOOD_P_4 , output3 , X , 132 , 0 , Z ) , " &
" 132 ( BC_0 , * , control , 0 ) , " &
" 131 ( BC_1 , HP_MRLn_P_1 , input , X ) , " &
" 130 ( BC_0 , HP_MRLn_P_1 , output3 , X , 129 , 0 , PULL1 ) , " &
" 129 ( BC_0 , * , control , 0 ) , " &
" 128 ( BC_1 , HP_PWRFLTn_P_1 , input , X ) , " &
" 127 ( BC_0 , HP_PWRFLTn_P_1 , output3 , X , 126 , 0 , PULL1 ) , " &
" 126 ( BC_0 , * , control , 0 ) , " &
" 125 ( BC_1 , PEX_LANE_GOOD_P_5 , input , X ) , " &
" 124 ( BC_0 , PEX_LANE_GOOD_P_5 , output3 , X , 123 , 0 , Z ) , " &
" 123 ( BC_0 , * , control , 0 ) , " &
" 122 ( BC_0 , HP_PWRENn_P_1 , output3 , X , 121 , 0 , PULL1 ) , " &
" 121 ( BC_0 , * , control , 0 ) , " &
" 120 ( BC_1 , HP_PRSNTn_P_1 , input , X ) , " &
" 119 ( BC_0 , HP_PRSNTn_P_1 , output3 , X , 118 , 0 , PULL1 ) , " &
" 118 ( BC_0 , * , control , 0 ) , " &
" 117 ( BC_0 , HP_PERSTn_P_1 , output3 , X , 116 , 0 , PULL1 ) , " &
" 116 ( BC_0 , * , control , 0 ) , " &
" 115 ( BC_0 , HP_PWRLEDn_P_1 , output3 , X , 114 , 0 , PULL1 ) , " &
" 114 ( BC_0 , * , control , 0 ) , " &
" 113 ( BC_0 , HP_CLKENn_P_1 , output3 , X , 112 , 0 , PULL1 ) , " &
" 112 ( BC_0 , * , control , 0 ) , " &
" 111 ( BC_1 , PROCMON_P , input , X ) , " &
" 110 ( BC_0 , PROCMON_P , output3 , X , 109 , 0 , Z ) , " &
" 109 ( BC_0 , * , control , 0 ) , " &
" 108 ( BC_1 , STRAP_PLL_BYPASSn_P , input , X ) , " &
" 107 ( BC_1 , STRAP_FAST_BRINGUPn_P , input , X ) , " &
-- SERDES_S0
" 106 ( AC_SELU , * , internal , 0 ) , " &
" 105 ( AC_1 , PEX_HSOp_P_0 , output2 , X ) , " &
" 104 ( BC_1 , * , internal , 1 ) , " &
" 103 ( BC_4 , PEX_HSIp_P_0 , observe_only , X ) , " &
" 102 ( BC_4 , PEX_HSIn_P_0 , observe_only , X ) , " &
" 101 ( BC_4 , PEX_HSIn_P_1 , observe_only , X ) , " &
" 100 ( BC_4 , PEX_HSIp_P_1 , observe_only , X ) , " &
" 99 ( BC_1 , * , internal , 1 ) , " &
" 98 ( AC_SELU , * , internal , 0 ) , " &
" 97 ( AC_1 , PEX_HSOp_P_1 , output2 , X ) , " &
" 96 ( AC_SELU , * , internal , 0 ) , " &
" 95 ( AC_1 , PEX_HSOp_P_2 , output2 , X ) , " &
" 94 ( BC_1 , * , internal , 1 ) , " &
" 93 ( BC_4 , PEX_HSIp_P_2 , observe_only , X ) , " &
" 92 ( BC_4 , PEX_HSIn_P_2 , observe_only , X ) , " &
" 91 ( BC_4 , PEX_HSIn_P_3 , observe_only , X ) , " &
" 90 ( BC_4 , PEX_HSIp_P_3 , observe_only , X ) , " &
" 89 ( BC_1 , * , internal , 1 ) , " &
" 88 ( AC_SELU , * , internal , 0 ) , " &
" 87 ( AC_1 , PEX_HSOp_P_3 , output2 , X ) , " &
-- SERDES_S1
" 86 ( AC_SELU , * , internal , 0 ) , " &
" 85 ( AC_1 , PEX_HSOp_P_4 , output2 , X ) , " &
" 84 ( BC_1 , * , internal , 1 ) , " &
" 83 ( BC_4 , PEX_HSIp_P_4 , observe_only , X ) , " &
" 82 ( BC_4 , PEX_HSIn_P_4 , observe_only , X ) , " &
" 81 ( BC_4 , PEX_HSIn_P_5 , observe_only , X ) , " &
" 80 ( BC_4 , PEX_HSIp_P_5 , observe_only , X ) , " &
" 79 ( BC_1 , * , internal , 1 ) , " &
" 78 ( AC_SELU , * , internal , 0 ) , " &
" 77 ( AC_1 , PEX_HSOp_P_5 , output2 , X ) , " &
" 76 ( AC_SELU , * , internal , 0 ) , " &
" 75 ( AC_1 , PEX_HSOp_P_6 , output2 , X ) , " &
" 74 ( BC_1 , * , internal , 1 ) , " &
" 73 ( BC_4 , PEX_HSIp_P_6 , observe_only , X ) , " &
" 72 ( BC_4 , PEX_HSIn_P_6 , observe_only , X ) , " &
" 71 ( BC_4 , PEX_HSIn_P_7 , observe_only , X ) , " &
" 70 ( BC_4 , PEX_HSIp_P_7 , observe_only , X ) , " &
" 69 ( BC_1 , * , internal , 1 ) , " &
" 68 ( AC_SELU , * , internal , 0 ) , " &
" 67 ( AC_1 , PEX_HSOp_P_7 , output2 , X ) , " &
--
" 66 ( BC_1 , I2C_ADDR_P_0 , input , X ) , " &
" 65 ( BC_1 , I2C_ADDR_P_1 , input , X ) , " &
" 64 ( BC_1 , I2C_ADDR_P_2 , input , X ) , " &
" 63 ( BC_1 , FATAL_ERRn_P , input , X ) , " &
" 62 ( BC_0 , FATAL_ERRn_P , output3 , X , 61 , 0 , Z ) , " &
" 61 ( BC_0 , * , control , 0 ) , " &
" 60 ( BC_1 , SPARE2_P , input , X ) , " &
" 59 ( BC_0 , SPARE2_P , output3 , X , 58 , 0 , PULL1 ) , " &
" 58 ( BC_0 , * , control , 0 ) , " &
" 57 ( BC_0 , I2C_SCL_P , output3 , X , 56 , 0 , Z ) , " &
" 56 ( BC_0 , * , control , 0 ) , " &
" 55 ( BC_1 , I2C_SCL_P , input , X ) , " &
" 54 ( BC_0 , I2C_SDA_P , output3 , X , 53 , 0 , Z ) , " &
" 53 ( BC_0 , * , control , 0 ) , " &
" 52 ( BC_1 , I2C_SDA_P , input , X ) , " &
" 51 ( BC_1 , STRAP_PROBE_MODEn_P , input , X ) , " &
" 50 ( BC_0 , EE_DI_P , output3 , X , 49 , 0 , Z ) , " &
" 49 ( BC_0 , * , control , 0 ) , " &
" 48 ( BC_0 , EE_CS_P , output3 , X , 47 , 0 , Z ) , " &
" 47 ( BC_0 , * , control , 0 ) , " &
" 46 ( BC_1 , EE_SK_P , input , X ) , " &
" 45 ( BC_0 , EE_SK_P , output3 , X , 44 , 0 , Z ) , " &
" 44 ( BC_0 , * , control , 0 ) , " &
" 43 ( BC_1 , STN0_STRAP_PORTCFG_P_0 , input , X ) , " &
" 42 ( BC_1 , EE_DO_P , input , X ) , " &
" 41 ( BC_0 , EE_DO_P , output3 , X , 40 , 0 , PULL1 ) , " &
" 40 ( BC_0 , * , control , 0 ) , " &
" 39 ( BC_1 , STN0_STRAP_PORTCFG_P_1 , input , X ) , " &
" 38 ( BC_0 , HP_CLKENn_P_3 , output3 , X , 37 , 0 , PULL1 ) , " &
" 37 ( BC_0 , * , control , 0 ) , " &
" 36 ( BC_0 , HP_PWRLEDn_P_3 , output3 , X , 35 , 0 , PULL1 ) , " &
" 35 ( BC_0 , * , control , 0 ) , " &
" 34 ( BC_1 , SPARE1_P , input , X ) , " &
" 33 ( BC_0 , SPARE1_P , output3 , X , 32 , 0 , PULL1 ) , " &
" 32 ( BC_0 , * , control , 0 ) , " &
" 31 ( BC_0 , HP_PERSTn_P_3 , output3 , X , 30 , 0 , PULL1 ) , " &
" 30 ( BC_0 , * , control , 0 ) , " &
" 29 ( BC_1 , HP_PRSNTn_P_3 , input , X ) , " &
" 28 ( BC_0 , HP_PRSNTn_P_3 , output3 , X , 27 , 0 , PULL1 ) , " &
" 27 ( BC_0 , * , control , 0 ) , " &
" 26 ( BC_1 , PEX_LANE_GOOD_P_6 , input , X ) , " &
" 25 ( BC_0 , PEX_LANE_GOOD_P_6 , output3 , X , 24 , 0 , Z ) , " &
" 24 ( BC_0 , * , control , 0 ) , " &
" 23 ( BC_0 , HP_PWRENn_P_3 , output3 , X , 22 , 0 , PULL1 ) , " &
" 22 ( BC_0 , * , control , 0 ) , " &
" 21 ( BC_1 , HP_PWRFLTn_P_3 , input , X ) , " &
" 20 ( BC_0 , HP_PWRFLTn_P_3 , output3 , X , 19 , 0 , PULL1 ) , " &
" 19 ( BC_0 , * , control , 0 ) , " &
" 18 ( BC_0 , PEX_LANE_GOOD_P_7 , output3 , X , 17 , 0 , Z ) , " &
" 17 ( BC_0 , * , control , 0 ) , " &
" 16 ( BC_1 , HP_MRLn_P_3 , input , X ) , " &
" 15 ( BC_0 , HP_MRLn_P_3 , output3 , X , 14 , 0 , PULL1 ) , " &
" 14 ( BC_0 , * , control , 0 ) , " &
" 13 ( BC_0 , HP_ATNLEDn_P_3 , output3 , X , 12 , 0 , PULL1 ) , " &
" 12 ( BC_0 , * , control , 0 ) , " &
" 11 ( BC_1 , HP_BUTTONn_P_3 , input , X ) , " &
" 10 ( BC_0 , HP_BUTTONn_P_3 , output3 , X , 9 , 0 , PULL1 ) , " &
" 9 ( BC_0 , * , control , 0 ) , " &
" 8 ( BC_1 , STRAP_DEBUG_SEL_P_1 , input , X ) , " &
" 7 ( BC_1 , STRAP_DEBUG_SEL_P_0 , input , X ) , " &
" 6 ( BC_1 , SPARE0_P , input , X ) , " &
" 5 ( BC_0 , SPARE0_P , output3 , X , 4 , 0 , PULL1 ) , " &
" 4 ( BC_0 , * , control , 0 ) , " &
" 3 ( BC_1 , * , internal , X ) , " &
" 2 ( BC_1 , * , internal , X ) , " &
" 1 ( BC_1 , * , internal , X ) , " &
" 0 ( BC_1 , * , internal , X ) " ;
attribute AIO_COMPONENT_CONFORMANCE of altairxl_top: entity is "STD_1149_6_2003";
attribute AIO_Pin_BEHAVIOR of altairxl_top : entity is
" PEX_HSIp_P_0[103] , " &
" PEX_HSIp_P_1[100] , " &
" PEX_HSIp_P_2[93] , " &
" PEX_HSIp_P_3[90] , " &
" PEX_HSIp_P_4[83] , " &
" PEX_HSIp_P_5[80] , " &
" PEX_HSIp_P_6[73] , " &
" PEX_HSIp_P_7[70] : LP_time = 6.75e-9 HP_time = 13.5e-9 ; " &
" PEX_HSOp_P_0 : AC_Select = 106 ; " &
" PEX_HSOp_P_1 : AC_Select = 98 ; " &
" PEX_HSOp_P_2 : AC_Select = 96 ; " &
" PEX_HSOp_P_3 : AC_Select = 88 ; " &
" PEX_HSOp_P_4 : AC_Select = 86 ; " &
" PEX_HSOp_P_5 : AC_Select = 78 ; " &
" PEX_HSOp_P_6 : AC_Select = 76 ; " &
" PEX_HSOp_P_7 : AC_Select = 68 " ;
end altairxl_top;
