BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: TE11CHIP_JTAG

	--  ********************************************************************
--  *
--  *  Module : te11chip_jtag
--  *  Created: Wed Jan  2 19:45:54 2008
--  *  By     : BSCAN2BSDL
--  *           bscan2bsdl te11chip_jtag
--  *  (c) 1991-2001, SynTest Technologies, Inc.
--  *
--  ********************************************************************

entity te11chip_jtag is
  --
  -- Generic Parameter
  --
  generic (PHYSICAL_PIN_MAP : string := "QFP");

  --
  -- Logical Port Description
  --
  port (
          lop: in bit;
          mclkin: in bit;
          mclkoutxn: out bit;
          rxoh_0: out bit;
          rxchn_0_4: out bit;
          rxchn_0_3: out bit;
          rxcasync_0: out bit;
          rxohclk_0: out bit;
          rxchn_0_2: out bit;
          rxsync_0: inout bit;
          rxchn_0_1: out bit;
          rxchclk_0: out bit;
          rxcrcsync_0: out bit;
          rxchn_0_0: out bit;
          rxserclk_0: inout bit;
          rxlos_0: out bit;
          rxser_0: out bit;
          txchn_0_4: out bit;
          txchn_0_3: out bit;
          txchn_0_2: out bit;
          txchclk_0: inout bit;
          txchn_0_1: inout bit;
          txoh_0: in bit;
          txchn_0_0: inout bit;
          txserclk_0: inout bit;
          txser_0: in bit;
          txohclk_0: out bit;
          txmsync_0: inout bit;
          txsync_0: inout bit;
          preq_l_1: out bit;
          pack_l_0: in bit;
          preq_l_0: out bit;
          pack_l_1: in bit;
          pclk: in bit;
          pdata_0: inout bit;
          pdata_1: inout bit;
          prd_l: in bit;
          pdben_l: in bit;
          pdack_l: out bit;
          paddr_0: in bit;
          paddr_1: in bit;
          paddr_2: in bit;
          paddr_3: in bit;
          paddr_4: in bit;
          paddr_5: in bit;
          paddr_6: in bit;
          paddr_7: in bit;
          reset_l_oe: in bit;
          oscclk: inout bit;
          eightkhzsync: inout bit;
          paddr_0_8: in bit;
          pdata_2: inout bit;
          pdata_3: inout bit;
          pas_l: in bit;
          paddr_1_9: in bit;
          paddr_2_10: in bit;
          pint_l: out bit;
          paddr_3_11: in bit;
          pblast_l: in bit;
          pdata_4: inout bit;
          pdata_5: inout bit;
          pdata_6: inout bit;
          pdata_7: inout bit;
          pwr_l: in bit;
          pcs_l: in bit;
          tck: in bit;
          trst: in bit;
          tdi: in bit;
          tms: in bit;
          tdo: out bit;
          gpio_0_1: inout bit;
          gpio_0_0: inout bit;
          gpio_0_2: inout bit;
          gpio_0_3: inout bit;
          atestmode: in bit;
          testmode: in bit;
          ext_osc_8k: in bit;
          fulladdr: in bit;
          indirectaddr: in bit;
          ptype_2: in bit;
          ptype_1: in bit;
          ptype_0: in bit;
          TXON_PAD: in bit
       );

  --
  -- Use Statements
  --
  use STD_1149_1_1994.all;  -- Get Std 1149.1-1994 attributes and definitions

  attribute COMPONENT_CONFORMANCE of te11chip_jtag : entity is "STD_1149_1_1993";

  --
  -- Package Pin Mapping
  --
  attribute PIN_MAP of te11chip_jtag : entity is PHYSICAL_PIN_MAP;
  constant QFP:PIN_MAP_STRING:=
          "lop : 1," &
          "mclkin : 24," &
          "mclkoutxn : 25," &
          "rxoh_0 : 26," &
          "rxchn_0_4 : 27," &
          "rxchn_0_3 : 28," &
          "rxcasync_0 : 30," &
          "rxohclk_0 : 31," &
          "rxchn_0_2 : 32," &
          "rxsync_0 : 33," &
          "rxchn_0_1 : 36," &
          "rxchclk_0 : 38," &
          "rxcrcsync_0 : 39," &
          "rxchn_0_0 : 40," &
          "rxserclk_0 : 42," &
          "rxlos_0 : 43," &
          "rxser_0 : 44," &
          "txchn_0_4 : 45," &
          "txchn_0_3 : 46," &
          "txchn_0_2 : 47," &
          "txchclk_0 : 49," &
          "txchn_0_1 : 50," &
          "txoh_0 : 51," &
          "txchn_0_0 : 53," &
          "txserclk_0 : 54," &
          "txser_0 : 55," &
          "txohclk_0 : 57," &
          "txmsync_0 : 58," &
          "txsync_0 : 59," &
          "preq_l_1 : 61," &
          "pack_l_0 : 62," &
          "preq_l_0 : 64," &
          "pack_l_1 : 65," &
          "pclk : 68," &
          "pdata_0 : 69," &
          "pdata_1 : 70," &
          "prd_l : 71," &
          "pdben_l : 73," &
          "pdack_l : 74," &
          "paddr_0 : 75," &
          "paddr_1 : 76," &
          "paddr_2 : 77," &
          "paddr_3 : 79," &
          "paddr_4 : 80," &
          "paddr_5 : 81," &
          "paddr_6 : 82," &
          "paddr_7 : 84," &
          "reset_l_oe : 85," &
          "oscclk : 86," &
          "eightkhzsync : 88," &
          "paddr_0_8 : 89," &
          "pdata_2 : 90," &
          "pdata_3 : 91," &
          "pas_l : 93," &
          "paddr_1_9 : 94," &
          "paddr_2_10 : 95," &
          "pint_l : 96," &
          "paddr_3_11 : 97," &
          "pblast_l : 100," &
          "pdata_4 : 101," &
          "pdata_5 : 103," &
          "pdata_6 : 104," &
          "pdata_7 : 106," &
          "pwr_l : 107," &
          "pcs_l : 108," &
          "tck : 111," &
          "trst : 112," &
          "tdi : 113," &
          "tms : 114," &
          "tdo : 115," &
          "gpio_0_1 : 116," &
          "gpio_0_0 : 117," &
          "gpio_0_2 : 118," &
          "gpio_0_3 : 119," &
          "atestmode : 120," &
          "testmode : 121," &
          "ext_osc_8k : 122," &
          "fulladdr : 123," &
          "indirectaddr : 124," &
          "ptype_2 : 125," &
          "ptype_1 : 126," &
          "ptype_0 : 127," &
          "TXON_PAD : 128";

  --
  -- Scan Port Identification
  --
  attribute TAP_SCAN_IN of tdi : signal is true;
  attribute TAP_SCAN_MODE of tms : signal is true;
  attribute TAP_SCAN_OUT of tdo : signal is true;
  attribute TAP_SCAN_RESET of trst : signal is true;
  attribute TAP_SCAN_CLOCK of tck : signal is (25.0e6,BOTH);

  --
  -- TAP Instruction Description
  --
  attribute INSTRUCTION_LENGTH of te11chip_jtag : entity is 4;
  attribute INSTRUCTION_OPCODE of te11chip_jtag : entity is
    "BYPASS     (1111),"  &
    "EXTEST     (0000),"  &
    "IDCODE     (0001),"  &
    "SAMPLE     (0011),"  &
    "HIGHZ      (1101),"  &
    "SYNTEST_ATPG (1010),"  &
    "BIST_MODE  (0110)";
  attribute INSTRUCTION_CAPTURE of te11chip_jtag : entity is "0001";
  attribute IDCODE_REGISTER of te11chip_jtag : entity is
      "0001" &                -- 4-bit version
      "0000000000111000" &    -- 16-bit part number
      "00001011110" &         -- 11-bit manufacturer
      "1";                    -- mandatory LSB

  attribute REGISTER_ACCESS of te11chip_jtag : entity is
  -- these are given by standard
  -- "BOUNDARY(EXTEST,SAMPLE,INTEST)";
  -- "BYPASS(BYPASS)";
     "BYPASS    (BYPASS)," &
     "BOUNDARY  (EXTEST)," &
     "DEVICE_ID (IDCODE)," &
     "BOUNDARY  (SAMPLE)," &
     "BYPASS    (HIGHZ)," &
     "BYPASS    (SYNTEST_ATPG)," &
     "BIST[45]  (BIST_MODE)";



  --
  -- Boundary Register Description for 1149.1 Boundary_Scan_Cell
  --
  attribute BOUNDARY_LENGTH of te11chip_jtag : entity is 94;


  attribute BOUNDARY_REGISTER of te11chip_jtag : entity is
  -- num   cell         port          function  safe [ccell disval rslt]

    "0    (BC_7        ,gpio_0_1     ,bidir    ,X   ,1    ,0     ,Z)," &
    "1    (BC_1        ,*            ,control  ,0)," &
    "2    (BC_7        ,gpio_0_0     ,bidir    ,X   ,3    ,0     ,Z)," &
    "3    (BC_1        ,*            ,control  ,0)," &
    "4    (BC_7        ,gpio_0_2     ,bidir    ,X   ,5    ,0     ,Z)," &
    "5    (BC_1        ,*            ,control  ,0)," &
    "6    (BC_7        ,gpio_0_3     ,bidir    ,X   ,7    ,0     ,Z)," &
    "7    (BC_1        ,*            ,control  ,0)," &
    "8    (BC_1        ,atestmode    ,input    ,X)," &
    "9    (BC_1        ,testmode     ,input    ,X)," &
    "10   (BC_1        ,ext_osc_8k   ,input    ,X)," &
    "11   (BC_1        ,fulladdr     ,input    ,X)," &
    "12   (BC_1        ,indirectaddr ,input    ,X)," &
    "13   (BC_1        ,ptype_2      ,input    ,X)," &
    "14   (BC_1        ,ptype_1      ,input    ,X)," &
    "15   (BC_1        ,ptype_0      ,input    ,X)," &
    "16   (BC_1        ,TXON_PAD     ,input    ,X)," &
    "17   (BC_1        ,lop          ,input    ,X)," &
    "18   (BC_1        ,mclkin       ,input    ,X)," &
    "19   (BC_1        ,mclkoutxn    ,output3  ,X   ,20   ,0     ,Z)," &
    "20   (BC_1        ,*            ,control  ,0)," &
    "21   (BC_1        ,rxoh_0       ,output3  ,X   ,20   ,0     ,Z)," &
    "22   (BC_1        ,rxchn_0_4    ,output3  ,X   ,20   ,0     ,Z)," &
    "23   (BC_1        ,rxchn_0_3    ,output3  ,X   ,20   ,0     ,Z)," &
    "24   (BC_1        ,rxcasync_0   ,output3  ,X   ,20   ,0     ,Z)," &
    "25   (BC_1        ,rxohclk_0    ,output3  ,X   ,20   ,0     ,Z)," &
    "26   (BC_1        ,rxchn_0_2    ,output3  ,X   ,20   ,0     ,Z)," &
    "27   (BC_7        ,rxsync_0     ,bidir    ,X   ,28   ,0     ,PULL0)," &
    "28   (BC_1        ,*            ,control  ,0)," &
    "29   (BC_1        ,rxchn_0_1    ,output3  ,X   ,20   ,0     ,Z)," &
    "30   (BC_1        ,rxchclk_0    ,output3  ,X   ,20   ,0     ,Z)," &
    "31   (BC_1        ,rxcrcsync_0  ,output3  ,X   ,20   ,0     ,Z)," &
    "32   (BC_1        ,rxchn_0_0    ,output3  ,X   ,33   ,0     ,Z)," &
    "33   (BC_1        ,*            ,control  ,0)," &
    "34   (BC_7        ,rxserclk_0   ,bidir    ,X   ,35   ,0     ,PULL1)," &
    "35   (BC_1        ,*            ,control  ,0)," &
    "36   (BC_1        ,rxlos_0      ,output3  ,X   ,37   ,0     ,Z)," &
    "37   (BC_1        ,*            ,control  ,0)," &
    "38   (BC_1        ,rxser_0      ,output3  ,X   ,39   ,0     ,Z)," &
    "39   (BC_1        ,*            ,control  ,0)," &
    "40   (BC_1        ,txchn_0_4    ,output3  ,X   ,20   ,0     ,Z)," &
    "41   (BC_1        ,txchn_0_3    ,output3  ,X   ,20   ,0     ,Z)," &
    "42   (BC_1        ,txchn_0_2    ,output3  ,X   ,20   ,0     ,Z)," &
    "43   (BC_7        ,txchclk_0    ,bidir    ,X   ,44   ,0     ,PULL0)," &
    "44   (BC_1        ,*            ,control  ,0)," &
    "45   (BC_7        ,txchn_0_1    ,bidir    ,X   ,46   ,0     ,PULL0)," &
    "46   (BC_1        ,*            ,control  ,0)," &
    "47   (BC_1        ,txoh_0       ,input    ,X)," &
    "48   (BC_7        ,txchn_0_0    ,bidir    ,X   ,46   ,0     ,PULL0)," &
    "49   (BC_7        ,txserclk_0   ,bidir    ,X   ,50   ,0     ,PULL1)," &
    "50   (BC_1        ,*            ,control  ,0)," &
    "51   (BC_1        ,txser_0      ,input    ,X)," &
    "52   (BC_1        ,txohclk_0    ,output3  ,X   ,20   ,0     ,Z)," &
    "53   (BC_7        ,txmsync_0    ,bidir    ,X   ,54   ,0     ,PULL0)," &
    "54   (BC_1        ,*            ,control  ,0)," &
    "55   (BC_7        ,txsync_0     ,bidir    ,X   ,54   ,0     ,PULL0)," &
    "56   (BC_1        ,preq_l_1     ,output3  ,X   ,20   ,0     ,Z)," &
    "57   (BC_1        ,pack_l_0     ,input    ,X)," &
    "58   (BC_1        ,preq_l_0     ,output3  ,X   ,20   ,0     ,Z)," &
    "59   (BC_1        ,pack_l_1     ,input    ,X)," &
    "60   (BC_1        ,pclk         ,input    ,X)," &
    "61   (BC_7        ,pdata_0      ,bidir    ,X   ,62   ,0     ,Z)," &
    "62   (BC_1        ,*            ,control  ,0)," &
    "63   (BC_7        ,pdata_1      ,bidir    ,X   ,62   ,0     ,Z)," &
    "64   (BC_1        ,prd_l        ,input    ,X)," &
    "65   (BC_1        ,pdben_l      ,input    ,X)," &
    "66   (BC_1        ,pdack_l      ,output3  ,X   ,20   ,0     ,Z)," &
    "67   (BC_1        ,paddr_0      ,input    ,X)," &
    "68   (BC_1        ,paddr_1      ,input    ,X)," &
    "69   (BC_1        ,paddr_2      ,input    ,X)," &
    "70   (BC_1        ,paddr_3      ,input    ,X)," &
    "71   (BC_1        ,paddr_4      ,input    ,X)," &
    "72   (BC_1        ,paddr_5      ,input    ,X)," &
    "73   (BC_1        ,paddr_6      ,input    ,X)," &
    "74   (BC_1        ,paddr_7      ,input    ,X)," &
    "75   (BC_1        ,reset_l_oe   ,input    ,X)," &
    "76   (BC_7        ,oscclk       ,bidir    ,X   ,77   ,0     ,PULL0)," &
    "77   (BC_1        ,*            ,control  ,0)," &
    "78   (BC_7        ,eightkhzsync ,bidir    ,X   ,77   ,0     ,PULL0)," &
    "79   (BC_1        ,paddr_0_8    ,input    ,X)," &
    "80   (BC_7        ,pdata_2      ,bidir    ,X   ,62   ,0     ,Z)," &
    "81   (BC_7        ,pdata_3      ,bidir    ,X   ,62   ,0     ,Z)," &
    "82   (BC_1        ,pas_l        ,input    ,X)," &
    "83   (BC_1        ,paddr_1_9    ,input    ,X)," &
    "84   (BC_1        ,paddr_2_10   ,input    ,X)," &
    "85   (BC_1        ,pint_l       ,output3  ,X   ,20   ,0     ,Z)," &
    "86   (BC_1        ,paddr_3_11   ,input    ,X)," &
    "87   (BC_1        ,pblast_l     ,input    ,X)," &
    "88   (BC_7        ,pdata_4      ,bidir    ,X   ,62   ,0     ,Z)," &
    "89   (BC_7        ,pdata_5      ,bidir    ,X   ,62   ,0     ,Z)," &
    "90   (BC_7        ,pdata_6      ,bidir    ,X   ,62   ,0     ,Z)," &
    "91   (BC_7        ,pdata_7      ,bidir    ,X   ,62   ,0     ,Z)," &
    "92   (BC_1        ,pwr_l        ,input    ,X)," &
    "93   (BC_1        ,pcs_l        ,input    ,X)";

end te11chip_jtag;