-- ***********************************************************************
-- BSDL file for design DBMX
-- Created by Synopsys Version 2001.08-SP1 (Nov 12, 2001)
-- Designer: saurabh
-- Company: Motorola Electronics Pte Ltd
-- Date: Sat Jun 8 23:21:42 2002
-- ***********************************************************************
entity DBMX is
-- This section identifies the default device package selected.
generic (PHYSICAL_PIN_MAP: string:= "BGA");
-- This section declares all the ports in the design.
port (
big_endian_128_pad : in bit;
-- pll_byp_b_146_pad : in bit;
-- prem_byp_b_147_pad : in bit;
reset_in_b_125_pad : in bit;
tck_152_pad : in bit;
tdi_153_pad : in bit;
tms_151_pad : in bit;
trst_b_134_pad : in bit;
a0_pa21_78_pad : inout bit;
a16_dbg9_pa24_22_pad : inout bit;
a17_dbg8_pa25_20_pad : inout bit;
a18_dbg7_pa26_18_pad : inout bit;
a19_dbg6_pa27_14_pad : inout bit;
a20_dbg5_pa28_12_pad : inout bit;
a21_dbg4_pa29_10_pad : inout bit;
a22_dbg3_pa30_6_pad : inout bit;
a23_dbg2_pa31_4_pad : inout bit;
a24_dbg1_pa0_2_pad : inout bit;
bclk_b_pa18_96_pad : inout bit;
bt10_ssi2_txdat_pc22_242_pad : inout bit;
bt11_ssi2_txclk_pc21_243_pad : inout bit;
bt12_ssi2_txfs_pc20_244_pad : inout bit;
bt13_ssi2_rxclk_pc19_245_pad : inout bit;
bt1_pc31_233_pad : inout bit;
bt2_pc30_234_pad : inout bit;
bt3_pc29_235_pad : inout bit;
bt4_pc28_236_pad : inout bit;
bt5_pc27_237_pad : inout bit;
bt6_pc26_238_pad : inout bit;
bt7_pc25_239_pad : inout bit;
bt8_ssi2_rxfs_pc24_240_pad : inout bit;
bt9_ssi2_rxdat_pc23_241_pad : inout bit;
clk_ms2_pb12_292_pad : inout bit;
cls_uart2_dco_pd8_201_pad : inout bit;
cmd_ms1_pb13_291_pad : inout bit;
contrast_pd11_198_pad : inout bit;
cs4_b_pa22_77_pad : inout bit;
cs5_b_pa23_73_pad : inout bit;
csi_d0_pa4_168_pad : inout bit;
csi_d1_pa5_167_pad : inout bit;
csi_d2_pa6_166_pad : inout bit;
csi_d3_pa7_165_pad : inout bit;
csi_d4_pa8_164_pad : inout bit;
csi_d5_pa9_161_pad : inout bit;
csi_d6_pa10_160_pad : inout bit;
csi_d7_pa11_159_pad : inout bit;
csi_hsync_pa13_157_pad : inout bit;
csi_mclk_pa3_169_pad : inout bit;
csi_pixclk_pa14_156_pad : inout bit;
csi_vsync_pa12_158_pad : inout bit;
d0_105_pad : inout bit;
d10_61_pad : inout bit;
d11_57_pad : inout bit;
d12_55_pad : inout bit;
d13_53_pad : inout bit;
d14_49_pad : inout bit;
d15_47_pad : inout bit;
d16_45_pad : inout bit;
d17_41_pad : inout bit;
d18_39_pad : inout bit;
d19_37_pad : inout bit;
d1_101_pad : inout bit;
d20_31_pad : inout bit;
d21_29_pad : inout bit;
d22_27_pad : inout bit;
d23_23_pad : inout bit;
d24_21_pad : inout bit;
d25_19_pad : inout bit;
d26_15_pad : inout bit;
d27_13_pad : inout bit;
d28_11_pad : inout bit;
d29_7_pad : inout bit;
d2_97_pad : inout bit;
d30_5_pad : inout bit;
d31_3_pad : inout bit;
d3_95_pad : inout bit;
d4_93_pad : inout bit;
d5_89_pad : inout bit;
d6_80_pad : inout bit;
d7_76_pad : inout bit;
d8_70_pad : inout bit;
d9_64_pad : inout bit;
dat0_pb8_296_pad : inout bit;
dat1_pb9_295_pad : inout bit;
dat2_pb10_294_pad : inout bit;
dat3_ms3_pb11_293_pad : inout bit;
dqm0_111_pad : inout bit;
dqm1_110_pad : inout bit;
dqm2_109_pad : inout bit;
dqm3_108_pad : inout bit;
ecb_b_pa20_92_pad : inout bit;
hsync_pd13_196_pad : inout bit;
i2c_clk_pa16_154_pad : inout bit;
i2c_data_pa15_155_pad : inout bit;
lba_b_pa19_94_pad : inout bit;
ld0_pd15_194_pad : inout bit;
ld10_pd25_182_pad : inout bit;
ld11_pd26_181_pad : inout bit;
ld12_pd27_176_pad : inout bit;
ld13_pd28_175_pad : inout bit;
ld14_pd29_174_pad : inout bit;
ld15_pd30_173_pad : inout bit;
ld1_pd16_193_pad : inout bit;
ld2_pd17_190_pad : inout bit;
ld3_pd18_189_pad : inout bit;
ld4_pd19_188_pad : inout bit;
ld5_pd20_187_pad : inout bit;
ld6_pd21_186_pad : inout bit;
ld7_pd22_185_pad : inout bit;
ld8_pd23_184_pad : inout bit;
ld9_pd24_183_pad : inout bit;
lsclk_pd6_203_pad : inout bit;
miso_pc16_249_pad : inout bit;
mosi_pc17_248_pad : inout bit;
oe_acd_pd12_197_pad : inout bit;
pa17_100_pad : inout bit;
ps_uart2_ri_pd9_200_pad : inout bit;
pwmo_pa2_170_pad : inout bit;
rev_uart2_dtr_pd7_202_pad : inout bit;
sclk_pc14_251_pad : inout bit;
sdclk_86_pad : inout bit;
sim_clk_ssi1_txclk_pb19_283_pad : inout bit;
sim_pd_ssi1_rxclk_pb15_287_pad : inout bit;
sim_rst_ssi1_txfs_pb18_284_pad : inout bit;
sim_rx_ssi1_txdat_pb17_285_pad : inout bit;
sim_sven_ssi1_rxfs_pb14_288_pad : inout bit;
sim_tx_ssi1_rxdat_pb16_286_pad : inout bit;
spi_rdy_pc13_252_pad : inout bit;
spl_spr_uart2_dsr_pd10_199_pad : inout bit;
ss_pc15_250_pad : inout bit;
ssi1_rxclk_pc4_261_pad : inout bit;
ssi1_rxdat_pc5_260_pad : inout bit;
ssi1_rxfs_pc3_262_pad : inout bit;
ssi1_txclk_pc8_257_pad : inout bit;
ssi1_txdat_pc6_259_pad : inout bit;
ssi1_txfs_pc7_258_pad : inout bit;
tin_pa1_171_pad : inout bit;
tout2_pd31_172_pad : inout bit;
uart1_cts_pc9_256_pad : inout bit;
uart1_rts_pc10_255_pad : inout bit;
uart1_rxd_pc12_253_pad : inout bit;
uart1_txd_pc11_254_pad : inout bit;
uart2_cts_pb28_270_pad : inout bit;
uart2_rts_pb29_269_pad : inout bit;
uart2_rxd_pb31_267_pad : inout bit;
uart2_txd_pb30_268_pad : inout bit;
usbd_afe_pb20_282_pad : inout bit;
usbd_rcv_pb22_280_pad : inout bit;
usbd_roe_pb21_281_pad : inout bit;
usbd_suspnd_pb23_275_pad : inout bit;
usbd_vm_treqb_pb25_273_pad : inout bit;
usbd_vmo_pb27_271_pad : inout bit;
usbd_vp_tack_pb24_274_pad : inout bit;
usbd_vpo_treqa_pb26_272_pad : inout bit;
vsync_pd14_195_pad : inout bit;
a10_40_pad : out bit;
a11_38_pad : out bit;
a12_36_pad : out bit;
a13_30_pad : out bit;
a14_28_pad : out bit;
a15_26_pad : out bit;
a1_72_pad : out bit;
a2_68_pad : out bit;
a3_62_pad : out bit;
a4_56_pad : out bit;
a5_54_pad : out bit;
a6_52_pad : out bit;
a7_48_pad : out bit;
a8_46_pad : out bit;
a9_44_pad : out bit;
cas_b_113_pad : out bit;
clko_120_pad : out bit;
cs0_b_88_pad : out bit;
cs1_b_87_pad : out bit;
cs2_b_csd0_81_pad : out bit;
cs3_b_csd1_79_pad : out bit;
eb0_b_60_pad : out bit;
eb1_b_63_pad : out bit;
eb2_b_65_pad : out bit;
eb3_b_69_pad : out bit;
ma10_104_pad : out bit;
ma11_103_pad : out bit;
oe_b_71_pad : out bit;
ras_b_112_pad : out bit;
reset_out_b_126_pad : out bit;
resetsf_b_119_pad : out bit;
rw_b_102_pad : out bit;
sdcke0_117_pad : out bit;
sdcke1_118_pad : out bit;
sdwe_b_116_pad : out bit;
tdo_b_150_pad : out bit;
BTRFGND_246_pad : linkage bit;
NVDD1_1_pad : linkage bit;
QVDD1_33_pad : linkage bit;
AVDD1_124_pad : linkage bit;
QVDD2_135_pad : linkage bit;
NVDD2_149_pad : linkage bit;
QVDD3_178_pad : linkage bit;
QVDD4_227_pad : linkage bit;
AVDD2_229_pad : linkage bit;
BTRFVDD_230_pad : linkage bit;
NVDD3_247_pad : linkage bit;
NVDD4_266_pad : linkage bit;
-- NVDD5_290_pad : linkage bit;
NVSS1_8_pad : linkage bit;
QVSS1_34_pad : linkage bit;
QVSS2_136_pad : linkage bit;
-- AVSS1_148_pad : linkage bit;
NVSS2_162_pad : linkage bit;
QVSS3_179_pad : linkage bit;
AVSS2_205_pad : linkage bit;
QVSS4_228_pad : linkage bit;
NVSS3_263_pad : linkage bit;
NVSS4_276_pad : linkage bit;
-- NVSS5_297_pad : linkage bit;
-- adc_iout_222_pad : linkage bit;
boot0_132_pad : in bit;
boot1_131_pad : in bit;
boot2_130_pad : in bit;
boot3_129_pad : in bit;
dac_om_226_pad : linkage bit;
dac_op_225_pad : linkage bit;
extal16m_137_pad : linkage bit;
extal32k_141_pad : linkage bit;
mim_219_pad : linkage bit;
mip_218_pad : linkage bit;
por_127_pad : in bit;
px1_208_pad : linkage bit;
px2_210_pad : linkage bit;
py1_209_pad : linkage bit;
py2_211_pad : linkage bit;
r1a_212_pad : linkage bit;
r1b_213_pad : linkage bit;
r2a_206_pad : linkage bit;
r2b_207_pad : linkage bit;
rm_215_pad : linkage bit;
rp_214_pad : linkage bit;
rvm1_224_pad : linkage bit;
rvm_220_pad : linkage bit;
rvp1_223_pad : linkage bit;
rvp_221_pad : linkage bit;
tristate_133_pad : in bit;
uin_216_pad : linkage bit;
uip_217_pad : linkage bit;
xtal16m_139_pad : linkage bit;
xtal32k_143_pad : linkage bit
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DBMX: entity is "STD_1149_1_1993";
attribute PIN_MAP of DBMX: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant BGA: PIN_MAP_STRING :=
"NVDD1_1_pad : H5," &
"a24_dbg1_pa0_2_pad : B1," &
"d31_3_pad : C2," &
"a23_dbg2_pa31_4_pad : C1," &
"d30_5_pad : D2," &
"a22_dbg3_pa30_6_pad : D1," &
"d29_7_pad : D3," &
"NVSS1_8_pad : A1," &
"a21_dbg4_pa29_10_pad : E2," &
"d28_11_pad : E3," &
"a20_dbg5_pa28_12_pad : E1," &
"d27_13_pad : F2," &
"a19_dbg6_pa27_14_pad : F4," &
"d26_15_pad : E4," &
"a18_dbg7_pa26_18_pad : F1," &
"d25_19_pad : F3," &
"a17_dbg8_pa25_20_pad : G2," &
"d24_21_pad : G3," &
"a16_dbg9_pa24_22_pad : F5," &
"d23_23_pad : G4," &
"a15_26_pad : G1," &
"d22_27_pad : H2," &
"a14_28_pad : H3," &
"d21_29_pad : G5," &
"a13_30_pad : H1," &
"d20_31_pad : H4," &
"QVDD1_33_pad : H9," &
"QVSS1_34_pad : H8," &
"a12_36_pad : J1," &
"d19_37_pad : J4," &
"a11_38_pad : J2," &
"d18_39_pad : J3," &
"a10_40_pad : K1," &
"d17_41_pad : K4," &
"a9_44_pad : K3," &
"d16_45_pad : K2," &
"a8_46_pad : L1," &
"d15_47_pad : L4," &
"a7_48_pad : L2," &
"d14_49_pad : L5," &
"a6_52_pad : M4," &
"d13_53_pad : L3," &
"a5_54_pad : M1," &
"d12_55_pad : M2," &
"a4_56_pad : N1," &
"d11_57_pad : M3," &
"eb0_b_60_pad : P3," &
"d10_61_pad : N3," &
"a3_62_pad : P1," &
"eb1_b_63_pad : N2," &
"d9_64_pad : P2," &
"eb2_b_65_pad : R1," &
"a2_68_pad : T2," &
"eb3_b_69_pad : R2," &
"d8_70_pad : R5," &
"oe_b_71_pad : T3," &
"a1_72_pad : R3," &
"cs5_b_pa23_73_pad : T4," &
"d7_76_pad : N4," &
"cs4_b_pa22_77_pad : R4," &
"a0_pa21_78_pad : N5," &
"cs3_b_csd1_79_pad : P4," &
"d6_80_pad : P5," &
"cs2_b_csd0_81_pad : T5," &
"sdclk_86_pad : M5," &
"cs1_b_87_pad : T6," &
"cs0_b_88_pad : T7," &
"d5_89_pad : R6," &
"ecb_b_pa20_92_pad : P6," &
"d4_93_pad : N6," &
"lba_b_pa19_94_pad : R7," &
"d3_95_pad : P8," &
"bclk_b_pa18_96_pad : R8," &
"d2_97_pad : P7," &
"pa17_100_pad : N7," &
"d1_101_pad : N8," &
"rw_b_102_pad : M7," &
"ma11_103_pad : T8," &
"ma10_104_pad : M8," &
"d0_105_pad : R9," &
"dqm3_108_pad : P9," &
"dqm2_109_pad : T9," &
"dqm1_110_pad : N9," &
"dqm0_111_pad : R10," &
"ras_b_112_pad : M9," &
"cas_b_113_pad : L8," &
"sdwe_b_116_pad : T10," &
"sdcke0_117_pad : R11," &
"sdcke1_118_pad : P10," &
"resetsf_b_119_pad : N10," &
"clko_120_pad : T11," &
"AVDD1_124_pad : T12," &
"reset_in_b_125_pad : M10," &
"reset_out_b_126_pad : N11," &
"por_127_pad : R12," &
"big_endian_128_pad : M11," &
"boot3_129_pad : P11," &
"boot2_130_pad : N12," &
"boot1_131_pad : R13," &
"boot0_132_pad : P12," &
"tristate_133_pad : T13," &
"trst_b_134_pad : P13," &
"QVDD2_135_pad : R15," &
"QVSS2_136_pad : T16," &
"extal16m_137_pad : T14," &
"xtal16m_139_pad : T15," &
"extal32k_141_pad : R16," &
"xtal32k_143_pad : P16," &
-- "pll_byp_b_146_pad : ," &
-- "prem_byp_b_147_pad : ," &
-- "AVSS1_148_pad : T16," &
"NVDD2_149_pad : K9," &
"tdo_b_150_pad : R14," &
"tms_151_pad : N15," &
"tck_152_pad : L9," &
"tdi_153_pad : N16," &
"i2c_clk_pa16_154_pad : P14," &
"i2c_data_pa15_155_pad : P15," &
"csi_pixclk_pa14_156_pad : N13," &
"csi_hsync_pa13_157_pad : M13," &
"csi_vsync_pa12_158_pad : M14," &
"csi_d7_pa11_159_pad : N14," &
"csi_d6_pa10_160_pad : M15," &
"csi_d5_pa9_161_pad : M16," &
"NVSS2_162_pad : J9," &
"csi_d4_pa8_164_pad : M12," &
"csi_d3_pa7_165_pad : L16," &
"csi_d2_pa6_166_pad : L15," &
"csi_d1_pa5_167_pad : L14," &
"csi_d0_pa4_168_pad : L13," &
"csi_mclk_pa3_169_pad : L12," &
"pwmo_pa2_170_pad : L11," &
"tin_pa1_171_pad : L10," &
"tout2_pd31_172_pad : K15," &
"ld15_pd30_173_pad : K16," &
"ld14_pd29_174_pad : K14," &
"ld13_pd28_175_pad : K13," &
"ld12_pd27_176_pad : K12," &
"QVDD3_178_pad : J15," &
"QVSS3_179_pad : J16," &
"ld11_pd26_181_pad : J14," &
"ld10_pd25_182_pad : K11," &
"ld9_pd24_183_pad : H15," &
"ld8_pd23_184_pad : J13," &
"ld7_pd22_185_pad : J12," &
"ld6_pd21_186_pad : J11," &
"ld5_pd20_187_pad : H14," &
"ld4_pd19_188_pad : H13," &
"ld3_pd18_189_pad : H16," &
"ld2_pd17_190_pad : H12," &
"ld1_pd16_193_pad : G16," &
"ld0_pd15_194_pad : H11," &
"vsync_pd14_195_pad : G15," &
"hsync_pd13_196_pad : G14," &
"oe_acd_pd12_197_pad : G13," &
"contrast_pd11_198_pad : G12," &
"spl_spr_uart2_dsr_pd10_199_pad : F16," &
"ps_uart2_ri_pd9_200_pad : H10," &
"cls_uart2_dco_pd8_201_pad : G11," &
"rev_uart2_dtr_pd7_202_pad : F12," &
"lsclk_pd6_203_pad : F15," &
"AVSS2_205_pad : C15," &
"r2a_206_pad : E16," &
"r2b_207_pad : D16," &
"px1_208_pad : F14," &
"py1_209_pad : F13," &
"px2_210_pad : E15," &
"py2_211_pad : E14," &
"r1a_212_pad : D15," &
"r1b_213_pad : C16," &
"rp_214_pad : B16," &
"rm_215_pad : A16," &
"uin_216_pad : B15," &
"uip_217_pad : A15," &
"mip_218_pad : E13," &
"mim_219_pad : D14," &
"rvm_220_pad : B14," &
"rvp_221_pad : A14," &
-- "adc_iout_222_pad : ," &
"rvp1_223_pad : D13," &
"rvm1_224_pad : C13," &
"dac_op_225_pad : E12," &
"dac_om_226_pad : D12," &
"QVDD4_227_pad : A13," &
"QVSS4_228_pad : B13," &
"AVDD2_229_pad : C14," &
"BTRFVDD_230_pad : C12," &
"bt1_pc31_233_pad : B12," &
"bt2_pc30_234_pad : F11," &
"bt3_pc29_235_pad : A12," &
"bt4_pc28_236_pad : E11," &
"bt5_pc27_237_pad : A11," &
"bt6_pc26_238_pad : D11," &
"bt7_pc25_239_pad : B11," &
"bt8_ssi2_rxfs_pc24_240_pad : C11," &
"bt9_ssi2_rxdat_pc23_241_pad : G10," &
"bt10_ssi2_txdat_pc22_242_pad : F10," &
"bt11_ssi2_txclk_pc21_243_pad : B10," &
"bt12_ssi2_txfs_pc20_244_pad : E10," &
"bt13_ssi2_rxclk_pc19_245_pad : D10," &
"BTRFGND_246_pad : C10," &
"NVDD3_247_pad : A10," &
"mosi_pc17_248_pad : G9," &
"miso_pc16_249_pad : F9," &
"ss_pc15_250_pad : E9," &
"sclk_pc14_251_pad : B9," &
"spi_rdy_pc13_252_pad : D9," &
"uart1_rxd_pc12_253_pad : A9," &
"uart1_txd_pc11_254_pad : C9," &
"uart1_rts_pc10_255_pad : A8," &
"uart1_cts_pc9_256_pad : G8," &
"ssi1_txclk_pc8_257_pad : B8," &
"ssi1_txfs_pc7_258_pad : F8," &
"ssi1_txdat_pc6_259_pad : E8," &
"ssi1_rxdat_pc5_260_pad : D8," &
"ssi1_rxclk_pc4_261_pad : B7," &
"ssi1_rxfs_pc3_262_pad : C8," &
"NVSS3_263_pad : A7," &
"NVDD4_266_pad : A6," &
"uart2_rxd_pb31_267_pad : C7," &
"uart2_txd_pb30_268_pad : F7," &
"uart2_rts_pb29_269_pad : E7," &
"uart2_cts_pb28_270_pad : C6," &
"usbd_vmo_pb27_271_pad : D7," &
"usbd_vpo_treqa_pb26_272_pad : D6," &
"usbd_vm_treqb_pb25_273_pad : E6," &
"usbd_vp_tack_pb24_274_pad : B6," &
"usbd_suspnd_pb23_275_pad : D5," &
"NVSS4_276_pad : A4," &
"usbd_rcv_pb22_280_pad : C5," &
"usbd_roe_pb21_281_pad : B5," &
"usbd_afe_pb20_282_pad : A5," &
"sim_clk_ssi1_txclk_pb19_283_pad : G7," &
"sim_rst_ssi1_txfs_pb18_284_pad : F6," &
"sim_rx_ssi1_txdat_pb17_285_pad : G6," &
"sim_tx_ssi1_rxdat_pb16_286_pad : B4," &
"sim_pd_ssi1_rxclk_pb15_287_pad : C4," &
"sim_sven_ssi1_rxfs_pb14_288_pad : D4," &
-- "NVDD5_290_pad : A6," &
"cmd_ms1_pb13_291_pad : B3," &
"clk_ms2_pb12_292_pad : A3," &
"dat3_ms3_pb11_293_pad : A2," &
"dat2_pb10_294_pad : E5," &
"dat1_pb9_295_pad : B2," &
"dat0_pb8_296_pad : C3";
-- "NVSS5_297_pad : A4";
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of tck_152_pad : signal is (2.000000e+07, BOTH);
attribute TAP_SCAN_IN of tdi_153_pad : signal is true;
attribute TAP_SCAN_MODE of tms_151_pad : signal is true;
attribute TAP_SCAN_OUT of tdo_b_150_pad : signal is true;
attribute TAP_SCAN_RESET of trst_b_134_pad: signal is true;
-- Specifies the compliance enable pins
attribute COMPLIANCE_PATTERNS of DBMX: entity is
"(boot0_132_pad, boot1_131_pad, boot2_130_pad, boot3_129_pad, por_127_pad, tristate_133_pad) (111101)";
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of DBMX: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of DBMX: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (010)," &
"CLAMP (011)," &
"HIGHZ (100)," &
"IDCODE (001)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of DBMX: entity is "001";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of DBMX: entity is
"0001" & -- 4-bit version number
"0000100100100000" & -- 16-bit part number
"00000001110" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of DBMX: entity is
"BYPASS (BYPASS, CLAMP, HIGHZ)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of DBMX: entity is 368;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of DBMX: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"367 (BC_4, big_endian_128_pad, observe_only, " &
"X), " &
-- "366 (BC_4, pll_byp_b_146_pad, observe_only, " &
"366 (BC_4, *, internal, " &
"X), " &
-- "365 (BC_4, prem_byp_b_147_pad, observe_only, " &
"365 (BC_4, *, internal, " &
"X), " &
"364 (BC_4, reset_in_b_125_pad, observe_only, " &
"X), " &
"363 (BC_2, *, control, " &
"0), " &
"362 (BC_1, a10_40_pad, output3, X, " &
"363, 0, Z)," &
"361 (BC_2, *, control, " &
"0), " &
"360 (BC_1, a11_38_pad, output3, X, " &
"361, 0, Z)," &
"359 (BC_2, *, control, " &
"0), " &
"358 (BC_1, a12_36_pad, output3, X, " &
"359, 0, Z)," &
"357 (BC_2, *, control, " &
"0), " &
"356 (BC_1, a13_30_pad, output3, X, " &
"357, 0, Z)," &
"355 (BC_2, *, control, " &
"0), " &
"354 (BC_1, a14_28_pad, output3, X, " &
"355, 0, Z)," &
"353 (BC_2, *, control, " &
"0), " &
"352 (BC_1, a15_26_pad, output3, X, " &
"353, 0, Z)," &
"351 (BC_2, *, control, " &
"0), " &
"350 (BC_1, a1_72_pad, output3, X, " &
"351, 0, Z)," &
"349 (BC_2, *, control, " &
"0), " &
"348 (BC_1, a2_68_pad, output3, X, " &
"349, 0, Z)," &
"347 (BC_2, *, control, " &
"0), " &
"346 (BC_1, a3_62_pad, output3, X, " &
"347, 0, Z)," &
"345 (BC_2, *, control, " &
"0), " &
"344 (BC_1, a4_56_pad, output3, X, " &
"345, 0, Z)," &
"343 (BC_2, *, control, " &
"0), " &
"342 (BC_1, a5_54_pad, output3, X, " &
"343, 0, Z)," &
"341 (BC_2, *, control, " &
"0), " &
"340 (BC_1, a6_52_pad, output3, X, " &
"341, 0, Z)," &
"339 (BC_2, *, control, " &
"0), " &
"338 (BC_1, a7_48_pad, output3, X, " &
"339, 0, Z)," &
"337 (BC_2, *, control, " &
"0), " &
"336 (BC_1, a8_46_pad, output3, X, " &
"337, 0, Z)," &
"335 (BC_2, *, control, " &
"0), " &
"334 (BC_1, a9_44_pad, output3, X, " &
"335, 0, Z)," &
"333 (BC_2, *, control, " &
"0), " &
"332 (BC_1, cas_b_113_pad, output3, X, " &
"333, 0, Z)," &
"331 (BC_2, *, control, " &
"0), " &
"330 (BC_1, clko_120_pad, output3, X, " &
"331, 0, Z)," &
"329 (BC_2, *, control, " &
"0), " &
"328 (BC_1, cs0_b_88_pad, output3, X, " &
"329, 0, Z)," &
"327 (BC_2, *, control, " &
"0), " &
"326 (BC_1, cs1_b_87_pad, output3, X, " &
"327, 0, Z)," &
"325 (BC_2, *, control, " &
"0), " &
"324 (BC_1, cs2_b_csd0_81_pad, output3, X, " &
"325, 0, Z)," &
"323 (BC_2, *, control, " &
"0), " &
"322 (BC_1, cs3_b_csd1_79_pad, output3, X, " &
"323, 0, Z)," &
"321 (BC_2, *, control, " &
"0), " &
"320 (BC_1, eb0_b_60_pad, output3, X, " &
"321, 0, Z)," &
"319 (BC_2, *, control, " &
"0), " &
"318 (BC_1, eb1_b_63_pad, output3, X, " &
"319, 0, Z)," &
"317 (BC_2, *, control, " &
"0), " &
"316 (BC_1, eb2_b_65_pad, output3, X, " &
"317, 0, Z)," &
"315 (BC_2, *, control, " &
"0), " &
"314 (BC_1, eb3_b_69_pad, output3, X, " &
"315, 0, Z)," &
"313 (BC_2, *, control, " &
"0), " &
"312 (BC_1, ma10_104_pad, output3, X, " &
"313, 0, Z)," &
"311 (BC_2, *, control, " &
"0), " &
"310 (BC_1, ma11_103_pad, output3, X, " &
"311, 0, Z)," &
"309 (BC_2, *, control, " &
"0), " &
"308 (BC_1, oe_b_71_pad, output3, X, " &
"309, 0, Z)," &
"307 (BC_2, *, control, " &
"0), " &
"306 (BC_1, ras_b_112_pad, output3, X, " &
"307, 0, Z)," &
"305 (BC_2, *, control, " &
"0), " &
"304 (BC_1, reset_out_b_126_pad, output3, X, " &
"305, 0, Z)," &
"303 (BC_2, *, control, " &
"0), " &
"302 (BC_1, resetsf_b_119_pad, output3, X, " &
"303, 0, Z)," &
"301 (BC_2, *, control, " &
"0), " &
"300 (BC_1, rw_b_102_pad, output3, X, " &
"301, 0, Z)," &
"299 (BC_2, *, control, " &
"0), " &
"298 (BC_1, sdcke0_117_pad, output3, X, " &
"299, 0, Z)," &
"297 (BC_2, *, control, " &
"0), " &
"296 (BC_1, sdcke1_118_pad, output3, X, " &
"297, 0, Z)," &
"295 (BC_2, *, control, " &
"0), " &
"294 (BC_1, sdwe_b_116_pad, output3, X, " &
"295, 0, Z)," &
"293 (BC_2, *, control, " &
"0), " &
"292 (BC_7, a0_pa21_78_pad, bidir, X, " &
"293, 0, Z)," &
"291 (BC_2, *, control, " &
"0), " &
"290 (BC_7, a16_dbg9_pa24_22_pad, bidir, X, " &
"291, 0, Z)," &
"289 (BC_2, *, control, " &
"0), " &
"288 (BC_7, a17_dbg8_pa25_20_pad, bidir, X, " &
"289, 0, Z)," &
"287 (BC_2, *, control, " &
"0), " &
"286 (BC_7, a18_dbg7_pa26_18_pad, bidir, X, " &
"287, 0, Z)," &
"285 (BC_2, *, control, " &
"0), " &
"284 (BC_7, a19_dbg6_pa27_14_pad, bidir, X, " &
"285, 0, Z)," &
"283 (BC_2, *, control, " &
"0), " &
"282 (BC_7, a20_dbg5_pa28_12_pad, bidir, X, " &
"283, 0, Z)," &
"281 (BC_2, *, control, " &
"0), " &
"280 (BC_7, a21_dbg4_pa29_10_pad, bidir, X, " &
"281, 0, Z)," &
"279 (BC_2, *, control, " &
"0), " &
"278 (BC_7, a22_dbg3_pa30_6_pad, bidir, X, " &
"279, 0, Z)," &
"277 (BC_2, *, control, " &
"0), " &
"276 (BC_7, a23_dbg2_pa31_4_pad, bidir, X, " &
"277, 0, Z)," &
"275 (BC_2, *, control, " &
"0), " &
"274 (BC_7, a24_dbg1_pa0_2_pad, bidir, X, " &
"275, 0, Z)," &
"273 (BC_2, *, control, " &
"0), " &
"272 (BC_7, bclk_b_pa18_96_pad, bidir, X, " &
"273, 0, Z)," &
"271 (BC_2, *, control, " &
"0), " &
"270 (BC_7, bt10_ssi2_txdat_pc22_242_pad, bidir, X, " &
"271, 0, Z)," &
"269 (BC_2, *, control, " &
"0), " &
"268 (BC_7, bt11_ssi2_txclk_pc21_243_pad, bidir, X, " &
"269, 0, Z)," &
"267 (BC_2, *, control, " &
"0), " &
"266 (BC_7, bt12_ssi2_txfs_pc20_244_pad, bidir, X, " &
"267, 0, Z)," &
"265 (BC_2, *, control, " &
"0), " &
"264 (BC_7, bt13_ssi2_rxclk_pc19_245_pad, bidir, X, " &
"265, 0, Z)," &
"263 (BC_2, *, control, " &
"0), " &
"262 (BC_7, bt1_pc31_233_pad, bidir, X, " &
"263, 0, Z)," &
"261 (BC_2, *, control, " &
"0), " &
"260 (BC_7, bt2_pc30_234_pad, bidir, X, " &
"261, 0, Z)," &
"259 (BC_2, *, control, " &
"0), " &
"258 (BC_7, bt3_pc29_235_pad, bidir, X, " &
"259, 0, Z)," &
"257 (BC_2, *, control, " &
"0), " &
"256 (BC_7, bt4_pc28_236_pad, bidir, X, " &
"257, 0, Z)," &
"255 (BC_2, *, control, " &
"0), " &
"254 (BC_7, bt5_pc27_237_pad, bidir, X, " &
"255, 0, Z)," &
"253 (BC_2, *, control, " &
"0), " &
"252 (BC_7, bt6_pc26_238_pad, bidir, X, " &
"253, 0, Z)," &
"251 (BC_2, *, control, " &
"0), " &
"250 (BC_7, bt7_pc25_239_pad, bidir, X, " &
"251, 0, Z)," &
"249 (BC_2, *, control, " &
"0), " &
"248 (BC_7, bt8_ssi2_rxfs_pc24_240_pad, bidir, X, " &
"249, 0, Z)," &
"247 (BC_2, *, control, " &
"0), " &
"246 (BC_7, bt9_ssi2_rxdat_pc23_241_pad, bidir, X, " &
"247, 0, Z)," &
"245 (BC_2, *, control, " &
"0), " &
"244 (BC_7, clk_ms2_pb12_292_pad, bidir, X, " &
"245, 0, Z)," &
"243 (BC_2, *, control, " &
"0), " &
"242 (BC_7, cls_uart2_dco_pd8_201_pad, bidir, X, " &
"243, 0, Z)," &
"241 (BC_2, *, control, " &
"0), " &
"240 (BC_7, cmd_ms1_pb13_291_pad, bidir, X, " &
"241, 0, Z)," &
"239 (BC_2, *, control, " &
"0), " &
"238 (BC_7, contrast_pd11_198_pad, bidir, X, " &
"239, 0, Z)," &
"237 (BC_2, *, control, " &
"0), " &
"236 (BC_7, cs4_b_pa22_77_pad, bidir, X, " &
"237, 0, Z)," &
"235 (BC_2, *, control, " &
"0), " &
"234 (BC_7, cs5_b_pa23_73_pad, bidir, X, " &
"235, 0, Z)," &
"233 (BC_2, *, control, " &
"0), " &
"232 (BC_7, csi_d0_pa4_168_pad, bidir, X, " &
"233, 0, Z)," &
"231 (BC_2, *, control, " &
"0), " &
"230 (BC_7, csi_d1_pa5_167_pad, bidir, X, " &
"231, 0, Z)," &
"229 (BC_2, *, control, " &
"0), " &
"228 (BC_7, csi_d2_pa6_166_pad, bidir, X, " &
"229, 0, Z)," &
"227 (BC_2, *, control, " &
"0), " &
"226 (BC_7, csi_d3_pa7_165_pad, bidir, X, " &
"227, 0, Z)," &
"225 (BC_2, *, control, " &
"0), " &
"224 (BC_7, csi_d4_pa8_164_pad, bidir, X, " &
"225, 0, Z)," &
"223 (BC_2, *, control, " &
"0), " &
"222 (BC_7, csi_d5_pa9_161_pad, bidir, X, " &
"223, 0, Z)," &
"221 (BC_2, *, control, " &
"0), " &
"220 (BC_7, csi_d6_pa10_160_pad, bidir, X, " &
"221, 0, Z)," &
"219 (BC_2, *, control, " &
"0), " &
"218 (BC_7, csi_d7_pa11_159_pad, bidir, X, " &
"219, 0, Z)," &
"217 (BC_2, *, control, " &
"0), " &
"216 (BC_7, csi_hsync_pa13_157_pad, bidir, X, " &
"217, 0, Z)," &
"215 (BC_2, *, control, " &
"0), " &
"214 (BC_7, csi_mclk_pa3_169_pad, bidir, X, " &
"215, 0, Z)," &
"213 (BC_2, *, control, " &
"0), " &
"212 (BC_7, csi_pixclk_pa14_156_pad, bidir, X, " &
"213, 0, Z)," &
"211 (BC_2, *, control, " &
"0), " &
"210 (BC_7, csi_vsync_pa12_158_pad, bidir, X, " &
"211, 0, Z)," &
"209 (BC_2, *, control, " &
"0), " &
"208 (BC_7, d0_105_pad, bidir, X, " &
"209, 0, Z)," &
"207 (BC_2, *, control, " &
"0), " &
"206 (BC_7, d10_61_pad, bidir, X, " &
"207, 0, Z)," &
"205 (BC_2, *, control, " &
"0), " &
"204 (BC_7, d11_57_pad, bidir, X, " &
"205, 0, Z)," &
"203 (BC_2, *, control, " &
"0), " &
"202 (BC_7, d12_55_pad, bidir, X, " &
"203, 0, Z)," &
"201 (BC_2, *, control, " &
"0), " &
"200 (BC_7, d13_53_pad, bidir, X, " &
"201, 0, Z)," &
"199 (BC_2, *, control, " &
"0), " &
"198 (BC_7, d14_49_pad, bidir, X, " &
"199, 0, Z)," &
"197 (BC_2, *, control, " &
"0), " &
"196 (BC_7, d15_47_pad, bidir, X, " &
"197, 0, Z)," &
"195 (BC_2, *, control, " &
"0), " &
"194 (BC_7, d16_45_pad, bidir, X, " &
"195, 0, Z)," &
"193 (BC_2, *, control, " &
"0), " &
"192 (BC_7, d17_41_pad, bidir, X, " &
"193, 0, Z)," &
"191 (BC_2, *, control, " &
"0), " &
"190 (BC_7, d18_39_pad, bidir, X, " &
"191, 0, Z)," &
"189 (BC_2, *, control, " &
"0), " &
"188 (BC_7, d19_37_pad, bidir, X, " &
"189, 0, Z)," &
"187 (BC_2, *, control, " &
"0), " &
"186 (BC_7, d1_101_pad, bidir, X, " &
"187, 0, Z)," &
"185 (BC_2, *, control, " &
"0), " &
"184 (BC_7, d20_31_pad, bidir, X, " &
"185, 0, Z)," &
"183 (BC_2, *, control, " &
"0), " &
"182 (BC_7, d21_29_pad, bidir, X, " &
"183, 0, Z)," &
"181 (BC_2, *, control, " &
"0), " &
"180 (BC_7, d22_27_pad, bidir, X, " &
"181, 0, Z)," &
"179 (BC_2, *, control, " &
"0), " &
"178 (BC_7, d23_23_pad, bidir, X, " &
"179, 0, Z)," &
"177 (BC_2, *, control, " &
"0), " &
"176 (BC_7, d24_21_pad, bidir, X, " &
"177, 0, Z)," &
"175 (BC_2, *, control, " &
"0), " &
"174 (BC_7, d25_19_pad, bidir, X, " &
"175, 0, Z)," &
"173 (BC_2, *, control, " &
"0), " &
"172 (BC_7, d26_15_pad, bidir, X, " &
"173, 0, Z)," &
"171 (BC_2, *, control, " &
"0), " &
"170 (BC_7, d27_13_pad, bidir, X, " &
"171, 0, Z)," &
"169 (BC_2, *, control, " &
"0), " &
"168 (BC_7, d28_11_pad, bidir, X, " &
"169, 0, Z)," &
"167 (BC_2, *, control, " &
"0), " &
"166 (BC_7, d29_7_pad, bidir, X, " &
"167, 0, Z)," &
"165 (BC_2, *, control, " &
"0), " &
"164 (BC_7, d2_97_pad, bidir, X, " &
"165, 0, Z)," &
"163 (BC_2, *, control, " &
"0), " &
"162 (BC_7, d30_5_pad, bidir, X, " &
"163, 0, Z)," &
"161 (BC_2, *, control, " &
"0), " &
"160 (BC_7, d31_3_pad, bidir, X, " &
"161, 0, Z)," &
"159 (BC_2, *, control, " &
"0), " &
"158 (BC_7, d3_95_pad, bidir, X, " &
"159, 0, Z)," &
"157 (BC_2, *, control, " &
"0), " &
"156 (BC_7, d4_93_pad, bidir, X, " &
"157, 0, Z)," &
"155 (BC_2, *, control, " &
"0), " &
"154 (BC_7, d5_89_pad, bidir, X, " &
"155, 0, Z)," &
"153 (BC_2, *, control, " &
"0), " &
"152 (BC_7, d6_80_pad, bidir, X, " &
"153, 0, Z)," &
"151 (BC_2, *, control, " &
"0), " &
"150 (BC_7, d7_76_pad, bidir, X, " &
"151, 0, Z)," &
"149 (BC_2, *, control, " &
"0), " &
"148 (BC_7, d8_70_pad, bidir, X, " &
"149, 0, Z)," &
"147 (BC_2, *, control, " &
"0), " &
"146 (BC_7, d9_64_pad, bidir, X, " &
"147, 0, Z)," &
"145 (BC_2, *, control, " &
"0), " &
"144 (BC_7, dat0_pb8_296_pad, bidir, X, " &
"145, 0, Z)," &
"143 (BC_2, *, control, " &
"0), " &
"142 (BC_7, dat1_pb9_295_pad, bidir, X, " &
"143, 0, Z)," &
"141 (BC_2, *, control, " &
"0), " &
"140 (BC_7, dat2_pb10_294_pad, bidir, X, " &
"141, 0, Z)," &
"139 (BC_2, *, control, " &
"0), " &
"138 (BC_7, dat3_ms3_pb11_293_pad, bidir, X, " &
"139, 0, Z)," &
"137 (BC_2, *, control, " &
"0), " &
"136 (BC_7, dqm0_111_pad, bidir, X, " &
"137, 0, Z)," &
"135 (BC_2, *, control, " &
"0), " &
"134 (BC_7, dqm1_110_pad, bidir, X, " &
"135, 0, Z)," &
"133 (BC_2, *, control, " &
"0), " &
"132 (BC_7, dqm2_109_pad, bidir, X, " &
"133, 0, Z)," &
"131 (BC_2, *, control, " &
"0), " &
"130 (BC_7, dqm3_108_pad, bidir, X, " &
"131, 0, Z)," &
"129 (BC_2, *, control, " &
"0), " &
"128 (BC_7, ecb_b_pa20_92_pad, bidir, X, " &
"129, 0, Z)," &
"127 (BC_2, *, control, " &
"0), " &
"126 (BC_7, hsync_pd13_196_pad, bidir, X, " &
"127, 0, Z)," &
"125 (BC_2, *, control, " &
"0), " &
"124 (BC_7, i2c_clk_pa16_154_pad, bidir, X, " &
"125, 0, Z)," &
"123 (BC_2, *, control, " &
"0), " &
"122 (BC_7, i2c_data_pa15_155_pad, bidir, X, " &
"123, 0, Z)," &
"121 (BC_2, *, control, " &
"0), " &
"120 (BC_7, lba_b_pa19_94_pad, bidir, X, " &
"121, 0, Z)," &
"119 (BC_2, *, control, " &
"0), " &
"118 (BC_7, ld0_pd15_194_pad, bidir, X, " &
"119, 0, Z)," &
"117 (BC_2, *, control, " &
"0), " &
"116 (BC_7, ld10_pd25_182_pad, bidir, X, " &
"117, 0, Z)," &
"115 (BC_2, *, control, " &
"0), " &
"114 (BC_7, ld11_pd26_181_pad, bidir, X, " &
"115, 0, Z)," &
"113 (BC_2, *, control, " &
"0), " &
"112 (BC_7, ld12_pd27_176_pad, bidir, X, " &
"113, 0, Z)," &
"111 (BC_2, *, control, " &
"0), " &
"110 (BC_7, ld13_pd28_175_pad, bidir, X, " &
"111, 0, Z)," &
"109 (BC_2, *, control, " &
"0), " &
"108 (BC_7, ld14_pd29_174_pad, bidir, X, " &
"109, 0, Z)," &
"107 (BC_2, *, control, " &
"0), " &
"106 (BC_7, ld15_pd30_173_pad, bidir, X, " &
"107, 0, Z)," &
"105 (BC_2, *, control, " &
"0), " &
"104 (BC_7, ld1_pd16_193_pad, bidir, X, " &
"105, 0, Z)," &
"103 (BC_2, *, control, " &
"0), " &
"102 (BC_7, ld2_pd17_190_pad, bidir, X, " &
"103, 0, Z)," &
"101 (BC_2, *, control, " &
"0), " &
"100 (BC_7, ld3_pd18_189_pad, bidir, X, " &
"101, 0, Z)," &
"99 (BC_2, *, control, " &
"0), " &
"98 (BC_7, ld4_pd19_188_pad, bidir, X, " &
"99, 0, Z)," &
"97 (BC_2, *, control, " &
"0), " &
"96 (BC_7, ld5_pd20_187_pad, bidir, X, " &
"97, 0, Z)," &
"95 (BC_2, *, control, " &
"0), " &
"94 (BC_7, ld6_pd21_186_pad, bidir, X, " &
"95, 0, Z)," &
"93 (BC_2, *, control, " &
"0), " &
"92 (BC_7, ld7_pd22_185_pad, bidir, X, " &
"93, 0, Z)," &
"91 (BC_2, *, control, " &
"0), " &
"90 (BC_7, ld8_pd23_184_pad, bidir, X, " &
"91, 0, Z)," &
"89 (BC_2, *, control, " &
"0), " &
"88 (BC_7, ld9_pd24_183_pad, bidir, X, " &
"89, 0, Z)," &
"87 (BC_2, *, control, " &
"0), " &
"86 (BC_7, lsclk_pd6_203_pad, bidir, X, " &
"87, 0, Z)," &
"85 (BC_2, *, control, " &
"0), " &
"84 (BC_7, miso_pc16_249_pad, bidir, X, " &
"85, 0, Z)," &
"83 (BC_2, *, control, " &
"0), " &
"82 (BC_7, mosi_pc17_248_pad, bidir, X, " &
"83, 0, Z)," &
"81 (BC_2, *, control, " &
"0), " &
"80 (BC_7, oe_acd_pd12_197_pad, bidir, X, " &
"81, 0, Z)," &
"79 (BC_2, *, control, " &
"0), " &
"78 (BC_7, pa17_100_pad, bidir, X, " &
"79, 0, Z)," &
"77 (BC_2, *, control, " &
"0), " &
"76 (BC_7, ps_uart2_ri_pd9_200_pad, bidir, X, " &
"77, 0, Z)," &
"75 (BC_2, *, control, " &
"0), " &
"74 (BC_7, pwmo_pa2_170_pad, bidir, X, " &
"75, 0, Z)," &
"73 (BC_2, *, control, " &
"0), " &
"72 (BC_7, rev_uart2_dtr_pd7_202_pad, bidir, X, " &
"73, 0, Z)," &
"71 (BC_2, *, control, " &
"0), " &
"70 (BC_7, sclk_pc14_251_pad, bidir, X, " &
"71, 0, Z)," &
"69 (BC_2, *, control, " &
"0), " &
"68 (BC_7, sdclk_86_pad, bidir, X, " &
"69, 0, Z)," &
"67 (BC_2, *, control, " &
"0), " &
"66 (BC_7, sim_clk_ssi1_txclk_pb19_283_pad, bidir, X, " &
"67, 0, Z)," &
"65 (BC_2, *, control, " &
"0), " &
"64 (BC_7, sim_pd_ssi1_rxclk_pb15_287_pad, bidir, X, " &
"65, 0, Z)," &
"63 (BC_2, *, control, " &
"0), " &
"62 (BC_7, sim_rst_ssi1_txfs_pb18_284_pad, bidir, X, " &
"63, 0, Z)," &
"61 (BC_2, *, control, " &
"0), " &
"60 (BC_7, sim_rx_ssi1_txdat_pb17_285_pad, bidir, X, " &
"61, 0, Z)," &
"59 (BC_2, *, control, " &
"0), " &
"58 (BC_7, sim_sven_ssi1_rxfs_pb14_288_pad, bidir, X, " &
"59, 0, Z)," &
"57 (BC_2, *, control, " &
"0), " &
"56 (BC_7, sim_tx_ssi1_rxdat_pb16_286_pad, bidir, X, " &
"57, 0, Z)," &
"55 (BC_2, *, control, " &
"0), " &
"54 (BC_7, spi_rdy_pc13_252_pad, bidir, X, " &
"55, 0, Z)," &
"53 (BC_2, *, control, " &
"0), " &
"52 (BC_7, spl_spr_uart2_dsr_pd10_199_pad, bidir, X, " &
"53, 0, Z)," &
"51 (BC_2, *, control, " &
"0), " &
"50 (BC_7, ss_pc15_250_pad, bidir, X, " &
"51, 0, Z)," &
"49 (BC_2, *, control, " &
"0), " &
"48 (BC_7, ssi1_rxclk_pc4_261_pad, bidir, X, " &
"49, 0, Z)," &
"47 (BC_2, *, control, " &
"0), " &
"46 (BC_7, ssi1_rxdat_pc5_260_pad, bidir, X, " &
"47, 0, Z)," &
"45 (BC_2, *, control, " &
"0), " &
"44 (BC_7, ssi1_rxfs_pc3_262_pad, bidir, X, " &
"45, 0, Z)," &
"43 (BC_2, *, control, " &
"0), " &
"42 (BC_7, ssi1_txclk_pc8_257_pad, bidir, X, " &
"43, 0, Z)," &
"41 (BC_2, *, control, " &
"0), " &
"40 (BC_7, ssi1_txdat_pc6_259_pad, bidir, X, " &
"41, 0, Z)," &
"39 (BC_2, *, control, " &
"0), " &
"38 (BC_7, ssi1_txfs_pc7_258_pad, bidir, X, " &
"39, 0, Z)," &
"37 (BC_2, *, control, " &
"0), " &
"36 (BC_7, tin_pa1_171_pad, bidir, X, " &
"37, 0, Z)," &
"35 (BC_2, *, control, " &
"0), " &
"34 (BC_7, tout2_pd31_172_pad, bidir, X, " &
"35, 0, Z)," &
"33 (BC_2, *, control, " &
"0), " &
"32 (BC_7, uart1_cts_pc9_256_pad, bidir, X, " &
"33, 0, Z)," &
"31 (BC_2, *, control, " &
"0), " &
"30 (BC_7, uart1_rts_pc10_255_pad, bidir, X, " &
"31, 0, Z)," &
"29 (BC_2, *, control, " &
"0), " &
"28 (BC_7, uart1_rxd_pc12_253_pad, bidir, X, " &
"29, 0, Z)," &
"27 (BC_2, *, control, " &
"0), " &
"26 (BC_7, uart1_txd_pc11_254_pad, bidir, X, " &
"27, 0, Z)," &
"25 (BC_2, *, control, " &
"0), " &
"24 (BC_7, uart2_cts_pb28_270_pad, bidir, X, " &
"25, 0, Z)," &
"23 (BC_2, *, control, " &
"0), " &
"22 (BC_7, uart2_rts_pb29_269_pad, bidir, X, " &
"23, 0, Z)," &
"21 (BC_2, *, control, " &
"0), " &
"20 (BC_7, uart2_rxd_pb31_267_pad, bidir, X, " &
"21, 0, Z)," &
"19 (BC_2, *, control, " &
"0), " &
"18 (BC_7, uart2_txd_pb30_268_pad, bidir, X, " &
"19, 0, Z)," &
"17 (BC_2, *, control, " &
"0), " &
"16 (BC_7, usbd_afe_pb20_282_pad, bidir, X, " &
"17, 0, Z)," &
"15 (BC_2, *, control, " &
"0), " &
"14 (BC_7, usbd_rcv_pb22_280_pad, bidir, X, " &
"15, 0, Z)," &
"13 (BC_2, *, control, " &
"0), " &
"12 (BC_7, usbd_roe_pb21_281_pad, bidir, X, " &
"13, 0, Z)," &
"11 (BC_2, *, control, " &
"0), " &
"10 (BC_7, usbd_suspnd_pb23_275_pad, bidir, X, " &
"11, 0, Z)," &
"9 (BC_2, *, control, " &
"0), " &
"8 (BC_7, usbd_vm_treqb_pb25_273_pad, bidir, X, " &
"9, 0, Z)," &
"7 (BC_2, *, control, " &
"0), " &
"6 (BC_7, usbd_vmo_pb27_271_pad, bidir, X, " &
"7, 0, Z)," &
"5 (BC_2, *, control, " &
"0), " &
"4 (BC_7, usbd_vp_tack_pb24_274_pad, bidir, X, " &
"5, 0, Z)," &
"3 (BC_2, *, control, " &
"0), " &
"2 (BC_7, usbd_vpo_treqa_pb26_272_pad, bidir, X, " &
"3, 0, Z)," &
"1 (BC_2, *, control, " &
"0), " &
"0 (BC_7, vsync_pd14_195_pad, bidir, X, " &
"1, 0, Z)";
end DBMX;
