BSDL Files Library for JTAG

The only free public library that contains thousands of BSDL (Boundary Scan Description Language) models to use with BScan/JTAG tools

BSDL model: XCS05_VQ100

--$ XILINX$RCSfile: xcs05_VQ100.bsd,v $
--$ XILINX$Revision: 1.4 $
--
-- BSDL file for device XCS05, package VQ100
-- Xilinx, Inc. $State: FINAL $ $Date: 2002-01-29 14:27:08-08 $
-- Generated by createBSDL 2.9
--
-- For technical support, contact Xilinx as follows: 
-- North America 1-800-255-7778 hotline@xilinx.com 
-- United Kingdom +44 870 7350 610 eurosupport@xilinx.com
-- France  (33) 1 3463 0100 eurosupport@xilinx.com
-- Germany  (49) 89 991 54930 eurosupport@xilinx.com
-- Japan  (81) 3-3297-9163 jhotline@xilinx.com
--
-- BSDL verified to conform to 1149.1b-1994 syntax. This device has been 
-- tested by the Intellitech 1149.1 Verification Lab using the Intellitech
-- Eclipse(TM) Scan Diagnostic Tool and the Intellitech RCT(TM). This
-- device has been verified to operate according to the BSDL provided,
-- and is compatible with the IEEE 1149.1 standard when the operating 
-- instructions in the BSDL are followed. 
-- PH: 603-868-7116 or email: scansupport@intellitech.com
--

-- This BSDL file reflects the pre-configuration JTAG behavior. To reflect
-- the post-configuration JTAG behavior (if any), edit this file as described
-- below. Many of these changes are demonstrated by commented-out template
-- lines preceeding the lines they would replace:
-- 	
-- 1. Enable USER instructions as appropriate (see below).
-- 2. For inputs using uncontrolled paths (e.g. PGCK, SGCK), change
-- 	boundary cell function from 'input' to 'clock' or 'observe_only'.
-- 3. Set disable result of all pads as configured.
-- 4. Set safe state of boundary cells as necessary.
-- 5. Set safe state of INIT output to X, or as necessary (see below).
-- 6. Rename entity if necessary to avoid name collisions.
-- 7. Change INIT port direction from "in" to "inout" (see below).
-- 8. Change COMPLIANCE_PATTERNS to "(PROGRAM) (1)" (see below).
-- 9. Change INIT boundary cells from internal to controlr, output3,
-- 	and input, respectively (see below).
-- 10. Remove the design warning regarding keeping INIT low.
-- 
-- NOTE: Post-configuration JTAG is available only if the BSCAN symbol
-- 	is instantiated in the FPGA design.
-- NOTE: PULLUP symbols must be instantiated on the TMS and TDI pins
-- 	in the FPGA design to comply with IEEE Std. 1149.1-1993.

entity XCS05_VQ100 is

generic (PHYSICAL_PIN_MAP : string := "VQ100" );

port (
	CCLK: linkage bit;
	DONE: linkage bit;
	GND: linkage bit_vector (1 to 8);
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the following line so
-- that INIT is of type inout.
-- 	INIT: inout bit;
	INIT: in bit; 
	IO2: inout bit;
	IO3: inout bit;
	IO4: inout bit;
	IO5: inout bit;
	IO6: inout bit;
	IO7: inout bit;
	IO8: inout bit;
	IO9: inout bit;
	IO10: inout bit;
	IO11: inout bit;
	IO15: inout bit;
	IO16: inout bit;
	IO20: inout bit;
	IO22: inout bit;
	IO23: inout bit;
	IO24: inout bit;
	IO27: inout bit;
	IO28: inout bit;
	IO29: inout bit;
	IO31: inout bit;
	IO32: inout bit;
	IO33: inout bit;
	IO34: inout bit;
	IO35: inout bit;
	IO36: inout bit;
	IO42: inout bit;
	IO43: inout bit;
	IO44: inout bit;
	IO45: inout bit;
	IO46: inout bit;
	IO47: inout bit;
	IO48: inout bit;
	IO49: inout bit;
	IO50: inout bit;
	IO54: inout bit;
	IO55: inout bit;
	IO56: inout bit;
	IO57: inout bit;
	IO58: inout bit;
	IO59: inout bit;
	IO60: inout bit;
	IO61: inout bit;
	IO62: inout bit;
	IO63: inout bit;
	IO68: inout bit;
	IO69: inout bit;
	IO70: inout bit;
	IO71: inout bit;
	IO72: inout bit;
	IO73: inout bit;
	IO74: inout bit;
	IO75: inout bit;
	IO76: inout bit;
	IO77: inout bit;
	IO80: inout bit;
	IO81: inout bit;
	IO82: inout bit;
	IO84: inout bit;
	IO85: inout bit;
	IO86: inout bit;
	IO87: inout bit;
	IO88: inout bit;
	IO89: inout bit;
	IO94: inout bit;
	IO95: inout bit;
	IO96: inout bit;
	IO97: inout bit;
	IO98: inout bit;
	IO99: inout bit;
	IO100: inout bit;
	IO101: inout bit;
	IO102: inout bit;
	IO103: inout bit;
	MODE: inout bit;
	PROGRAM: in bit;
	TCK: in bit;
	TDI: in bit;
	TDO: out bit;
	TMS: in bit;
	VDD: linkage bit_vector (1 to 8)
); --end port list

use STD_1149_1_1994.all;

attribute COMPONENT_CONFORMANCE of XCS05_VQ100 : entity is
	"STD_1149_1_1993";

attribute PIN_MAP of XCS05_VQ100 : entity is PHYSICAL_PIN_MAP;

constant VQ100: PIN_MAP_STRING:=
	"CCLK:      P74," &
	"DONE:      P50," &
	"GND:(       P1,      P11,      P23,      P38,      P49,      P64,      P77,      P88)," &
	"INIT:      P36," &
	"IO2:      P90," &
	"IO3:      P91," &
	"IO4:      P92," &
	"IO5:      P93," &
	"IO6:      P94," &
	"IO7:      P95," &
	"IO8:      P96," &
	"IO9:      P97," &
	"IO10:      P98," &
	"IO11:      P99," &
	"IO15:       P2," &
	"IO16:       P3," &
	"IO20:       P7," &
	"IO22:       P8," &
	"IO23:       P9," &
	"IO24:      P10," &
	"IO27:      P13," &
	"IO28:      P14," &
	"IO29:      P15," &
	"IO31:      P16," &
	"IO32:      P17," &
	"IO33:      P18," &
	"IO34:      P19," &
	"IO35:      P20," &
	"IO36:      P21," &
	"IO42:      P27," &
	"IO43:      P28," &
	"IO44:      P29," &
	"IO45:      P30," &
	"IO46:      P31," &
	"IO47:      P32," &
	"IO48:      P33," &
	"IO49:      P34," &
	"IO50:      P35," &
	"IO54:      P39," &
	"IO55:      P40," &
	"IO56:      P41," &
	"IO57:      P42," &
	"IO58:      P43," &
	"IO59:      P44," &
	"IO60:      P45," &
	"IO61:      P46," &
	"IO62:      P47," &
	"IO63:      P48," &
	"IO68:      P53," &
	"IO69:      P54," &
	"IO70:      P55," &
	"IO71:      P56," &
	"IO72:      P57," &
	"IO73:      P58," &
	"IO74:      P59," &
	"IO75:      P60," &
	"IO76:      P61," &
	"IO77:      P62," &
	"IO80:      P65," &
	"IO81:      P66," &
	"IO82:      P67," &
	"IO84:      P68," &
	"IO85:      P69," &
	"IO86:      P70," &
	"IO87:      P71," &
	"IO88:      P72," &
	"IO89:      P73," &
	"IO94:      P78," &
	"IO95:      P79," &
	"IO96:      P80," &
	"IO97:      P81," &
	"IO98:      P82," &
	"IO99:      P83," &
	"IO100:      P84," &
	"IO101:      P85," &
	"IO102:      P86," &
	"IO103:      P87," &
	"MODE:      P24," &
	"PROGRAM:      P52," &
	"TCK:       P5," &
	"TDI:       P4," &
	"TDO:      P76," &
	"TMS:       P6," &
	"VDD:(      P89,     P100,      P12,      P25,      P37,      P51,      P63,      P75)";
--end pin map

attribute TAP_SCAN_IN    of TDI : signal is true;
attribute TAP_SCAN_MODE  of TMS : signal is true;
attribute TAP_SCAN_OUT   of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (2.0e6, LOW);
-- This is conservative. Real max is expected to be (~5MHz, BOTH).

attribute COMPLIANCE_PATTERNS of XCS05_VQ100 : entity is
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the corresponding line
-- below.
-- 	"(PROGRAM) (1)";
-- 
-- NOTE: If INIT has been high or floating since the later of power-on
-- 	and the last rising transition of PROGRAM, then the device may
-- 	be in configuration mode in which case some JTAG instructions
-- 	will not be available.
	"(INIT,PROGRAM) (01)"; 

attribute INSTRUCTION_LENGTH of XCS05_VQ100 : entity is 3;

attribute INSTRUCTION_OPCODE of XCS05_VQ100 : entity is
	"SAMPLE (001)," & -- Internal capture not valid until after config
	"RESERVED (110)," &
	"READBACK (100)," & -- Not available during configuration
	"CONFIGURE (101)," & -- Not available during configuration
	"USER2 (011)," & -- Not available until after configuration
	"USER1 (010)," & -- Not available until after configuration
	"EXTEST (000)," & -- Not available during configuration
	"BYPASS (111)";

attribute INSTRUCTION_CAPTURE of XCS05_VQ100 : entity is "X01";
-- MSB of instruction capture is low during configuration.

-- If the device is configured, and a USER instruction is implemented
-- and not private to the FPGA designer, then it should be removed
-- from INSTRUCTION_PRIVATE, and the target register should be defined
-- in REGISTER_ACCESS.

attribute INSTRUCTION_PRIVATE of XCS05_VQ100 : entity is
	"USER1," &
	"USER2," &
	"READBACK," &
	"RESERVED," &
	"CONFIGURE";

attribute REGISTER_ACCESS of XCS05_VQ100 : entity is
--	"<reg_name>[<length>] (USER1)," &
--	"<reg_name>[<length>] (USER2)," &
	"BYPASS (BYPASS)," &
	"BOUNDARY (SAMPLE,EXTEST)";

attribute BOUNDARY_LENGTH of XCS05_VQ100 : entity is 248;

attribute BOUNDARY_REGISTER of XCS05_VQ100 : entity is
-- cellnum (type, port, function, safe[, ccell, disval, disrslt])
	"   0 (BC_1, *, internal, X)," &
	"   1 (BC_1, *, internal, X)," &
	"   2 (BC_1, *, controlr, 1)," &
	"   3 (BC_1, IO94, output3, X, 2, 1, PULL1)," &
	"   4 (BC_1, IO94, input, X)," &
	"   5 (BC_1, *, controlr, 1)," &
	"   6 (BC_1, IO95, output3, X, 5, 1, PULL1)," &
	"   7 (BC_1, IO95, input, X)," &
	"   8 (BC_1, *, controlr, 1)," &
	"   9 (BC_1, IO96, output3, X, 8, 1, PULL1)," &
	"  10 (BC_1, IO96, input, X)," &
	"  11 (BC_1, *, controlr, 1)," &
	"  12 (BC_1, IO97, output3, X, 11, 1, PULL1)," &
	"  13 (BC_1, IO97, input, X)," &
	"  14 (BC_1, *, controlr, 1)," &
	"  15 (BC_1, IO98, output3, X, 14, 1, PULL1)," &
	"  16 (BC_1, IO98, input, X)," &
	"  17 (BC_1, *, controlr, 1)," &
	"  18 (BC_1, IO99, output3, X, 17, 1, PULL1)," &
	"  19 (BC_1, IO99, input, X)," &
	"  20 (BC_1, *, controlr, 1)," &
	"  21 (BC_1, IO100, output3, X, 20, 1, PULL1)," &
	"  22 (BC_1, IO100, input, X)," &
	"  23 (BC_1, *, controlr, 1)," &
	"  24 (BC_1, IO101, output3, X, 23, 1, PULL1)," &
	"  25 (BC_1, IO101, input, X)," &
	"  26 (BC_1, *, controlr, 1)," &
	"  27 (BC_1, IO102, output3, X, 26, 1, PULL1)," &
	"  28 (BC_1, IO102, input, X)," &
	"  29 (BC_1, *, controlr, 1)," &
	"  30 (BC_1, IO103, output3, X, 29, 1, PULL1)," &
	"  31 (BC_1, IO103, input, X)," &
	"  32 (BC_1, *, controlr, 1)," &
	"  33 (BC_1, IO2, output3, X, 32, 1, PULL1)," &
	"  34 (BC_1, IO2, input, X)," &
	"  35 (BC_1, *, controlr, 1)," &
	"  36 (BC_1, IO3, output3, X, 35, 1, PULL1)," &
	"  37 (BC_1, IO3, input, X)," &
	"  38 (BC_1, *, controlr, 1)," &
	"  39 (BC_1, IO4, output3, X, 38, 1, PULL1)," &
	"  40 (BC_1, IO4, input, X)," &
	"  41 (BC_1, *, controlr, 1)," &
	"  42 (BC_1, IO5, output3, X, 41, 1, PULL1)," &
	"  43 (BC_1, IO5, input, X)," &
	"  44 (BC_1, *, controlr, 1)," &
	"  45 (BC_1, IO6, output3, X, 44, 1, PULL1)," &
	"  46 (BC_1, IO6, input, X)," &
	"  47 (BC_1, *, controlr, 1)," &
	"  48 (BC_1, IO7, output3, X, 47, 1, PULL1)," &
	"  49 (BC_1, IO7, input, X)," &
	"  50 (BC_1, *, controlr, 1)," &
	"  51 (BC_1, IO8, output3, X, 50, 1, PULL1)," &
	"  52 (BC_1, IO8, input, X)," &
	"  53 (BC_1, *, controlr, 1)," &
	"  54 (BC_1, IO9, output3, X, 53, 1, PULL1)," &
	"  55 (BC_1, IO9, input, X)," &
	"  56 (BC_1, *, controlr, 1)," &
	"  57 (BC_1, IO10, output3, X, 56, 1, PULL1)," &
	"  58 (BC_1, IO10, input, X)," &
	"  59 (BC_1, *, controlr, 1)," &
	"  60 (BC_1, IO11, output3, X, 59, 1, PULL1)," &
	"  61 (BC_1, IO11, input, X)," &
	"  62 (BC_1, *, controlr, 1)," &
	"  63 (BC_1, IO15, output3, X, 62, 1, PULL1)," &
	"  64 (BC_1, IO15, input, X)," &
	"  65 (BC_1, *, controlr, 1)," &
	"  66 (BC_1, IO16, output3, X, 65, 1, PULL1)," &
	"  67 (BC_1, IO16, input, X)," &
	"  68 (BC_1, *, internal, X)," &
	"  69 (BC_1, *, internal, X)," &
	"  70 (BC_1, *, internal, X)," &
	"  71 (BC_1, *, internal, X)," &
	"  72 (BC_1, *, internal, X)," &
	"  73 (BC_1, *, internal, X)," &
	"  74 (BC_1, *, internal, X)," &
	"  75 (BC_1, *, internal, X)," &
	"  76 (BC_1, *, internal, X)," &
	"  77 (BC_1, *, controlr, 1)," &
	"  78 (BC_1, IO20, output3, X, 77, 1, PULL1)," &
	"  79 (BC_1, IO20, input, X)," &
	"  80 (BC_1, *, internal, 1)," & -- IO21.T
	"  81 (BC_1, *, internal, X)," & -- IO21.O
	"  82 (BC_1, *, internal, X)," & -- IO21.I
	"  83 (BC_1, *, controlr, 1)," &
	"  84 (BC_1, IO22, output3, X, 83, 1, PULL1)," &
	"  85 (BC_1, IO22, input, X)," &
	"  86 (BC_1, *, controlr, 1)," &
	"  87 (BC_1, IO23, output3, X, 86, 1, PULL1)," &
	"  88 (BC_1, IO23, input, X)," &
	"  89 (BC_1, *, controlr, 1)," &
	"  90 (BC_1, IO24, output3, X, 89, 1, PULL1)," &
	"  91 (BC_1, IO24, input, X)," &
	"  92 (BC_1, *, controlr, 1)," &
	"  93 (BC_1, IO27, output3, X, 92, 1, PULL1)," &
	"  94 (BC_1, IO27, input, X)," &
	"  95 (BC_1, *, controlr, 1)," &
	"  96 (BC_1, IO28, output3, X, 95, 1, PULL1)," &
	"  97 (BC_1, IO28, input, X)," &
	"  98 (BC_1, *, controlr, 1)," &
	"  99 (BC_1, IO29, output3, X, 98, 1, PULL1)," &
	" 100 (BC_1, IO29, input, X)," &
	" 101 (BC_1, *, internal, 1)," & -- IO30.T
	" 102 (BC_1, *, internal, X)," & -- IO30.O
	" 103 (BC_1, *, internal, X)," & -- IO30.I
	" 104 (BC_1, *, controlr, 1)," &
	" 105 (BC_1, IO31, output3, X, 104, 1, PULL1)," &
	" 106 (BC_1, IO31, input, X)," &
	" 107 (BC_1, *, controlr, 1)," &
	" 108 (BC_1, IO32, output3, X, 107, 1, PULL1)," &
	" 109 (BC_1, IO32, input, X)," &
	" 110 (BC_1, *, controlr, 1)," &
	" 111 (BC_1, IO33, output3, X, 110, 1, PULL1)," &
	" 112 (BC_1, IO33, input, X)," &
	" 113 (BC_1, *, controlr, 1)," &
	" 114 (BC_1, IO34, output3, X, 113, 1, PULL1)," &
	" 115 (BC_1, IO34, input, X)," &
	" 116 (BC_1, *, controlr, 1)," &
	" 117 (BC_1, IO35, output3, X, 116, 1, PULL1)," &
	" 118 (BC_1, IO35, input, X)," &
	" 119 (BC_1, *, controlr, 1)," &
	" 120 (BC_1, IO36, output3, X, 119, 1, PULL1)," &
	" 121 (BC_1, IO36, input, X)," &
	" 122 (BC_1, *, controlr, 1)," &
	" 123 (BC_1, MODE, output3, X, 122, 1, PULL1)," &
	" 124 (BC_1, MODE, input, X)," &
	" 125 (BC_4, MODE, observe_only, X)," &
	" 126 (BC_4, MODE, observe_only, X)," &
	" 127 (BC_1, *, controlr, 1)," &
	" 128 (BC_1, IO42, output3, X, 127, 1, PULL1)," &
	" 129 (BC_1, IO42, input, X)," &
	" 130 (BC_1, *, controlr, 1)," &
	" 131 (BC_1, IO43, output3, X, 130, 1, PULL1)," &
	" 132 (BC_1, IO43, input, X)," &
	" 133 (BC_1, *, controlr, 1)," &
	" 134 (BC_1, IO44, output3, X, 133, 1, PULL1)," &
	" 135 (BC_1, IO44, input, X)," &
	" 136 (BC_1, *, controlr, 1)," &
	" 137 (BC_1, IO45, output3, X, 136, 1, PULL1)," &
	" 138 (BC_1, IO45, input, X)," &
	" 139 (BC_1, *, controlr, 1)," &
	" 140 (BC_1, IO46, output3, X, 139, 1, PULL1)," &
	" 141 (BC_1, IO46, input, X)," &
	" 142 (BC_1, *, controlr, 1)," &
	" 143 (BC_1, IO47, output3, X, 142, 1, PULL1)," &
	" 144 (BC_1, IO47, input, X)," &
	" 145 (BC_1, *, controlr, 1)," &
	" 146 (BC_1, IO48, output3, X, 145, 1, PULL1)," &
	" 147 (BC_1, IO48, input, X)," &
	" 148 (BC_1, *, controlr, 1)," &
	" 149 (BC_1, IO49, output3, X, 148, 1, PULL1)," &
	" 150 (BC_1, IO49, input, X)," &
	" 151 (BC_1, *, controlr, 1)," &
	" 152 (BC_1, IO50, output3, X, 151, 1, PULL1)," &
	" 153 (BC_1, IO50, input, X)," &
-- INIT is not a compliance enable after configuration. For post-configuration
-- operation un-comment the next line and comment out the following line.
-- Repeat for registers 154 through 156.
-- 	" 154 (BC_1, *, controlr, 1)," &
	" 154 (BC_1, *, internal, 1)," & 
-- 	" 155 (BC_1, INIT, output3, X, 154, 1, PULL1)," &
	" 155 (BC_1, *, internal, 0)," & 
-- 	" 156 (BC_1, INIT, input, X)," &
	" 156 (BC_1, *, internal, X)," & 
	" 157 (BC_1, *, controlr, 1)," &
	" 158 (BC_1, IO54, output3, X, 157, 1, PULL1)," &
	" 159 (BC_1, IO54, input, X)," &
	" 160 (BC_1, *, controlr, 1)," &
	" 161 (BC_1, IO55, output3, X, 160, 1, PULL1)," &
	" 162 (BC_1, IO55, input, X)," &
	" 163 (BC_1, *, controlr, 1)," &
	" 164 (BC_1, IO56, output3, X, 163, 1, PULL1)," &
	" 165 (BC_1, IO56, input, X)," &
	" 166 (BC_1, *, controlr, 1)," &
	" 167 (BC_1, IO57, output3, X, 166, 1, PULL1)," &
	" 168 (BC_1, IO57, input, X)," &
	" 169 (BC_1, *, controlr, 1)," &
	" 170 (BC_1, IO58, output3, X, 169, 1, PULL1)," &
	" 171 (BC_1, IO58, input, X)," &
	" 172 (BC_1, *, controlr, 1)," &
	" 173 (BC_1, IO59, output3, X, 172, 1, PULL1)," &
	" 174 (BC_1, IO59, input, X)," &
	" 175 (BC_1, *, controlr, 1)," &
	" 176 (BC_1, IO60, output3, X, 175, 1, PULL1)," &
	" 177 (BC_1, IO60, input, X)," &
	" 178 (BC_1, *, controlr, 1)," &
	" 179 (BC_1, IO61, output3, X, 178, 1, PULL1)," &
	" 180 (BC_1, IO61, input, X)," &
	" 181 (BC_1, *, controlr, 1)," &
	" 182 (BC_1, IO62, output3, X, 181, 1, PULL1)," &
	" 183 (BC_1, IO62, input, X)," &
	" 184 (BC_1, *, controlr, 1)," &
	" 185 (BC_1, IO63, output3, X, 184, 1, PULL1)," &
	" 186 (BC_1, IO63, input, X)," &
	" 187 (BC_1, *, controlr, 1)," &
	" 188 (BC_1, IO68, output3, X, 187, 1, PULL1)," &
	" 189 (BC_1, IO68, input, X)," &
	" 190 (BC_1, *, controlr, 1)," &
	" 191 (BC_1, IO69, output3, X, 190, 1, PULL1)," &
	" 192 (BC_1, IO69, input, X)," &
	" 193 (BC_1, *, controlr, 1)," &
	" 194 (BC_1, IO70, output3, X, 193, 1, PULL1)," &
	" 195 (BC_1, IO70, input, X)," &
	" 196 (BC_1, *, controlr, 1)," &
	" 197 (BC_1, IO71, output3, X, 196, 1, PULL1)," &
	" 198 (BC_1, IO71, input, X)," &
	" 199 (BC_1, *, controlr, 1)," &
	" 200 (BC_1, IO72, output3, X, 199, 1, PULL1)," &
	" 201 (BC_1, IO72, input, X)," &
	" 202 (BC_1, *, controlr, 1)," &
	" 203 (BC_1, IO73, output3, X, 202, 1, PULL1)," &
	" 204 (BC_1, IO73, input, X)," &
	" 205 (BC_1, *, controlr, 1)," &
	" 206 (BC_1, IO74, output3, X, 205, 1, PULL1)," &
	" 207 (BC_1, IO74, input, X)," &
	" 208 (BC_1, *, controlr, 1)," &
	" 209 (BC_1, IO75, output3, X, 208, 1, PULL1)," &
	" 210 (BC_1, IO75, input, X)," &
	" 211 (BC_1, *, controlr, 1)," &
	" 212 (BC_1, IO76, output3, X, 211, 1, PULL1)," &
	" 213 (BC_1, IO76, input, X)," &
	" 214 (BC_1, *, controlr, 1)," &
	" 215 (BC_1, IO77, output3, X, 214, 1, PULL1)," &
	" 216 (BC_1, IO77, input, X)," &
	" 217 (BC_1, *, controlr, 1)," &
	" 218 (BC_1, IO80, output3, X, 217, 1, PULL1)," &
	" 219 (BC_1, IO80, input, X)," &
	" 220 (BC_1, *, controlr, 1)," &
	" 221 (BC_1, IO81, output3, X, 220, 1, PULL1)," &
	" 222 (BC_1, IO81, input, X)," &
	" 223 (BC_1, *, controlr, 1)," &
	" 224 (BC_1, IO82, output3, X, 223, 1, PULL1)," &
	" 225 (BC_1, IO82, input, X)," &
	" 226 (BC_1, *, internal, 1)," & -- IO83.T
	" 227 (BC_1, *, internal, X)," & -- IO83.O
	" 228 (BC_1, *, internal, X)," & -- IO83.I
	" 229 (BC_1, *, controlr, 1)," &
	" 230 (BC_1, IO84, output3, X, 229, 1, PULL1)," &
	" 231 (BC_1, IO84, input, X)," &
	" 232 (BC_1, *, controlr, 1)," &
	" 233 (BC_1, IO85, output3, X, 232, 1, PULL1)," &
	" 234 (BC_1, IO85, input, X)," &
	" 235 (BC_1, *, controlr, 1)," &
	" 236 (BC_1, IO86, output3, X, 235, 1, PULL1)," &
	" 237 (BC_1, IO86, input, X)," &
	" 238 (BC_1, *, controlr, 1)," &
	" 239 (BC_1, IO87, output3, X, 238, 1, PULL1)," &
	" 240 (BC_1, IO87, input, X)," &
	" 241 (BC_1, *, controlr, 1)," &
	" 242 (BC_1, IO88, output3, X, 241, 1, PULL1)," &
	" 243 (BC_1, IO88, input, X)," &
	" 244 (BC_1, *, controlr, 1)," &
	" 245 (BC_1, IO89, output3, X, 244, 1, PULL1)," &
	" 246 (BC_1, IO89, input, X)," &
	" 247 (BC_1, *, internal, X)";
--end boundary register

attribute DESIGN_WARNING of XCS05_VQ100 : entity is
	"CCLK and DONE are not represented in BOUNDARY_REGISTER." &
	"This BSDL file must be modified by the FPGA designer in order to" &
		"reflect post-configuration behavior (if any)." &
	"If INIT has been high or floating since power-on or the last" &
		"rising edge of PROGRAM, then the device may be in" &
		"configuration mode in which case this file is not valid." &
	"The output and tristate capture values are not valid until after" &
		"the device is configured." &
	"The tristate control is not captured properly when GTS is activated." &
	"Some pins have both controlled and uncontrolled input paths.";

end XCS05_VQ100;