-- Generated by boundaryScanGenerate 6.0a.SP2-Build20071205.019 on 01/15/09 15:05:33 -- BSDL Version 2001 entity chip is generic (PHYSICAL_PIN_MAP : string := "DEFAULT_PACKAGE_NAME"); port ( -- Port List TX5 : out bit; DTR5 : out bit; DSR5 : in bit; CD5 : in bit; RI5 : in bit; RX5 : in bit; GPIO0 : inout bit; GPIO1 : inout bit; GPIO2 : inout bit; GPIO3 : inout bit; GPIO4 : inout bit; GPIO5 : inout bit; GPIO6 : inout bit; TXP : out bit; TXM : out bit; RXP : in bit; RXM : in bit; NCLKREQ : out bit; NPERST : in bit; GPIO7 : inout bit; GPIO8 : inout bit; GPIO9 : inout bit; GPIO10 : inout bit; GPIO11 : inout bit; GPIO12 : inout bit; GPIO13 : inout bit; GPIO14 : inout bit; GPIO15 : inout bit; RESETB : in bit; TRST : in bit; TCK : in bit; TMS : in bit; TDI : in bit; TDO : out bit; RX3 : in bit; TX3 : out bit; RTS3 : out bit; CTS3 : inout bit; DTR3 : out bit; DSR3 : in bit; CD3 : in bit; RTS6 : out bit; TX6 : out bit; RI3 : in bit; RX6 : in bit; CTS6 : inout bit; DTR6 : out bit; DSR6 : in bit; CD6 : in bit; RI6 : in bit; TX7 : out bit; RTS7 : out bit; RX7 : in bit; CTS7 : inout bit; DTR7 : out bit; DSR7 : in bit; CD7 : in bit; RI7 : in bit; EECK : inout bit; EECS : inout bit; EEDI : out bit; EEDO : in bit; TX0 : out bit; RTS0 : out bit; RX0 : in bit; CTS0 : inout bit; DTR0 : out bit; DSR0 : in bit; CD0 : in bit; RI0 : in bit; TX1 : out bit; RTS1 : out bit; RX1 : in bit; CTS1 : inout bit; DTR1 : out bit; DSR1 : in bit; CD1 : in bit; RI1 : in bit; PRES : in bit; MODE : in bit; CLK : inout bit; SEL : inout bit; DB7 : inout bit; DB6 : inout bit; DB5 : inout bit; DB4 : inout bit; DB3 : inout bit; DB2 : inout bit; DB1 : inout bit; DB0 : inout bit; INT : inout bit; TEST1 : in bit; TEST2 : in bit; EN485 : in bit; ENIR : in bit; TMRCK : in bit; TX2 : out bit; RX2 : in bit; RTS2 : out bit; CTS2 : inout bit; DTR2 : out bit; DSR2 : in bit; CD2 : in bit; RI2 : in bit; TX4 : out bit; RX4 : in bit; RTS4 : out bit; CTS4 : inout bit; DTR4 : out bit; DSR4 : in bit; CD4 : in bit; RI4 : in bit; RTS5 : out bit; CTS5 : inout bit); use STD_1149_1_2001.all; use STD_1149_6_2003.all; use LVS_BSCAN_CELLS.all; attribute COMPONENT_CONFORMANCE of chip: entity is "STD_1149_1_2001"; --Pin mappings attribute PIN_MAP of chip: entity is PHYSICAL_PIN_MAP; constant DEFAULT_PACKAGE_NAME: PIN_MAP_STRING := "TX5 : A2 , " & "DTR5 : B2 , " & "DSR5 : C3 , " & "CD5 : B1 , " & "RI5 : C2 , " & "RX5 : D3 , " & "GPIO0 : C1 , " & "GPIO1 : D2 , " & "GPIO2 : D1 , " & "GPIO3 : E3 , " & "GPIO4 : E2 , " & "GPIO5 : E1 , " & "GPIO6 : F3 , " & "TXP : J1 , " & "TXM : J2 , " & "RXP : G1 , " & "RXM : G2 , " & "NCLKREQ : L1 , " & "NPERST : L2 , " & "GPIO7 : L3 , " & "GPIO8 : M2 , " & "GPIO9 : N1 , " & "GPIO10 : P1 , " & "GPIO11 : M3 , " & "GPIO12 : N2 , " & "GPIO13 : P2 , " & "GPIO14 : M4 , " & "GPIO15 : N3 , " & "RESETB : R2 , " & "TRST : N4 , " & "TCK : P3 , " & "TMS : M5 , " & "TDI : R3 , " & "TDO : P4 , " & "RX3 : R5 , " & "TX3 : N5 , " & "RTS3 : P5 , " & "CTS3 : N6 , " & "DTR3 : P6 , " & "DSR3 : R6 , " & "CD3 : N7 , " & "RTS6 : P7 , " & "TX6 : R7 , " & "RI3 : N8 , " & "RX6 : P8 , " & "CTS6 : R9 , " & "DTR6 : P9 , " & "DSR6 : N9 , " & "CD6 : R10 , " & "RI6 : P10 , " & "TX7 : N10 , " & "RTS7 : R11 , " & "RX7 : P11 , " & "CTS7 : N11 , " & "DTR7 : P12 , " & "DSR7 : R13 , " & "CD7 : M11 , " & "RI7 : N12 , " & "EECK : P13 , " & "EECS : R14 , " & "EEDI : P14 , " & "EEDO : M12 , " & "TX0 : N13 , " & "RTS0 : P15 , " & "RX0 : M13 , " & "CTS0 : N14 , " & "DTR0 : N15 , " & "DSR0 : M14 , " & "CD0 : L13 , " & "RI0 : L14 , " & "TX1 : L15 , " & "RTS1 : K13 , " & "RX1 : K14 , " & "CTS1 : K15 , " & "DTR1 : J13 , " & "DSR1 : J14 , " & "CD1 : J15 , " & "RI1 : H13 , " & "PRES : H14 , " & "MODE : G15 , " & "CLK : G14 , " & "SEL : G13 , " & "DB7 : F15 , " & "DB6 : F14 , " & "DB5 : F13 , " & "DB4 : E15 , " & "DB3 : E14 , " & "DB2 : D15 , " & "DB1 : E13 , " & "DB0 : C15 , " & "INT : D14 , " & "TEST1 : B11 , " & "TEST2 : A11 , " & "EN485 : C10 , " & "ENIR : B10 , " & "TMRCK : A10 , " & "TX2 : C9 , " & "RX2 : B9 , " & "RTS2 : A9 , " & "CTS2 : C8 , " & "DTR2 : B8 , " & "DSR2 : A7 , " & "CD2 : B7 , " & "RI2 : C7 , " & "TX4 : A6 , " & "RX4 : B6 , " & "RTS4 : C6 , " & "CTS4 : A5 , " & "DTR4 : B5 , " & "DSR4 : C5 , " & "CD4 : B4 , " & "RI4 : A3 , " & "RTS5 : C4 , " & "CTS5 : B3 " ; attribute PORT_GROUPING of chip : entity is "Differential_Voltage ( (TXP, TXM), " & "(RXP, RXM)) " ; attribute TAP_SCAN_RESET of TRST : signal is true; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (1.0000000000000000000e+07, BOTH); attribute INSTRUCTION_LENGTH of chip: entity is 25; attribute INSTRUCTION_OPCODE of chip: entity is "IDCODE (1111111111111111111111110)," & "BYPASS (0000000000000000000000000, 1111111111111111111111111)," & "EXTEST (1111111111111111111101000)," & "EXTEST_PULSE (1111111101111111111101000)," & "EXTEST_TRAIN (1111111011111111111101000)," & "SAMPLE (1111111111111111111111000)," & "PRELOAD (1111111111111111111111000)," & "HIGHZ (1111111111111111111001111)," & "CLAMP (1111111111111111111101111) " ; attribute INSTRUCTION_CAPTURE of chip: entity is "xxxxxxxxxxxxxxxxxxxxxxx01"; attribute IDCODE_REGISTER of chip: entity is "0011" & -- version "0000001101011000" & -- part number "00001011110" & -- manufacturer's identity "1"; -- required by 1149.1 attribute REGISTER_ACCESS of chip: entity is "BOUNDARY ( EXTEST_PULSE, EXTEST_TRAIN )," & "BOUNDARY ( SAMPLE, PRELOAD )," & "BYPASS ( HIGHZ, CLAMP, BYPASS ) " ; --Boundary scan definition attribute BOUNDARY_LENGTH of chip: entity is 132; attribute BOUNDARY_REGISTER of chip: entity is -- num cell port function safe [ccell disval rslt] " 131 (BC_2 , * , control , 1 ) ,"& " 130 (BC_2 , TX5 , output3 , X , 131 , 1 , Z ),"& " 129 (BC_2 , DTR5 , output3 , X , 131 , 1 , Z ),"& " 128 (BC_2 , DSR5 , input , X ) ,"& " 127 (BC_2 , CD5 , input , X ) ,"& " 126 (BC_2 , RI5 , input , X ) ,"& " 125 (BC_2 , RX5 , input , X ) ,"& " 124 (BC_2 , * , control , 1 ) ,"& " 123 (LV_BC_7 , GPIO0 , bidir , X , 124 , 1 , Z ),"& " 122 (BC_2 , * , control , 1 ) ,"& " 121 (LV_BC_7 , GPIO1 , bidir , X , 122 , 1 , Z ),"& " 120 (BC_2 , * , control , 1 ) ,"& " 119 (LV_BC_7 , GPIO2 , bidir , X , 120 , 1 , Z ),"& " 118 (BC_2 , * , control , 1 ) ,"& " 117 (LV_BC_7 , GPIO3 , bidir , X , 118 , 1 , Z ),"& " 116 (BC_2 , * , control , 1 ) ,"& " 115 (LV_BC_7 , GPIO4 , bidir , X , 116 , 1 , Z ),"& " 114 (BC_2 , * , control , 1 ) ,"& " 113 (LV_BC_7 , GPIO5 , bidir , X , 114 , 1 , Z ),"& " 112 (BC_2 , * , control , 1 ) ,"& " 111 (LV_BC_7 , GPIO6 , bidir , X , 112 , 1 , Z ),"& " 110 (BC_1 , * , control , 0 ) ,"& " 109 (AC_1 , TXP , output3 , X , 110 , 0 , Z ),"& " 108 (BC_4 , RXP , observe_only , X ) ,"& " 107 (BC_4 , RXM , observe_only , X ) ,"& " 106 (BC_2 , NCLKREQ , output3 , X , 131 , 1 , Z ),"& " 105 (BC_2 , NPERST , input , X ) ,"& " 104 (BC_2 , * , control , 1 ) ,"& " 103 (LV_BC_7 , GPIO7 , bidir , X , 104 , 1 , Z ),"& " 102 (BC_2 , * , control , 1 ) ,"& " 101 (LV_BC_7 , GPIO8 , bidir , X , 102 , 1 , Z ),"& " 100 (BC_2 , * , control , 1 ) ,"& " 99 (LV_BC_7 , GPIO9 , bidir , X , 100 , 1 , Z ),"& " 98 (BC_2 , * , control , 1 ) ,"& " 97 (LV_BC_7 , GPIO10 , bidir , X , 98 , 1 , Z ),"& " 96 (BC_2 , * , control , 1 ) ,"& " 95 (LV_BC_7 , GPIO11 , bidir , X , 96 , 1 , Z ),"& " 94 (BC_2 , * , control , 1 ) ,"& " 93 (LV_BC_7 , GPIO12 , bidir , X , 94 , 1 , Z ),"& " 92 (BC_2 , * , control , 1 ) ,"& " 91 (LV_BC_7 , GPIO13 , bidir , X , 92 , 1 , Z ),"& " 90 (BC_2 , * , control , 1 ) ,"& " 89 (LV_BC_7 , GPIO14 , bidir , X , 90 , 1 , Z ),"& " 88 (BC_2 , * , control , 1 ) ,"& " 87 (LV_BC_7 , GPIO15 , bidir , X , 88 , 1 , Z ),"& " 86 (BC_2 , RESETB , input , X ) ,"& " 85 (BC_2 , RX3 , input , X ) ,"& " 84 (BC_2 , TX3 , output3 , X , 131 , 1 , Z ),"& " 83 (BC_2 , RTS3 , output3 , X , 131 , 1 , Z ),"& " 82 (BC_2 , * , control , 1 ) ,"& " 81 (LV_BC_7 , CTS3 , bidir , X , 82 , 1 , Z ),"& " 80 (BC_2 , DTR3 , output3 , X , 131 , 1 , Z ),"& " 79 (BC_2 , DSR3 , input , X ) ,"& " 78 (BC_2 , CD3 , input , X ) ,"& " 77 (BC_2 , RTS6 , output3 , X , 131 , 1 , Z ),"& " 76 (BC_2 , TX6 , output3 , X , 131 , 1 , Z ),"& " 75 (BC_2 , RI3 , input , X ) ,"& " 74 (BC_2 , RX6 , input , X ) ,"& " 73 (LV_BC_7 , CTS6 , bidir , X , 82 , 1 , Z ),"& " 72 (BC_2 , DTR6 , output3 , X , 131 , 1 , Z ),"& " 71 (BC_2 , DSR6 , input , X ) ,"& " 70 (BC_2 , CD6 , input , X ) ,"& " 69 (BC_2 , RI6 , input , X ) ,"& " 68 (BC_2 , TX7 , output3 , X , 131 , 1 , Z ),"& " 67 (BC_2 , RTS7 , output3 , X , 131 , 1 , Z ),"& " 66 (BC_2 , RX7 , input , X ) ,"& " 65 (LV_BC_7 , CTS7 , bidir , X , 82 , 1 , Z ),"& " 64 (BC_2 , DTR7 , output3 , X , 131 , 1 , Z ),"& " 63 (BC_2 , DSR7 , input , X ) ,"& " 62 (BC_2 , CD7 , input , X ) ,"& " 61 (BC_2 , RI7 , input , X ) ,"& " 60 (BC_2 , * , control , 1 ) ,"& " 59 (LV_BC_7 , EECK , bidir , X , 60 , 1 , Z ),"& " 58 (LV_BC_7 , EECS , bidir , X , 60 , 1 , Z ),"& " 57 (BC_2 , EEDI , output3 , X , 60 , 1 , Z ),"& " 56 (BC_2 , EEDO , input , X ) ,"& " 55 (BC_2 , TX0 , output3 , X , 131 , 1 , Z ),"& " 54 (BC_2 , * , control , 1 ) ,"& " 53 (BC_2 , RTS0 , output3 , X , 54 , 1 , Z ),"& " 52 (BC_2 , RX0 , input , X ) ,"& " 51 (LV_BC_7 , CTS0 , bidir , X , 82 , 1 , Z ),"& " 50 (BC_2 , DTR0 , output3 , X , 54 , 1 , Z ),"& " 49 (BC_2 , DSR0 , input , X ) ,"& " 48 (BC_2 , CD0 , input , X ) ,"& " 47 (BC_2 , RI0 , input , X ) ,"& " 46 (BC_2 , TX1 , output3 , X , 54 , 1 , Z ),"& " 45 (BC_2 , RTS1 , output3 , X , 54 , 1 , Z ),"& " 44 (BC_2 , RX1 , input , X ) ,"& " 43 (LV_BC_7 , CTS1 , bidir , X , 82 , 1 , Z ),"& " 42 (BC_2 , DTR1 , output3 , X , 54 , 1 , Z ),"& " 41 (BC_2 , DSR1 , input , X ) ,"& " 40 (BC_2 , CD1 , input , X ) ,"& " 39 (BC_2 , RI1 , input , X ) ,"& " 38 (BC_2 , PRES , input , X ) ,"& " 37 (BC_4 , MODE , observe_only , X ) ,"& " 36 (BC_2 , * , control , 1 ) ,"& " 35 (LV_BC_7 , CLK , bidir , X , 36 , 1 , Z ),"& " 34 (LV_BC_7 , SEL , bidir , X , 36 , 1 , Z ),"& " 33 (BC_2 , * , control , 1 ) ,"& " 32 (LV_BC_7 , DB7 , bidir , X , 33 , 1 , Z ),"& " 31 (LV_BC_7 , DB6 , bidir , X , 33 , 1 , Z ),"& " 30 (LV_BC_7 , DB5 , bidir , X , 33 , 1 , Z ),"& " 29 (LV_BC_7 , DB4 , bidir , X , 33 , 1 , Z ),"& " 28 (LV_BC_7 , DB3 , bidir , X , 33 , 1 , Z ),"& " 27 (LV_BC_7 , DB2 , bidir , X , 33 , 1 , Z ),"& " 26 (LV_BC_7 , DB1 , bidir , X , 33 , 1 , Z ),"& " 25 (LV_BC_7 , DB0 , bidir , X , 33 , 1 , Z ),"& " 24 (BC_2 , * , control , 1 ) ,"& " 23 (LV_BC_7 , INT , bidir , X , 24 , 1 , Z ),"& " 22 (BC_4 , TEST1 , observe_only , X ) ,"& " 21 (BC_4 , TEST2 , observe_only , X ) ,"& " 20 (BC_2 , EN485 , input , X ) ,"& " 19 (BC_2 , ENIR , input , X ) ,"& " 18 (BC_2 , TMRCK , input , X ) ,"& " 17 (BC_2 , TX2 , output3 , X , 54 , 1 , Z ),"& " 16 (BC_2 , RX2 , input , X ) ,"& " 15 (BC_2 , RTS2 , output3 , X , 54 , 1 , Z ),"& " 14 (LV_BC_7 , CTS2 , bidir , X , 82 , 1 , Z ),"& " 13 (BC_2 , DTR2 , output3 , X , 54 , 1 , Z ),"& " 12 (BC_2 , DSR2 , input , X ) ,"& " 11 (BC_2 , CD2 , input , X ) ,"& " 10 (BC_2 , RI2 , input , X ) ,"& " 9 (BC_2 , TX4 , output3 , X , 54 , 1 , Z ),"& " 8 (BC_2 , RX4 , input , X ) ,"& " 7 (BC_2 , RTS4 , output3 , X , 54 , 1 , Z ),"& " 6 (LV_BC_7 , CTS4 , bidir , X , 82 , 1 , Z ),"& " 5 (BC_2 , DTR4 , output3 , X , 54 , 1 , Z ),"& " 4 (BC_2 , DSR4 , input , X ) ,"& " 3 (BC_2 , CD4 , input , X ) ,"& " 2 (BC_2 , RI4 , input , X ) ,"& " 1 (BC_2 , RTS5 , output3 , X , 54 , 1 , Z ),"& " 0 (LV_BC_7 , CTS5 , bidir , X , 82 , 1 , Z ) "; attribute AIO_COMPONENT_CONFORMANCE of chip: entity is "STD_1149_6_2003"; attribute AIO_EXTEST_Train_Execution of chip: entity is "train 4, maximum_time 0.001" ; attribute AIO_Pin_Behavior of chip: entity is "TXP ;"& "RXP[108] : LP_Time=2.30e-07 HP_Time=7.00e-06"; end chip;