-- ../../bsdl/eX128_cs128.bsd -- FAMILY: eX -- DEVICE: eX128 -- PACKAGE: 128 CS -- Version: 1.0 -- RESTRICT JTAG: 0 -- RESTRICT TRST: 0 -- -- This is a preliminary BSDL file which has not been verified. -- This BSDL file reflects the pre-programming JTAG -- behavior. To reflect the post-programming JTAG -- behavior, edit this file as described below: -- If the I/O is unused or configured as an output, -- the input boundary scan cell becomes internal only. -- The input buffer is turned off, and you can not -- transfer data from the I/O pad into the input scan -- cell. For example: -- IO(1) is an output, the BSDL entry would be modified -- from: -- " 0 (BC_1, IO(1), input, X), "& -- " 1 (BC_1, IO(1), output3, X, 2, 0, Z), "& -- " 2 (BC_1, *, control, 0), "& -- to: -- " 0 (BC_1, *, internal, X), "& -- " 1 (BC_1, IO(1), output3, X, 2, 0, Z), "& -- " 2 (BC_1, *, control, 0), "& -- No modification is necessary when the I/O is -- configured as an input. entity eX128cs128 is generic (PHYSICAL_PIN_MAP : string := "cs128"); port( CLKA :in bit; CLKB :in bit; GND :linkage bit_vector (0 to 13 ); HCLK :in bit; IO_A1 :out bit; IO_A4 :out bit; IO_A5 :out bit; IO_A7 :out bit; IO_A8 :out bit; IO_B2 :out bit; IO_B3 :out bit; IO_B4 :out bit; IO_B5 :out bit; IO_B6 :out bit; IO_B8 :out bit; IO_B9 :out bit; IO_C1 :out bit; IO_C3 :out bit; IO_C4 :out bit; IO_C5 :out bit; IO_C7 :out bit; IO_C8 :out bit; IO_C9 :out bit; IO_D1 :out bit; IO_D2 :out bit; IO_D3 :out bit; IO_D4 :out bit; IO_D5 :out bit; IO_D7 :out bit; IO_D9 :out bit; IO_E1 :out bit; IO_E3 :out bit; IO_F1 :out bit; IO_F2 :out bit; IO_F3 :out bit; IO_F4 :out bit; IO_G1 :out bit; IO_G2 :out bit; IO_G3 :out bit; IO_H2 :out bit; IO_H9 :out bit; IO_J2 :out bit; IO_J4 :out bit; IO_J5 :out bit; IO_J6 :out bit; IO_J8 :out bit; IO_K1 :out bit; IO_K2 :out bit; IO_K3 :out bit; IO_K4 :out bit; IO_K5 :out bit; IO_K6 :out bit; IO_K8 :out bit; IO_K9 :out bit; IO_L1 :out bit; IO_L2 :out bit; IO_L3 :out bit; IO_L4 :out bit; IO_L5 :out bit; IO_L6 :out bit; IO_L7 :out bit; IO_L8 :out bit; IO_L9 :out bit; IO_M2 :out bit; IO_M3 :out bit; IO_M4 :out bit; IO_M5 :out bit; IO_M6 :out bit; IO_M8 :out bit; IO_M9 :out bit; IO_A10 :out bit; IO_A11 :out bit; IO_A12 :out bit; IO_B10 :out bit; IO_B12 :out bit; IO_C10 :out bit; IO_C11 :out bit; IO_C12 :out bit; IO_D10 :out bit; IO_D11 :out bit; IO_E10 :out bit; IO_F10 :out bit; IO_F11 :out bit; IO_F12 :out bit; IO_G10 :out bit; IO_G11 :out bit; IO_G12 :out bit; IO_H12 :out bit; IO_J10 :out bit; IO_J11 :out bit; IO_J12 :out bit; IO_K10 :out bit; IO_K12 :out bit; IO_L10 :out bit; IO_L11 :out bit; IO_M10 :out bit; IO_M11 :out bit; IO_M12 :out bit; NC :linkage bit; TCK :in bit; TDI :in bit; TDO :out bit; TMS :in bit; VCC :linkage bit_vector (0 to 11 ) ); use STD_1149_1_1990.all; attribute PIN_MAP of eX128cs128 : entity is PHYSICAL_PIN_MAP; constant cs128 : PIN_MAP_STRING:= "CLKA :C6, "& "CLKB :B7, "& "GND :(B11, D6, D8, E11, E4, E9, F9, "& "G4, G9, H1, H4, J7, J9, M1), "& "HCLK :K7, "& "IO_A1 :A1, "& "IO_A4 :A4, "& "IO_A5 :A5, "& "IO_A7 :A7, "& "IO_A8 :A8, "& "IO_B2 :B2, "& "IO_B3 :B3, "& "IO_B4 :B4, "& "IO_B5 :B5, "& "IO_B6 :B6, "& "IO_B8 :B8, "& "IO_B9 :B9, "& "IO_C1 :C1, "& "IO_C3 :C3, "& "IO_C4 :C4, "& "IO_C5 :C5, "& "IO_C7 :C7, "& "IO_C8 :C8, "& "IO_C9 :C9, "& "IO_D1 :D1, "& "IO_D2 :D2, "& "IO_D3 :D3, "& "IO_D4 :D4, "& "IO_D5 :D5, "& "IO_D7 :D7, "& "IO_D9 :D9, "& "IO_E1 :E1, "& "IO_E3 :E3, "& "IO_F1 :F1, "& "IO_F2 :F2, "& "IO_F3 :F3, "& "IO_F4 :F4, "& "IO_G1 :G1, "& "IO_G2 :G2, "& "IO_G3 :G3, "& "IO_H2 :H2, "& "IO_H9 :H9, "& "IO_J2 :J2, "& "IO_J4 :J4, "& "IO_J5 :J5, "& "IO_J6 :J6, "& "IO_J8 :J8, "& "IO_K1 :K1, "& "IO_K2 :K2, "& "IO_K3 :K3, "& "IO_K4 :K4, "& "IO_K5 :K5, "& "IO_K6 :K6, "& "IO_K8 :K8, "& "IO_K9 :K9, "& "IO_L1 :L1, "& "IO_L2 :L2, "& "IO_L3 :L3, "& "IO_L4 :L4, "& "IO_L5 :L5, "& "IO_L6 :L6, "& "IO_L7 :L7, "& "IO_L8 :L8, "& "IO_L9 :L9, "& "IO_M2 :M2, "& "IO_M3 :M3, "& "IO_M4 :M4, "& "IO_M5 :M5, "& "IO_M6 :M6, "& "IO_M8 :M8, "& "IO_M9 :M9, "& "IO_A10 :A10, "& "IO_A11 :A11, "& "IO_A12 :A12, "& "IO_B10 :B10, "& "IO_B12 :B12, "& "IO_C10 :C10, "& "IO_C11 :C11, "& "IO_C12 :C12, "& "IO_D10 :D10, "& "IO_D11 :D11, "& "IO_E10 :E10, "& "IO_F10 :F10, "& "IO_F11 :F11, "& "IO_F12 :F12, "& "IO_G10 :G10, "& "IO_G11 :G11, "& "IO_G12 :G12, "& "IO_H12 :H12, "& "IO_J10 :J10, "& "IO_J11 :J11, "& "IO_J12 :J12, "& "IO_K10 :K10, "& "IO_K12 :K12, "& "IO_L10 :L10, "& "IO_L11 :L11, "& "IO_M10 :M10, "& "IO_M11 :M11, "& "IO_M12 :M12, "& "NC :J1, "& "TCK :A2, "& "TDI :C2, "& "TDO :K11, "& "TMS :B1, "& "VCC :(A3, A6, A9, D12, E12, E2, H10, "& "H11, H3, J3, L12, M7) "; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is ( 1.00e+007, BOTH); attribute INSTRUCTION_LENGTH of eX128cs128 : entity is 5; attribute INSTRUCTION_OPCODE of eX128cs128 : entity is "EXTEST (00000), "& "SAMPLE (00001), "& "INTEST (00010), "& "USERCODE (00011), "& "IDCODE (00100), "& "HIGHZ (01110), "& "CLAMP (01111), "& "PROBE (10000), "& "BYPASS (11111) "; attribute INSTRUCTION_CAPTURE of eX128cs128 : entity is "XXX01"; attribute INSTRUCTION_DISABLE of eX128cs128 : entity is "HIGHZ"; attribute INSTRUCTION_GUARD of eX128cs128 : entity is "CLAMP"; attribute INSTRUCTION_PRIVATE of eX128cs128 : entity is "PROBE"; attribute IDCODE_REGISTER of eX128cs128 : entity is "XXXX"& -- Version "XXXXXXXXXXXXXXXX"& -- Device "00000101111"& -- Manufacturer "1"; -- Required attribute USERCODE_REGISTER of eX128cs128 : entity is "00000000000000000000000000000000"; attribute REGISTER_ACCESS of eX128cs128 : entity is "BYPASS(HIGHZ, CLAMP)"; attribute BOUNDARY_CELLS of eX128cs128 : entity is "BC_1"; attribute BOUNDARY_LENGTH of eX128cs128 : entity is 285; attribute BOUNDARY_REGISTER of eX128cs128 : entity is -- num cell port function safe [ccell disval rslt] --BSR IO_L1 L1 " 0 (BC_1, *,internal, X), "& " 1 (BC_1, IO_L1, output3, X, 2, 0, Z), "& " 2 (BC_1, *, control, 0), "& --BSR IO_H2 H2 " 3 (BC_1, *,internal, X), "& " 4 (BC_1, IO_H2, output3, X, 5, 0, Z), "& " 5 (BC_1, *, control, 0), "& --BSR IO_K1 K1 " 6 (BC_1, *,internal, X), "& " 7 (BC_1, IO_K1, output3, X, 8, 0, Z), "& " 8 (BC_1, *, control, 0), "& --BSR IO_G1 G1 " 9 (BC_1, *,internal, X), "& " 10 (BC_1, IO_G1, output3, X, 11, 0, Z), "& " 11 (BC_1, *, control, 0), "& --BSR IO_F1 F1 " 12 (BC_1, *,internal, X), "& " 13 (BC_1, IO_F1, output3, X, 14, 0, Z), "& " 14 (BC_1, *, control, 0), "& --BSR IO_G3 G3 " 15 (BC_1, *,internal, X), "& " 16 (BC_1, IO_G3, output3, X, 17, 0, Z), "& " 17 (BC_1, *, control, 0), "& --BSR IO_G2 G2 " 18 (BC_1, *,internal, X), "& " 19 (BC_1, IO_G2, output3, X, 20, 0, Z), "& " 20 (BC_1, *, control, 0), "& --BSR IO_D1 D1 " 21 (BC_1, *,internal, X), "& " 22 (BC_1, IO_D1, output3, X, 23, 0, Z), "& " 23 (BC_1, *, control, 0), "& --BSR IO_E1 E1 " 24 (BC_1, *,internal, X), "& " 25 (BC_1, IO_E1, output3, X, 26, 0, Z), "& " 26 (BC_1, *, control, 0), "& --BSR IO_F2 F2 " 27 (BC_1, *,internal, X), "& " 28 (BC_1, IO_F2, output3, X, 29, 0, Z), "& " 29 (BC_1, *, control, 0), "& --BSR IO_F3 F3 " 30 (BC_1, *,internal, X), "& " 31 (BC_1, IO_F3, output3, X, 32, 0, Z), "& " 32 (BC_1, *, control, 0), "& --BSR IO_F4 F4 " 33 (BC_1, *,internal, X), "& " 34 (BC_1, IO_F4, output3, X, 35, 0, Z), "& " 35 (BC_1, *, control, 0), "& --BSR IO_C1 C1 " 36 (BC_1, *,internal, X), "& " 37 (BC_1, IO_C1, output3, X, 38, 0, Z), "& " 38 (BC_1, *, control, 0), "& --BSR IO_A1 A1 " 39 (BC_1, *,internal, X), "& " 40 (BC_1, IO_A1, output3, X, 41, 0, Z), "& " 41 (BC_1, *, control, 0), "& --BSR IO_B2 B2 " 42 (BC_1, *,internal, X), "& " 43 (BC_1, IO_B2, output3, X, 44, 0, Z), "& " 44 (BC_1, *, control, 0), "& --BSR IO_D2 D2 " 45 (BC_1, *,internal, X), "& " 46 (BC_1, IO_D2, output3, X, 47, 0, Z), "& " 47 (BC_1, *, control, 0), "& --BSR IO_B3 B3 " 48 (BC_1, *,internal, X), "& " 49 (BC_1, IO_B3, output3, X, 50, 0, Z), "& " 50 (BC_1, *, control, 0), "& --BSR IO_C3 C3 " 51 (BC_1, *,internal, X), "& " 52 (BC_1, IO_C3, output3, X, 53, 0, Z), "& " 53 (BC_1, *, control, 0), "& --BSR IO_B4 B4 " 54 (BC_1, *,internal, X), "& " 55 (BC_1, IO_B4, output3, X, 56, 0, Z), "& " 56 (BC_1, *, control, 0), "& --BSR IO_C4 C4 " 57 (BC_1, *,internal, X), "& " 58 (BC_1, IO_C4, output3, X, 59, 0, Z), "& " 59 (BC_1, *, control, 0), "& --BSR IO_A4 A4 " 60 (BC_1, *,internal, X), "& " 61 (BC_1, IO_A4, output3, X, 62, 0, Z), "& " 62 (BC_1, *, control, 0), "& --BSR IO_E3 E3 " 63 (BC_1, *,internal, X), "& " 64 (BC_1, IO_E3, output3, X, 65, 0, Z), "& " 65 (BC_1, *, control, 0), "& --BSR IO_B5 B5 " 66 (BC_1, *,internal, X), "& " 67 (BC_1, IO_B5, output3, X, 68, 0, Z), "& " 68 (BC_1, *, control, 0), "& --BSR IO_D3 D3 " 69 (BC_1, *,internal, X), "& " 70 (BC_1, IO_D3, output3, X, 71, 0, Z), "& " 71 (BC_1, *, control, 0), "& --BSR IO_D4 D4 " 72 (BC_1, *,internal, X), "& " 73 (BC_1, IO_D4, output3, X, 74, 0, Z), "& " 74 (BC_1, *, control, 0), "& --BSR IO_D5 D5 " 75 (BC_1, *,internal, X), "& " 76 (BC_1, IO_D5, output3, X, 77, 0, Z), "& " 77 (BC_1, *, control, 0), "& --BSR IO_A5 A5 " 78 (BC_1, *,internal, X), "& " 79 (BC_1, IO_A5, output3, X, 80, 0, Z), "& " 80 (BC_1, *, control, 0), "& --BSR IO_B6 B6 " 81 (BC_1, *,internal, X), "& " 82 (BC_1, IO_B6, output3, X, 83, 0, Z), "& " 83 (BC_1, *, control, 0), "& --BSR IO_C5 C5 " 84 (BC_1, *,internal, X), "& " 85 (BC_1, IO_C5, output3, X, 86, 0, Z), "& " 86 (BC_1, *, control, 0), "& --BSR CLKB B7 " 87 (BC_1, CLKB, input, X), "& --BSR CLKA C6 " 88 (BC_1, CLKA, input, X), "& --BSR IO_D7 D7 " 89 (BC_1, *,internal, X), "& " 90 (BC_1, IO_D7, output3, X, 91, 0, Z), "& " 91 (BC_1, *, control, 0), "& --BSR IO_A7 A7 " 92 (BC_1, *,internal, X), "& " 93 (BC_1, IO_A7, output3, X, 94, 0, Z), "& " 94 (BC_1, *, control, 0), "& --BSR IO_C7 C7 " 95 (BC_1, *,internal, X), "& " 96 (BC_1, IO_C7, output3, X, 97, 0, Z), "& " 97 (BC_1, *, control, 0), "& --BSR IO_A8 A8 " 98 (BC_1, *,internal, X), "& " 99 (BC_1, IO_A8, output3, X, 100, 0, Z), "& " 100 (BC_1, *, control, 0), "& --BSR IO_C8 C8 " 101 (BC_1, *,internal, X), "& " 102 (BC_1, IO_C8, output3, X, 103, 0, Z), "& " 103 (BC_1, *, control, 0), "& --BSR IO_B8 B8 " 104 (BC_1, *,internal, X), "& " 105 (BC_1, IO_B8, output3, X, 106, 0, Z), "& " 106 (BC_1, *, control, 0), "& --BSR IO_D9 D9 " 107 (BC_1, *,internal, X), "& " 108 (BC_1, IO_D9, output3, X, 109, 0, Z), "& " 109 (BC_1, *, control, 0), "& --BSR IO_C9 C9 " 110 (BC_1, *,internal, X), "& " 111 (BC_1, IO_C9, output3, X, 112, 0, Z), "& " 112 (BC_1, *, control, 0), "& --BSR IO_E10 E10 " 113 (BC_1, *,internal, X), "& " 114 (BC_1, IO_E10, output3, X, 115, 0, Z), "& " 115 (BC_1, *, control, 0), "& --BSR IO_D10 D10 " 116 (BC_1, *,internal, X), "& " 117 (BC_1, IO_D10, output3, X, 118, 0, Z), "& " 118 (BC_1, *, control, 0), "& --BSR IO_D11 D11 " 119 (BC_1, *,internal, X), "& " 120 (BC_1, IO_D11, output3, X, 121, 0, Z), "& " 121 (BC_1, *, control, 0), "& --BSR IO_A10 A10 " 122 (BC_1, *,internal, X), "& " 123 (BC_1, IO_A10, output3, X, 124, 0, Z), "& " 124 (BC_1, *, control, 0), "& --BSR IO_B9 B9 " 125 (BC_1, *,internal, X), "& " 126 (BC_1, IO_B9, output3, X, 127, 0, Z), "& " 127 (BC_1, *, control, 0), "& --BSR IO_B10 B10 " 128 (BC_1, *,internal, X), "& " 129 (BC_1, IO_B10, output3, X, 130, 0, Z), "& " 130 (BC_1, *, control, 0), "& --BSR IO_C10 C10 " 131 (BC_1, *,internal, X), "& " 132 (BC_1, IO_C10, output3, X, 133, 0, Z), "& " 133 (BC_1, *, control, 0), "& --BSR IO_A11 A11 " 134 (BC_1, *,internal, X), "& " 135 (BC_1, IO_A11, output3, X, 136, 0, Z), "& " 136 (BC_1, *, control, 0), "& --BSR IO_A12 A12 " 137 (BC_1, *,internal, X), "& " 138 (BC_1, IO_A12, output3, X, 139, 0, Z), "& " 139 (BC_1, *, control, 0), "& --BSR IO_C11 C11 " 140 (BC_1, *,internal, X), "& " 141 (BC_1, IO_C11, output3, X, 142, 0, Z), "& " 142 (BC_1, *, control, 0), "& --BSR IO_B12 B12 " 143 (BC_1, *,internal, X), "& " 144 (BC_1, IO_B12, output3, X, 145, 0, Z), "& " 145 (BC_1, *, control, 0), "& --BSR IO_C12 C12 " 146 (BC_1, *,internal, X), "& " 147 (BC_1, IO_C12, output3, X, 148, 0, Z), "& " 148 (BC_1, *, control, 0), "& --BSR IO_G12 G12 " 149 (BC_1, *,internal, X), "& " 150 (BC_1, IO_G12, output3, X, 151, 0, Z), "& " 151 (BC_1, *, control, 0), "& --BSR IO_F10 F10 " 152 (BC_1, *,internal, X), "& " 153 (BC_1, IO_F10, output3, X, 154, 0, Z), "& " 154 (BC_1, *, control, 0), "& --BSR IO_F12 F12 " 155 (BC_1, *,internal, X), "& " 156 (BC_1, IO_F12, output3, X, 157, 0, Z), "& " 157 (BC_1, *, control, 0), "& --BSR IO_F11 F11 " 158 (BC_1, *,internal, X), "& " 159 (BC_1, IO_F11, output3, X, 160, 0, Z), "& " 160 (BC_1, *, control, 0), "& --BSR IO_H12 H12 " 161 (BC_1, *,internal, X), "& " 162 (BC_1, IO_H12, output3, X, 163, 0, Z), "& " 163 (BC_1, *, control, 0), "& --BSR IO_G10 G10 " 164 (BC_1, *,internal, X), "& " 165 (BC_1, IO_G10, output3, X, 166, 0, Z), "& " 166 (BC_1, *, control, 0), "& --BSR IO_J12 J12 " 167 (BC_1, *,internal, X), "& " 168 (BC_1, IO_J12, output3, X, 169, 0, Z), "& " 169 (BC_1, *, control, 0), "& --BSR IO_G11 G11 " 170 (BC_1, *,internal, X), "& " 171 (BC_1, IO_G11, output3, X, 172, 0, Z), "& " 172 (BC_1, *, control, 0), "& --BSR IO_K12 K12 " 173 (BC_1, *,internal, X), "& " 174 (BC_1, IO_K12, output3, X, 175, 0, Z), "& " 175 (BC_1, *, control, 0), "& --BSR IO_J11 J11 " 176 (BC_1, *,internal, X), "& " 177 (BC_1, IO_J11, output3, X, 178, 0, Z), "& " 178 (BC_1, *, control, 0), "& --BSR IO_M12 M12 " 179 (BC_1, *,internal, X), "& " 180 (BC_1, IO_M12, output3, X, 181, 0, Z), "& " 181 (BC_1, *, control, 0), "& --BSR IO_L11 L11 " 182 (BC_1, *,internal, X), "& " 183 (BC_1, IO_L11, output3, X, 184, 0, Z), "& " 184 (BC_1, *, control, 0), "& --BSR IO_J10 J10 " 185 (BC_1, *,internal, X), "& " 186 (BC_1, IO_J10, output3, X, 187, 0, Z), "& " 187 (BC_1, *, control, 0), "& --BSR IO_K10 K10 " 188 (BC_1, *,internal, X), "& " 189 (BC_1, IO_K10, output3, X, 190, 0, Z), "& " 190 (BC_1, *, control, 0), "& --BSR IO_M11 M11 " 191 (BC_1, *,internal, X), "& " 192 (BC_1, IO_M11, output3, X, 193, 0, Z), "& " 193 (BC_1, *, control, 0), "& --BSR IO_H9 H9 " 194 (BC_1, *,internal, X), "& " 195 (BC_1, IO_H9, output3, X, 196, 0, Z), "& " 196 (BC_1, *, control, 0), "& --BSR IO_L10 L10 " 197 (BC_1, *,internal, X), "& " 198 (BC_1, IO_L10, output3, X, 199, 0, Z), "& " 199 (BC_1, *, control, 0), "& --BSR IO_L9 L9 " 200 (BC_1, *,internal, X), "& " 201 (BC_1, IO_L9, output3, X, 202, 0, Z), "& " 202 (BC_1, *, control, 0), "& --BSR IO_M10 M10 " 203 (BC_1, *,internal, X), "& " 204 (BC_1, IO_M10, output3, X, 205, 0, Z), "& " 205 (BC_1, *, control, 0), "& --BSR IO_K9 K9 " 206 (BC_1, *,internal, X), "& " 207 (BC_1, IO_K9, output3, X, 208, 0, Z), "& " 208 (BC_1, *, control, 0), "& --BSR IO_M9 M9 " 209 (BC_1, *,internal, X), "& " 210 (BC_1, IO_M9, output3, X, 211, 0, Z), "& " 211 (BC_1, *, control, 0), "& --BSR IO_L8 L8 " 212 (BC_1, *,internal, X), "& " 213 (BC_1, IO_L8, output3, X, 214, 0, Z), "& " 214 (BC_1, *, control, 0), "& --BSR IO_M8 M8 " 215 (BC_1, *,internal, X), "& " 216 (BC_1, IO_M8, output3, X, 217, 0, Z), "& " 217 (BC_1, *, control, 0), "& --BSR IO_K8 K8 " 218 (BC_1, *,internal, X), "& " 219 (BC_1, IO_K8, output3, X, 220, 0, Z), "& " 220 (BC_1, *, control, 0), "& --BSR IO_L7 L7 " 221 (BC_1, *,internal, X), "& " 222 (BC_1, IO_L7, output3, X, 223, 0, Z), "& " 223 (BC_1, *, control, 0), "& --BSR IO_J8 J8 " 224 (BC_1, *,internal, X), "& " 225 (BC_1, IO_J8, output3, X, 226, 0, Z), "& " 226 (BC_1, *, control, 0), "& --BSR HCLK K7 " 227 (BC_1, HCLK, input, X), "& --BSR IO_L6 L6 " 228 (BC_1, *,internal, X), "& " 229 (BC_1, IO_L6, output3, X, 230, 0, Z), "& " 230 (BC_1, *, control, 0), "& --BSR IO_J6 J6 " 231 (BC_1, *,internal, X), "& " 232 (BC_1, IO_J6, output3, X, 233, 0, Z), "& " 233 (BC_1, *, control, 0), "& --BSR IO_K6 K6 " 234 (BC_1, *,internal, X), "& " 235 (BC_1, IO_K6, output3, X, 236, 0, Z), "& " 236 (BC_1, *, control, 0), "& --BSR IO_M6 M6 " 237 (BC_1, *,internal, X), "& " 238 (BC_1, IO_M6, output3, X, 239, 0, Z), "& " 239 (BC_1, *, control, 0), "& --BSR IO_L5 L5 " 240 (BC_1, *,internal, X), "& " 241 (BC_1, IO_L5, output3, X, 242, 0, Z), "& " 242 (BC_1, *, control, 0), "& --BSR IO_M5 M5 " 243 (BC_1, *,internal, X), "& " 244 (BC_1, IO_M5, output3, X, 245, 0, Z), "& " 245 (BC_1, *, control, 0), "& --BSR IO_K5 K5 " 246 (BC_1, *,internal, X), "& " 247 (BC_1, IO_K5, output3, X, 248, 0, Z), "& " 248 (BC_1, *, control, 0), "& --BSR IO_J5 J5 " 249 (BC_1, *,internal, X), "& " 250 (BC_1, IO_J5, output3, X, 251, 0, Z), "& " 251 (BC_1, *, control, 0), "& --BSR IO_K4 K4 " 252 (BC_1, *,internal, X), "& " 253 (BC_1, IO_K4, output3, X, 254, 0, Z), "& " 254 (BC_1, *, control, 0), "& --BSR IO_M4 M4 " 255 (BC_1, *,internal, X), "& " 256 (BC_1, IO_M4, output3, X, 257, 0, Z), "& " 257 (BC_1, *, control, 0), "& --BSR IO_J4 J4 " 258 (BC_1, *,internal, X), "& " 259 (BC_1, IO_J4, output3, X, 260, 0, Z), "& " 260 (BC_1, *, control, 0), "& --BSR IO_L4 L4 " 261 (BC_1, *,internal, X), "& " 262 (BC_1, IO_L4, output3, X, 263, 0, Z), "& " 263 (BC_1, *, control, 0), "& --BSR IO_K3 K3 " 264 (BC_1, *,internal, X), "& " 265 (BC_1, IO_K3, output3, X, 266, 0, Z), "& " 266 (BC_1, *, control, 0), "& --BSR IO_M3 M3 " 267 (BC_1, *,internal, X), "& " 268 (BC_1, IO_M3, output3, X, 269, 0, Z), "& " 269 (BC_1, *, control, 0), "& --BSR IO_J2 J2 " 270 (BC_1, *,internal, X), "& " 271 (BC_1, IO_J2, output3, X, 272, 0, Z), "& " 272 (BC_1, *, control, 0), "& --BSR IO_L3 L3 " 273 (BC_1, *,internal, X), "& " 274 (BC_1, IO_L3, output3, X, 275, 0, Z), "& " 275 (BC_1, *, control, 0), "& --BSR IO_K2 K2 " 276 (BC_1, *,internal, X), "& " 277 (BC_1, IO_K2, output3, X, 278, 0, Z), "& " 278 (BC_1, *, control, 0), "& --BSR IO_M2 M2 " 279 (BC_1, *,internal, X), "& " 280 (BC_1, IO_M2, output3, X, 281, 0, Z), "& " 281 (BC_1, *, control, 0), "& --BSR IO_L2 L2 " 282 (BC_1, *,internal, X), "& " 283 (BC_1, IO_L2, output3, X, 284, 0, Z), "& " 284 (BC_1, *, control, 0) "; end eX128cs128;