--******************************************************************************************************* --** Copyright (c) 2000 Cypress Semiconductor --** All rights reserved. --** --** File Name: cy7c1361a.bsdl --** Release: 1.0 --** Last Updated: March 29, 2001 --** --** Function: 256x36 Sync F/T SRAM, BSDL file for JTAG --** Part #: CY7C1361A/GVT7125BD36 --** --** Notes: IMPORTANT NOTE: Please be aware that the CY7C1361A device is NOT IEEE --** 1149.1 compliant. --** Ref CY7C1361A/GVT71256B36 Datasheet at www.cypress.com/sram/datasheets.html --** --** Queries ?: Contact MPD Applications at 408-943-2891 or e-mail: mpd_apps@cypress.com --******************************************************************************************************* entity CY7C1361A is generic (PHYSICAL_PIN_MAP : string := "BGA"); port ( A: in bit_vector(0 to 17); ADSP_b: in bit; ADSC_b: in bit; ADV_b: in bit; BWS_A_b: in bit; BWS_B_b: in bit; BWS_C_b: in bit; BWS_D_b: in bit; BWE_b: in bit; CE_b: in bit; CE2: in bit; CLK: in bit; DQ_A: in bit_vector(0 to 8); DQ_B: in bit_vector(0 to 8); DQ_C: in bit_vector(0 to 8); DQ_D: in bit_vector(0 to 8); GW_b: in bit; OE_b: in bit; MODE: in bit; TMS: in bit; TDI: in bit; TCK: in bit; TDO: out bit; ZZ: linkage bit; VCC: linkage bit_vector(0 to 4); VSS: linkage bit_vector(0 to 15); VCCQ: linkage bit_vector(0 to 9); NC: linkage bit_vector(0 to 14) ); use STD_1149_1_1994.all; attribute PIN_MAP of CY7C1361A : entity is PHYSICAL_PIN_MAP; constant BGA:PIN_MAP_STRING:= "A: (P4,N4,A2,A3,A5,A6,B3,B5,B6,C2,C3,C5,C6, " & " R2,R6,T3,T4,T5), " & -- Address "ADSP_b: A4, " & "ADSC_b: B4, " & "ADV_b: G4, " & "BWS_A_b: L5, " & "BWS_B_b: G5, " & "BWS_C_b: G3, " & "BWS_D_b: L3, " & -- Byte Write "BWE_b: M4, " & -- Write Enable "CE_b: E4, " & "CE2: B2, " & "CLK: K4, " & -- Clock "DQ_A: (K6,K7,L6,L7,M6,N6,N7,P6,P7), " & "DQ_B: (D6,D7,E6,E7,F6,G6,G7,H6,H7), " & "DQ_C: (D1,D2,E1,E2,F2,G1,G2,H1,H2), " & "DQ_D: (K1,K2,L1,L2,M2,N1,N2,P1,P2), " & "GW_b: H4, " & "OE_b: F4, " & "MODE: R3, " & "TMS: U2, " & "TDI: U3, " & "TCK: U4, " & "TDO: U5, " & "VCC: (C4,J2,J4,J6,R4), " & "VCCQ: (A1,A7,F1,F7,J1,J7,M1,M7,U1,U7), " & "VSS: (D3,D5,E3,E5,F3,F5,H3,H5,K3,K5, " & " M3,M5,N3,N5,P3,P5), " & "ZZ: T7, " & "NC: (B1,B7,C1,C7,D4,J3,J5,L4,R1,R5,R7,T1,T2,T6,U6) "; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (50.0e6, BOTH); attribute INSTRUCTION_LENGTH of CY7C1361A : entity is 3; attribute INSTRUCTION_OPCODE of CY7C1361A : entity is "EXTEST (000)," & "IDCODE (001)," & "SAMPLE (010)," & -- Sample-Z "SAMPLD (100)," & -- Sample/Preload "BYPASS (111) "; attribute INSTRUCTION_CAPTURE of CY7C1361A: entity is "001"; attribute IDCODE_REGISTER of CY7C1361A : entity is "XXXX" & -- Reserved for version number "00110" & -- Defines the depth of the device "00100" & -- Defines the width of the device "XXXXXX" & -- Reserved for future use "00011100100" & -- Manufacturer identity "1"; -- ID register Presence indicator attribute REGISTER_ACCESS of CY7C1361A : entity is "BOUNDARY (EXTEST,SAMPLE,SAMPLD)," & "BYPASS (BYPASS)"; attribute BOUNDARY_LENGTH of CY7C1361A : entity is 70; attribute BOUNDARY_REGISTER of CY7C1361A : entity is "0 (BC_4, A(13), input, X)," & "1 (BC_4, A(15), input, X)," & "2 (BC_4, A(16), input, X)," & "3 (BC_4, A(17), input, X)," & "4 (BC_4, A(14), input, X)," & "5 (BC_4, A(6), input, X)," & "6 (BC_4, A(7), input, X)," & "7 (BC_4, DQ_A(7), input, X)," & "8 (BC_4, DQ_A(6), input, X)," & "9 (BC_4, DQ_A(4), input, X)," & "10 (BC_4, DQ_A(3), input, X)," & "11 (BC_4, DQ_A(0), input, X)," & "12 (BC_4, DQ_A(8), input, X)," & "13 (BC_4, DQ_A(5), input, X)," & "14 (BC_4, DQ_A(2), input, X)," & "15 (BC_4, DQ_A(1), input, X)," & "16 (BC_4, *, internal, X)," & "17 (BC_4, DQ_B(7), input, X)," & "18 (BC_4, DQ_B(6), input, X)," & "19 (BC_4, DQ_B(4), input, X)," & "20 (BC_4, DQ_B(3), input, X)," & "21 (BC_4, DQ_B(0), input, X)," & "22 (BC_4, DQ_B(8), input, X)," & "23 (BC_4, DQ_B(5), input, X)," & "24 (BC_4, DQ_B(2), input, X)," & "25 (BC_4, DQ_B(1), input, X)," & "26 (BC_4, A(5), input, X)," & "27 (BC_4, A(4), input, X)," & "28 (BC_4, ADV_b, input, X)," & "29 (BC_4, ADSP_b, input, X)," & "30 (BC_4, ADSC_b, input, X)," & "31 (BC_4, OE_b, input, X)," & "32 (BC_4, BWE_b, input, X)," & "33 (BC_4, GW_b, input, X)," & "34 (BC_4, CLK, input, X)," & "35 (BC_4, A(8), input, X)," & "36 (BC_4, BWS_A_b, input, X)," & "37 (BC_4, BWS_B_b, input, X)," & "38 (BC_4, BWS_C_b, input, X)," & "39 (BC_4, BWS_D_b, input, X)," & "40 (BC_4, CE2, input, X)," & "41 (BC_4, CE_b, input, X)," & "42 (BC_4, A(3), input, X)," & "43 (BC_4, A(2), input, X)," & "44 (BC_4, DQ_C(1), input, X)," & "45 (BC_4, DQ_C(2), input, X)," & "46 (BC_4, DQ_C(4), input, X)," & "47 (BC_4, DQ_C(5), input, X)," & "48 (BC_4, DQ_C(8), input, X)," & "49 (BC_4, DQ_C(0), input, X)," & "50 (BC_4, DQ_C(3), input, X)," & "51 (BC_4, DQ_C(6), input, X)," & "52 (BC_4, DQ_C(7), input, X)," & "53 (BC_4, *, internal, X)," & "54 (BC_4, DQ_D(1), input, X)," & "55 (BC_4, DQ_D(2), input, X)," & "56 (BC_4, DQ_D(4), input, X)," & "57 (BC_4, DQ_D(5), input, X)," & "58 (BC_4, DQ_D(8), input, X)," & "59 (BC_4, DQ_D(0), input, X)," & "60 (BC_4, DQ_D(3), input, X)," & "61 (BC_4, DQ_D(6), input, X)," & "62 (BC_4, DQ_D(7), input, X)," & "63 (BC_4, MODE, input, X)," & "64 (BC_4, A(9), input, X)," & "65 (BC_4, A(10), input, X)," & "66 (BC_4, A(11), input, X)," & "67 (BC_4, A(12), input, X)," & "68 (BC_4, A(1), input, X)," & "69 (BC_4, A(0), input, X)"; end CY7C1361A;