-- --------------------------------------------------------------------------- -- Copyright Message -- --------------------------------------------------------------------------- -- -- NXP Semiconductors confidential and proprietary. -- COPYRIGHT 2008 by NXP Semiconductors N.V. -- -- All rights are reserved. Reproduction in whole or in part is -- prohibited without the written consent of the copyright owner. -- -- --------------------------------------------------------------------------- -- Design Information -- --------------------------------------------------------------------------- -- -- File : $RCSfile: LPC3180FEL320_01_REVDASH_2008_11_04.BSDL.rca $ -- -- Author : $Author: usb10152 $ -- -- Description : LPC3180/01 BSDL -- -- --------------------------------------------------------------------------- -- $Id: LPC3180FEL320_01_REVDASH_2008_11_04.BSDL.rca 1.1 Wed Nov 5 08:17:29 2008 usb10152 Experimental $ -- $Source: /home/usb10152/bsdl/LPC3180FEL320_01_REVDASH_2008_11_04.BSDL.rca $ -- --------------------------------------------------------------------------- -- ------------------------------------------------------------------------------- -- Job Status: Pass -- -- File Name: LPC3180FEL320_01_REVDASH_2008_11_04.BSDL -- Timestamp: Wednesday, November 05, 2008 10:24 AM -- -- Results: Entity name: LPC3180FEL320_01 -- IEEE Std 1149.1-2001 (Version 2.0) -- Packaging option selected is LFBGA320. -- Inputs = 1 -- Outputs = 0 -- Bidirectionals = 173 -- Instruction Reg Length = 4 -- Boundary Reg Length = 403 -- -- BSDL compilation of 1055 lines completed without errors. ------------------------------------------------------------------------------- -- use work.std_1149_1_2001.all; entity LPC3180FEL320_01 is -- -- This section identifies the default device package selected. -- generic (PHYSICAL_PIN_MAP : string := "LFBGA320"); -- -- This section declares all the ports in the design. -- port (JTAG1_TCK : in bit; JTAG1_TDI : in bit; JTAG1_TDO : out bit; JTAG1_TMS : in bit; JTAG1_NTRST : in bit; I2C1_SDA : inout bit; I2C1_SCL : inout bit; I2C2_SCL : inout bit; I2C2_SDA : inout bit; USB_I2C_SDA : inout bit; USB_I2C_SCL : inout bit; SYSX_IN : linkage bit; SYSX_OUT : linkage bit; RTCX_IN : linkage bit; RTCX_OUT : linkage bit; PLL397_LOOP : linkage bit; ADIN0 : linkage bit; ADIN1 : linkage bit; ADIN2 : linkage bit; RAM_D31_PIO_SD12 : inout bit; RAM_D30_PIO_SD11 : inout bit; RAM_D29_PIO_SD10 : inout bit; RAM_D28_PIO_SD9 : inout bit; RAM_D27_PIO_SD8 : inout bit; RAM_D26_PIO_SD7 : inout bit; RAM_D25_PIO_SD6 : inout bit; RAM_D24_PIO_SD5 : inout bit; RAM_D23_PIO_SD4 : inout bit; RAM_D22_PIO_SD3 : inout bit; RAM_D21_PIO_SD2 : inout bit; RAM_D20_PIO_SD1 : inout bit; RAM_D19_PIO_SD0 : inout bit; RAM_D18_DDR_NCLK : inout bit; RAM_D17_DDR_DQS1 : inout bit; RAM_D16_DDR_DQS0 : inout bit; RAM_D15 : inout bit; RAM_D14 : inout bit; RAM_D13 : inout bit; RAM_D12 : inout bit; RAM_D11 : inout bit; RAM_D10 : inout bit; RAM_D9 : inout bit; RAM_D8 : inout bit; RAM_D7 : inout bit; RAM_D6 : inout bit; RAM_D5 : inout bit; RAM_D4 : inout bit; RAM_D3 : inout bit; RAM_D2 : inout bit; RAM_D1 : inout bit; RAM_D0 : inout bit; RAM_A14 : inout bit; RAM_A13 : inout bit; RAM_A12 : inout bit; RAM_A11 : inout bit; RAM_A10 : inout bit; RAM_A9 : inout bit; RAM_A8 : inout bit; RAM_A7 : inout bit; RAM_A6 : inout bit; RAM_A5 : inout bit; RAM_A4 : inout bit; RAM_A3 : inout bit; RAM_A2 : inout bit; RAM_A1 : inout bit; RAM_A0 : inout bit; RAM_CLK : inout bit; RAM_CLKIN : inout bit; RAM_CKE : inout bit; RAM_CS_N : inout bit; RAM_RAS_N : inout bit; RAM_CAS_N : inout bit; RAM_WR_N : inout bit; RAM_DQM3 : inout bit; RAM_DQM2 : inout bit; RAM_DQM1 : inout bit; RAM_DQM0 : inout bit; VSS0 : inout bit; VSS1 : inout bit; VSS2 : inout bit; SYSCLKEN : inout bit; RESOUT_N : inout bit; ONSW : inout bit; HIGHCORE : inout bit; TEST : in bit; TEST_CLK2 : inout bit; USB_ATX_INT_N : inout bit; USB_OE_TP_N : inout bit; USB_DAT_VP_U5_RX : inout bit; USB_SE0_VM_U5_TX : inout bit; FLASH_IO7 : inout bit; FLASH_IO6 : inout bit; FLASH_IO5 : inout bit; FLASH_IO4 : inout bit; FLASH_IO3 : inout bit; FLASH_IO2 : inout bit; FLASH_IO1 : inout bit; FLASH_IO0 : inout bit; FLASH_ALE : inout bit; FLASH_CE_N : inout bit; FLASH_WR_N : inout bit; FLASH_RD_N : inout bit; FLASH_CLE : inout bit; FLASH_RDY : inout bit; MS_SCLK : inout bit; MS_BS : inout bit; MS_DIO0 : inout bit; MS_DIO1 : inout bit; MS_DIO2 : inout bit; MS_DIO3 : inout bit; GPI11 : inout bit; GPI10_U4_RX : inout bit; GPI09_KEY_COL7 : inout bit; GPI08_KEY_COL6_SPI2_BUSY : inout bit; GPI07 : inout bit; GPI06_HSTIM_CAP : inout bit; GPI05 : inout bit; GPI04_SPI1_BUSY : inout bit; GPI03 : inout bit; GPI02 : inout bit; GPI01_SERVICE_N : inout bit; GPI00 : inout bit; GPO23_U2_HRTS : inout bit; GPO22_U7_HRTS : inout bit; GPO21_U4_TX : inout bit; GPO20 : inout bit; GPO19 : inout bit; GPO18 : inout bit; GPO17 : inout bit; GPO16 : inout bit; GPO15 : inout bit; GPO14 : inout bit; GPO13 : inout bit; GPO12 : inout bit; GPO11 : inout bit; GPO10 : inout bit; GPO09 : inout bit; GPO08 : inout bit; GPO07 : inout bit; GPO06 : inout bit; GPO05 : inout bit; GPO04 : inout bit; GPO03 : inout bit; GPO02 : inout bit; GPO01 : inout bit; GPO00_TST_CLK1 : inout bit; GPIO05 : inout bit; GPIO04 : inout bit; GPIO03_KEY_ROW7 : inout bit; GPIO02_KEY_ROW6 : inout bit; GPIO01 : inout bit; GPIO00 : inout bit; JTAG1_RTCK : inout bit; U1_TX : inout bit; U1_RX_PIO_INP15 : inout bit; U2_TX : inout bit; U2_RX_PIO_INP17 : inout bit; U2_HCTS_PIO_INP16 : inout bit; U3_TX : inout bit; U3_RX_PIO_INP18 : inout bit; U5_TX : inout bit; U5_RX_PIO_INP20 : inout bit; U6_IRTX : inout bit; U6_IRRX_PIO_INP21 : inout bit; U7_TX : inout bit; U7_RX_PIO_INP23 : inout bit; U7_HCTS_PIO_INP22 : inout bit; KEY_ROW5 : inout bit; KEY_ROW4 : inout bit; KEY_ROW3 : inout bit; KEY_ROW2 : inout bit; KEY_ROW1 : inout bit; KEY_ROW0 : inout bit; KEY_COL5 : inout bit; KEY_COL4 : inout bit; KEY_COL3 : inout bit; KEY_COL2 : inout bit; KEY_COL1 : inout bit; KEY_COL0 : inout bit; PWM_OUT1 : inout bit; PWM_OUT2 : inout bit; SPI1_CLK : inout bit; SPI1_DATIO : inout bit; SPI1_DATIN : inout bit; SPI2_CLK : inout bit; SPI2_DATIO : inout bit; SPI2_DATIN : inout bit; RESET_N : in bit; VDD12 : linkage bit; VDD_AD28 : linkage bit_vector(1 to 2); VDD_CORE12_01 : linkage bit; VDD_CORE12_02 : linkage bit; VDD_CORE12_03 : linkage bit; VDD_CORE12_05 : linkage bit; VDD_CORE12_06 : linkage bit; VDD_CORE12_07 : linkage bit; VDD_CORE12_08 : linkage bit; VDD_COREFXD12_01 : linkage bit; VDD_COREFXD12_02 : linkage bit; VDD_IOA : linkage bit_vector(1 to 2); VDD_IOB : linkage bit; VDD_IOC : linkage bit_vector(1 to 4); VDD_IOD : linkage bit_vector(1 to 2); VDD_OSC12 : linkage bit; VDD_PLL397_12 : linkage bit; VDD_PLLHCLK_12 : linkage bit; VDD_PLLUSB_12 : linkage bit; VDD_RTC12 : linkage bit; VDD_RTCCORE12 : linkage bit; VDD_RTCOSC12 : linkage bit; VDD_RAM : linkage bit_vector(1 to 9); VSS_AD : linkage bit; VSS_CORE_01 : linkage bit; VSS_CORE_02 : linkage bit; VSS_CORE_03 : linkage bit; VSS_CORE_04 : linkage bit; VSS_CORE_05 : linkage bit; VSS_CORE_06 : linkage bit; VSS_CORE_07 : linkage bit; VSS_CORE_08 : linkage bit; VSS_CORE_09 : linkage bit; VSS_IOA : linkage bit; VSS_IOB : linkage bit; VSS_IOC : linkage bit_vector(1 to 3); VSS_IOD : linkage bit_vector(1 to 4); VSS_OSC : linkage bit; VSS_PLL397 : linkage bit; VSS_PLLHCLK : linkage bit; VSS_PLLUSB : linkage bit; VSS_RTCCORE : linkage bit; VSS_RTCOSC : linkage bit; VSS_RAM : linkage bit_vector(1 to 11); NC : linkage bit_vector(1 to 59) ); use std_1149_1_2001.all; attribute COMPONENT_CONFORMANCE of LPC3180FEL320_01 : entity is "std_1149_1_2001"; attribute PIN_MAP of LPC3180FEL320_01 : entity is PHYSICAL_PIN_MAP; -- -- This section specifies the pin map for each port. -- constant LFBGA320 : PIN_MAP_STRING := "JTAG1_TCK : B5, " & "JTAG1_TDI : B6, " & "JTAG1_TDO : A4, " & "JTAG1_TMS : A5, " & "JTAG1_NTRST : D7, " & "I2C1_SDA : AC1, " & "I2C1_SCL : Y4, " & "I2C2_SCL : AD8, " & "I2C2_SDA : AA9, " & "USB_I2C_SDA : AD7, " & "USB_I2C_SCL : AC8, " & "SYSX_IN : A23, " & "SYSX_OUT : B23, " & "RTCX_IN : A14, " & "RTCX_OUT : A13, " & "PLL397_LOOP : C21, " & "ADIN0 : C24, " & "ADIN1 : E22, " & "ADIN2 : D23, " & "RAM_D31_PIO_SD12 : E24, " & "RAM_D30_PIO_SD11 : E23, " & "RAM_D29_PIO_SD10 : F21, " & "RAM_D28_PIO_SD9 : F24, " & "RAM_D27_PIO_SD8 : G24, " & "RAM_D26_PIO_SD7 : H23, " & "RAM_D25_PIO_SD6 : J21, " & "RAM_D24_PIO_SD5 : G23, " & "RAM_D23_PIO_SD4 : H22, " & "RAM_D22_PIO_SD3 : K23, " & "RAM_D21_PIO_SD2 : H24, " & "RAM_D20_PIO_SD1 : J24, " & "RAM_D19_PIO_SD0 : H21, " & "RAM_D18_DDR_NCLK : K24, " & "RAM_D17_DDR_DQS1 : L21, " & "RAM_D16_DDR_DQS0 : L23, " & "RAM_D15 : L24, " & "RAM_D14 : M23, " & "RAM_D13 : L22, " & "RAM_D12 : M24, " & "RAM_D11 : N23, " & "RAM_D10 : M22, " & "RAM_D9 : N24, " & "RAM_D8 : P23, " & "RAM_D7 : N21, " & "RAM_D6 : P24, " & "RAM_D5 : R23, " & "RAM_D4 : P21, " & "RAM_D3 : R24, " & "RAM_D2 : T24, " & "RAM_D1 : T22, " & "RAM_D0 : T23, " & "RAM_A14 : W21, " & "RAM_A13 : AA24," & "RAM_A12 : Y23, " & "RAM_A11 : AB24," & "RAM_A10 : Y22, " & "RAM_A9 : AA23," & "RAM_A8 : AB23," & "RAM_A7 : AB22," & "RAM_A6 : AC23," & "RAM_A5 : AA21," & "RAM_A4 : AC22," & "RAM_A3 : AD24," & "RAM_A2 : AD23," & "RAM_A1 : AB20," & "RAM_A0 : AD22," & "RAM_CLK : U23, " & "RAM_CLKIN : T21, " & "RAM_CKE : U24, " & "RAM_CS_N : V24, " & "RAM_RAS_N : U21, " & "RAM_CAS_N : V23, " & "RAM_WR_N : V22, " & "RAM_DQM3 : W24, " & "RAM_DQM2 : V21, " & "RAM_DQM1 : W23, " & "RAM_DQM0 : Y24, " & "VSS0 : AC2, " & "VSS1 : AC3, " & "VSS2 : AC4, " & "SYSCLKEN : C5, " & "RESOUT_N : AB12," & "ONSW : D12, " & "HIGHCORE : A3, " & "TEST : D3, " & "TEST_CLK2 : AB3, " & "USB_ATX_INT_N : AA7, " & "USB_OE_TP_N : AD6, " & "USB_DAT_VP_U5_RX : AA8, " & "USB_SE0_VM_U5_TX : AB7, " & "FLASH_IO7 : AD18," & "FLASH_IO6 : AC17," & "FLASH_IO5 : AD19," & "FLASH_IO4 : AB19," & "FLASH_IO3 : AC20," & "FLASH_IO2 : AC19," & "FLASH_IO1 : AD20," & "FLASH_IO0 : AD21," & "FLASH_ALE : AA16," & "FLASH_CE_N : AC21," & "FLASH_WR_N : AD17," & "FLASH_RD_N : AA17," & "FLASH_CLE : AC15," & "FLASH_RDY : AC18," & "MS_SCLK : AA1, " & "MS_BS : Y1, " & "MS_DIO0 : W2, " & "MS_DIO1 : U2, " & "MS_DIO2 : Y2, " & "MS_DIO3 : V4, " & "GPI11 : D10, " & "GPI10_U4_RX : K1, " & "GPI09_KEY_COL7 : L2, " & "GPI08_KEY_COL6_SPI2_BUSY : K2, " & "GPI07 : J1, " & "GPI06_HSTIM_CAP : AA3, " & "GPI05 : A12, " & "GPI04_SPI1_BUSY : K4, " & "GPI03 : AA11," & "GPI02 : J3, " & "GPI01_SERVICE_N : K3, " & "GPI00 : H1, " & "GPO23_U2_HRTS : A11, " & "GPO22_U7_HRTS : P2, " & "GPO21_U4_TX : P4, " & "GPO20 : AD10," & "GPO19 : AC10," & "GPO18 : P1, " & "GPO17 : B12, " & "GPO16 : N2, " & "GPO15 : R4, " & "GPO14 : AD9, " & "GPO13 : N1, " & "GPO12 : P3, " & "GPO11 : AB1, " & "GPO10 : M2, " & "GPO09 : N4, " & "GPO08 : M1, " & "GPO07 : M3, " & "GPO06 : M4, " & "GPO05 : AB10," & "GPO04 : Y3, " & "GPO03 : L1, " & "GPO02 : L4, " & "GPO01 : AC9, " & "GPO00_TST_CLK1 : AB9, " & "GPIO05 : R2, " & "GPIO04 : T2, " & "GPIO03_KEY_ROW7 : T1, " & "GPIO02_KEY_ROW6 : U3, " & "GPIO01 : R1, " & "GPIO00 : T3, " & "JTAG1_RTCK : A6, " & "U1_TX : B10, " & "U1_RX_PIO_INP15 : B9, " & "U2_TX : D9, " & "U2_RX_PIO_INP17 : C7, " & "U2_HCTS_PIO_INP16 : B8, " & "U3_TX : A7, " & "U3_RX_PIO_INP18 : C6, " & "U5_TX : C4, " & "U5_RX_PIO_INP20 : A2, " & "U6_IRTX : D5, " & "U6_IRRX_PIO_INP21 : A1, " & "U7_TX : B3, " & "U7_RX_PIO_INP23 : C3, " & "U7_HCTS_PIO_INP22 : B2, " & "KEY_ROW5 : E2, " & "KEY_ROW4 : D1, " & "KEY_ROW3 : F3, " & "KEY_ROW2 : E1, " & "KEY_ROW1 : F2, " & "KEY_ROW0 : G3, " & "KEY_COL5 : B1, " & "KEY_COL4 : E4, " & "KEY_COL3 : C2, " & "KEY_COL2 : C1, " & "KEY_COL1 : F4, " & "KEY_COL0 : D2, " & "PWM_OUT1 : J2, " & "PWM_OUT2 : H3, " & "SPI1_CLK : W3, " & "SPI1_DATIO : W1, " & "SPI1_DATIN : V1, " & "SPI2_CLK : V3, " & "SPI2_DATIO : V2, " & "SPI2_DATIN : T4, " & "RESET_N : D13, " & "VDD12 : B14, " & "VDD_AD28 : (D24, E21), " & "VDD_CORE12_01 : AA2, " & "VDD_CORE12_02 : D6, " & "VDD_CORE12_03 : K21, " & "VDD_CORE12_05 : L3, " & "VDD_CORE12_06 : AA12," & "VDD_CORE12_07 : AB6, " & "VDD_CORE12_08 : AB18," & "VDD_COREFXD12_01 : C10, " & "VDD_COREFXD12_02 : D18, " & "VDD_IOA : (B7, B4), " & "VDD_IOB : AA4, " & "VDD_IOC : (AA19, AA15, AB11, AC7), " & "VDD_IOD : (U4, G4), " & "VDD_OSC12 : D20, " & "VDD_PLL397_12 : C22, " & "VDD_PLLHCLK_12 : A22, " & "VDD_PLLUSB_12 : B22, " & "VDD_RTC12 : C12, " & "VDD_RTCCORE12 : C11, " & "VDD_RTCOSC12 : C14, " & "VDD_RAM : (G21, F22, J22, K22, P22, U22, Y21, AC24, AA20), " & "VSS_AD : D22, " & "VSS_CORE_01 : C20, " & "VSS_CORE_02 : D8, " & "VSS_CORE_03 : D16, " & "VSS_CORE_04 : J4, " & "VSS_CORE_05 : R3, " & "VSS_CORE_06 : R21, " & "VSS_CORE_07 : AA5, " & "VSS_CORE_08 : AA10," & "VSS_CORE_09 : AB17," & "VSS_IOA : A10, " & "VSS_IOB : AB5, " & "VSS_IOC : (AC16, AD15, AB8), " & "VSS_IOD : (D4, E3, F1, N3), " & "VSS_OSC : B21, " & "VSS_PLL397 : C23, " & "VSS_PLLHCLK : D19, " & "VSS_PLLUSB : B20, " & "VSS_RTCCORE : B13, " & "VSS_RTCOSC : C13, " & "VSS_RAM : (AD11, C19, F23, G22, J23, M21, N22, R22, W22, AA22, AB21), " & "NC : (A8,A9,A15,A16,A17,A18,A19,A20,A21,A24,B11,B17,B18,B15,B16,B19,B24,C9,C8,C15,C16,C17,C18,D11,D14,D15,D17,D21,G1,G2,H2,H4,U1,W4,AA6,AA13,AA14,AA18,AB2,AB4,AB13,AB14,AB15,AB16,AC5,AC6,AC11,AC12,AC13,AC14,AD1,AD2,AD3,AD4,AD5,AD12,AD13,AD14,AD16)"; -- -- This section specifies the TAP ports. For the TAP TCK port, the parameters in the brackets are: -- First Field : Maximum TCK frequency. -- Second Field : Allowable states TCK may be stopped in. -- attribute TAP_SCAN_CLOCK of JTAG1_TCK : signal is (10.0e6, both); attribute TAP_SCAN_IN of JTAG1_TDI : signal is true; attribute TAP_SCAN_MODE of JTAG1_TMS : signal is true; attribute TAP_SCAN_OUT of JTAG1_TDO : signal is true; attribute TAP_SCAN_RESET of JTAG1_NTRST : signal is true; -- -- Specifies the compliance enable patterns for the design. It lists a set of -- design ports and the values that they should be set to, in order to enable -- compliance to IEEE Std 1149.1 -- attribute COMPLIANCE_PATTERNS of LPC3180FEL320_01 : entity is "(TEST) (1)"; -- -- Specifies the number of bits in the instruction register. -- attribute INSTRUCTION_LENGTH of LPC3180FEL320_01 : entity is 4; -- -- Specifies the boundary-scan instructions implemented in the design and their -- opcodes. -- attribute INSTRUCTION_OPCODE of LPC3180FEL320_01 : entity is "BYPASS (1111)," & "EXTEST (0000)," & "INTEST (0011)," & "SAMPLE (0001)," & "PRELOAD (0010)," & "HIGHZ (0101)," & "CLAMP (0110)," & "IDCODE (0100)"; -- -- Specifies the bit pattern that is loaded into the instruction register when -- the TAP controller passes through the Capture-IR state. The standard mandates -- that the two LSBs must be "01". The remaining bits are design specific. -- attribute INSTRUCTION_CAPTURE of LPC3180FEL320_01 : entity is "0001"; -- -- Specifies the bit pattern that is loaded into the DEVICE_ID register during -- the IDCODE instruction when the TAP controller passes through the Capture-DR -- state. -- attribute IDCODE_REGISTER of LPC3180FEL320_01 : entity is "0000" & -- version "1000110100100100" & -- part number "00000010101" & -- manufacturer "1"; -- mandatory -- -- This section specifies the test data register placed between TDI and TDO for -- each implemented instruction. -- attribute REGISTER_ACCESS of LPC3180FEL320_01 : entity is "BYPASS (BYPASS)," & "BOUNDARY (EXTEST)," & "BOUNDARY (INTEST)," & "BOUNDARY (SAMPLE)," & "BOUNDARY (PRELOAD)," & "BYPASS (HIGHZ)," & "BYPASS (CLAMP)," & "DEVICE_ID (IDCODE)"; -- -- Specifies the length of the boundary scan register. -- attribute BOUNDARY_LENGTH of LPC3180FEL320_01 : entity is 403; -- -- The following list specifies the characteristics of each cell in the boundary -- scan register from TDI to TDO. The following is a description of the label -- fields : -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not have a port -- name. -- function : Is the function of the cell as defined by the standard. Is one -- of input, output2, output3, bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be loaded with -- for safe operation when the software might otherwise choose a -- random value. -- ccell : The control cell number. Specifies the control cell that -- drives the output enable for this port. -- disval : Specifies the value that is loaded into the control cell to -- disable the output enable for the corresponding port. -- rslt : Resulting state. Shows the state of the driver when it is -- disabled. -- attribute BOUNDARY_REGISTER of LPC3180FEL320_01 : entity is -- -- num cell port function safe [ccell disval rslt] -- "402 (BC_1, *, CONTROL, 1)," & "401 (BC_7, RAM_D31_PIO_SD12, BIDIR, X, 402, 1, Z)," & "400 (BC_1, *, CONTROL, 1)," & "399 (BC_7, RAM_D30_PIO_SD11, BIDIR, X, 400, 1, Z)," & "398 (BC_1, *, CONTROL, 1)," & "397 (BC_7, RAM_D29_PIO_SD10, BIDIR, X, 398, 1, Z)," & "396 (BC_1, *, CONTROL, 1)," & "395 (BC_7, RAM_D28_PIO_SD9, BIDIR, X, 396, 1, Z)," & "394 (BC_1, *, CONTROL, 1)," & "393 (BC_7, RAM_D27_PIO_SD8, BIDIR, X, 394, 1, Z)," & "392 (BC_1, *, CONTROL, 1)," & "391 (BC_7, RAM_D26_PIO_SD7, BIDIR, X, 392, 1, Z)," & "390 (BC_1, *, CONTROL, 1)," & "389 (BC_7, RAM_D25_PIO_SD6, BIDIR, X, 390, 1, Z)," & "388 (BC_1, *, CONTROL, 1)," & "387 (BC_7, RAM_D24_PIO_SD5, BIDIR, X, 388, 1, Z)," & "386 (BC_1, *, CONTROL, 1)," & "385 (BC_7, RAM_D23_PIO_SD4, BIDIR, X, 386, 1, Z)," & "384 (BC_1, *, CONTROL, 1)," & "383 (BC_7, RAM_D22_PIO_SD3, BIDIR, X, 384, 1, Z)," & "382 (BC_1, *, CONTROL, 1)," & "381 (BC_7, RAM_D21_PIO_SD2, BIDIR, X, 382, 1, Z)," & "380 (BC_1, *, CONTROL, 1)," & "379 (BC_7, RAM_D20_PIO_SD1, BIDIR, X, 380, 1, Z)," & "378 (BC_1, *, CONTROL, 1)," & "377 (BC_7, RAM_D19_PIO_SD0, BIDIR, X, 378, 1, Z)," & "376 (BC_1, *, CONTROL, 1)," & "375 (BC_7, RAM_D18_DDR_NCLK, BIDIR, X, 376, 1, Z)," & "374 (BC_1, *, CONTROL, 1)," & "373 (BC_7, RAM_D17_DDR_DQS1, BIDIR, X, 374, 1, Z)," & "372 (BC_1, *, CONTROL, 1)," & "371 (BC_7, RAM_D16_DDR_DQS0, BIDIR, X, 372, 1, Z)," & "370 (BC_1, *, CONTROL, 1)," & "369 (BC_7, RAM_D15, BIDIR, X, 370, 1, Z)," & "368 (BC_1, *, CONTROL, 1)," & "367 (BC_7, RAM_D14, BIDIR, X, 368, 1, Z)," & "366 (BC_1, *, CONTROL, 1)," & "365 (BC_7, RAM_D13, BIDIR, X, 366, 1, Z)," & "364 (BC_1, *, CONTROL, 1)," & "363 (BC_7, RAM_D12, BIDIR, X, 364, 1, Z)," & "362 (BC_1, *, CONTROL, 1)," & "361 (BC_7, RAM_D11, BIDIR, X, 362, 1, Z)," & "360 (BC_1, *, CONTROL, 1)," & "359 (BC_7, RAM_D10, BIDIR, X, 360, 1, Z)," & "358 (BC_1, *, CONTROL, 1)," & "357 (BC_7, RAM_D9, BIDIR, X, 358, 1, Z)," & "356 (BC_1, *, CONTROL, 1)," & "355 (BC_7, RAM_D8, BIDIR, X, 356, 1, Z)," & "354 (BC_1, *, CONTROL, 1)," & "353 (BC_7, RAM_D7, BIDIR, X, 354, 1, Z)," & "352 (BC_1, *, CONTROL, 1)," & "351 (BC_7, RAM_D6, BIDIR, X, 352, 1, Z)," & "350 (BC_1, *, CONTROL, 1)," & "349 (BC_7, RAM_D5, BIDIR, X, 350, 1, Z)," & "348 (BC_1, *, CONTROL, 1)," & "347 (BC_7, RAM_D4, BIDIR, X, 348, 1, Z)," & "346 (BC_1, *, CONTROL, 1)," & "345 (BC_7, RAM_D3, BIDIR, X, 346, 1, Z)," & "344 (BC_1, *, CONTROL, 1)," & "343 (BC_7, RAM_D2, BIDIR, X, 344, 1, Z)," & "342 (BC_1, *, CONTROL, 1)," & "341 (BC_7, RAM_D1, BIDIR, X, 342, 1, Z)," & "340 (BC_1, *, CONTROL, 1)," & "339 (BC_7, RAM_D0, BIDIR, X, 340, 1, Z)," & "338 (BC_1, *, INTERNAL, 1)," & "337 (BC_1, *, INTERNAL, X)," & "336 (BC_1, *, INTERNAL, 1)," & "335 (BC_1, *, INTERNAL, X)," & "334 (BC_1, *, INTERNAL, 1)," & "333 (BC_1, *, INTERNAL, X)," & "332 (BC_1, *, INTERNAL, 1)," & "331 (BC_1, *, INTERNAL, X)," & "330 (BC_1, *, INTERNAL, 1)," & "329 (BC_1, *, INTERNAL, X)," & "328 (BC_1, *, INTERNAL, 1)," & "327 (BC_1, *, INTERNAL, X)," & "326 (BC_1, *, INTERNAL, 1)," & "325 (BC_1, *, INTERNAL, X)," & "324 (BC_1, *, INTERNAL, 1)," & "323 (BC_1, *, INTERNAL, X)," & "322 (BC_1, *, INTERNAL, 1)," & "321 (BC_1, *, INTERNAL, X)," & "320 (BC_1, *, CONTROL, 1)," & "319 (BC_7, RAM_A14, BIDIR, X, 320, 1, Z)," & "318 (BC_1, *, CONTROL, 1)," & "317 (BC_7, RAM_A13, BIDIR, X, 318, 1, Z)," & "316 (BC_1, *, CONTROL, 1)," & "315 (BC_7, RAM_A12, BIDIR, X, 316, 1, Z)," & "314 (BC_1, *, CONTROL, 1)," & "313 (BC_7, RAM_A11, BIDIR, X, 314, 1, Z)," & "312 (BC_1, *, CONTROL, 1)," & "311 (BC_7, RAM_A10, BIDIR, X, 312, 1, Z)," & "310 (BC_1, *, CONTROL, 1)," & "309 (BC_7, RAM_A9, BIDIR, X, 310, 1, Z)," & "308 (BC_1, *, CONTROL, 1)," & "307 (BC_7, RAM_A8, BIDIR, X, 308, 1, Z)," & "306 (BC_1, *, CONTROL, 1)," & "305 (BC_7, RAM_A7, BIDIR, X, 306, 1, Z)," & "304 (BC_1, *, CONTROL, 1)," & "303 (BC_7, RAM_A6, BIDIR, X, 304, 1, Z)," & "302 (BC_1, *, CONTROL, 1)," & "301 (BC_7, RAM_A5, BIDIR, X, 302, 1, Z)," & "300 (BC_1, *, CONTROL, 1)," & "299 (BC_7, RAM_A4, BIDIR, X, 300, 1, Z)," & "298 (BC_1, *, CONTROL, 1)," & "297 (BC_7, RAM_A3, BIDIR, X, 298, 1, Z)," & "296 (BC_1, *, CONTROL, 1)," & "295 (BC_7, RAM_A2, BIDIR, X, 296, 1, Z)," & "294 (BC_1, *, CONTROL, 1)," & "293 (BC_7, RAM_A1, BIDIR, X, 294, 1, Z)," & "292 (BC_1, *, CONTROL, 1)," & "291 (BC_7, RAM_A0, BIDIR, X, 292, 1, Z)," & "290 (BC_1, *, CONTROL, 1)," & "289 (BC_7, RAM_CLK, BIDIR, X, 290, 1, Z)," & "288 (BC_1, *, CONTROL, 1)," & "287 (BC_7, RAM_CLKIN, BIDIR, X, 288, 1, Z)," & "286 (BC_1, *, CONTROL, 1)," & "285 (BC_7, RAM_CKE, BIDIR, X, 286, 1, Z)," & "284 (BC_1, *, INTERNAL, 1)," & "283 (BC_1, *, INTERNAL, X)," & "282 (BC_1, *, INTERNAL, 1)," & "281 (BC_1, *, INTERNAL, X)," & "280 (BC_1, *, INTERNAL, 1)," & "279 (BC_1, *, INTERNAL, X)," & "278 (BC_1, *, INTERNAL, 1)," & "277 (BC_1, *, INTERNAL, X)," & "276 (BC_1, *, CONTROL, 1)," & "275 (BC_7, RAM_CS_N, BIDIR, X, 276, 1, Z)," & "274 (BC_1, *, INTERNAL, 1)," & "273 (BC_1, *, INTERNAL, X)," & "272 (BC_1, *, CONTROL, 1)," & "271 (BC_7, RAM_RAS_N, BIDIR, X, 272, 1, Z)," & "270 (BC_1, *, CONTROL, 1)," & "269 (BC_7, RAM_CAS_N, BIDIR, X, 270, 1, Z)," & "268 (BC_1, *, CONTROL, 1)," & "267 (BC_7, RAM_WR_N, BIDIR, X, 268, 1, Z)," & "266 (BC_1, *, CONTROL, 1)," & "265 (BC_7, RAM_DQM3, BIDIR, X, 266, 1, Z)," & "264 (BC_1, *, CONTROL, 1)," & "263 (BC_7, RAM_DQM2, BIDIR, X, 264, 1, Z)," & "262 (BC_1, *, CONTROL, 1)," & "261 (BC_7, RAM_DQM1, BIDIR, X, 262, 1, Z)," & "260 (BC_1, *, CONTROL, 1)," & "259 (BC_7, RAM_DQM0, BIDIR, X, 260, 1, Z)," & "258 (BC_1, *, INTERNAL, 1)," & "257 (BC_1, *, INTERNAL, X)," & "256 (BC_1, *, INTERNAL, 1)," & "255 (BC_1, *, INTERNAL, X)," & "254 (BC_1, *, INTERNAL, 1)," & "253 (BC_1, *, INTERNAL, X)," & "252 (BC_1, *, INTERNAL, 1)," & "251 (BC_1, *, INTERNAL, X)," & "250 (BC_1, *, INTERNAL, 1)," & "249 (BC_1, *, INTERNAL, X)," & "248 (BC_1, *, INTERNAL, 1)," & "247 (BC_1, *, INTERNAL, X)," & "246 (BC_1, *, INTERNAL, 1)," & "245 (BC_1, *, INTERNAL, X )," & "244 (BC_1, *, INTERNAL, 1)," & "243 (BC_1, *, INTERNAL, X)," & "242 (BC_1, *, INTERNAL, 1)," & "241 (BC_1, *, INTERNAL, X)," & "240 (BC_1, *, INTERNAL, 1)," & "239 (BC_1, *, INTERNAL, X)," & "238 (BC_1, *, INTERNAL, 1)," & "237 (BC_1, *, INTERNAL, X)," & "236 (BC_1, *, INTERNAL, 1)," & "235 (BC_1, *, INTERNAL, X)," & "234 (BC_1, *, INTERNAL, 1)," & "233 (BC_1, *, INTERNAL, X)," & "232 (BC_1, *, CONTROL, 1)," & "231 (BC_7, VSS0, BIDIR, X, 232, 1, Z)," & "230 (BC_1, *, CONTROL, 1)," & "229 (BC_7, VSS1, BIDIR, X, 230, 1, Z)," & "228 (BC_1, *, CONTROL, 1)," & "227 (BC_7, VSS2, BIDIR, X, 228, 1, Z)," & "226 (BC_1, *, CONTROL, 1)," & "225 (BC_7, SYSCLKEN, BIDIR, X, 226, 1, Z)," & "224 (BC_1, *, CONTROL, 1)," & "223 (BC_7, RESOUT_N, BIDIR, X, 224, 1, Z)," & "222 (BC_1, *, CONTROL, 1)," & "221 (BC_7, ONSW, BIDIR, X, 222, 1, Z)," & "220 (BC_1, *, CONTROL, 1)," & "219 (BC_7, HIGHCORE, BIDIR, X, 220, 1, Z)," & "218 (BC_1, *, CONTROL, 1)," & "217 (BC_7, TEST_CLK2, BIDIR, X, 218, 1, Z)," & "216 (BC_1, *, CONTROL, 1)," & "215 (BC_7, USB_ATX_INT_N, BIDIR, X, 216, 1, Z)," & "214 (BC_1, *, CONTROL, 1)," & "213 (BC_7, USB_OE_TP_N, BIDIR, X, 214, 1, Z)," & "212 (BC_1, *, CONTROL, 1)," & "211 (BC_7, USB_DAT_VP_U5_RX, BIDIR, X, 212, 1, Z)," & "210 (BC_1, *, CONTROL, 1)," & "209 (BC_7, USB_SE0_VM_U5_TX, BIDIR, X, 210, 1, Z)," & "208 (BC_1, *, CONTROL, 1)," & "207 (BC_7, FLASH_IO7, BIDIR, X, 208, 1, Z)," & "206 (BC_1, *, CONTROL, 1)," & "205 (BC_7, FLASH_IO6, BIDIR, X, 206, 1, Z)," & "204 (BC_1, *, CONTROL, 1)," & "203 (BC_7, FLASH_IO5, BIDIR, X, 204, 1, Z)," & "202 (BC_1, *, CONTROL, 1)," & "201 (BC_7, FLASH_IO4, BIDIR, X, 202, 1, Z)," & "200 (BC_1, *, CONTROL, 1)," & "199 (BC_7, FLASH_IO3, BIDIR, X, 200, 1, Z)," & "198 (BC_1, *, CONTROL, 1)," & "197 (BC_7, FLASH_IO2, BIDIR, X, 198, 1, Z)," & "196 (BC_1, *, CONTROL, 1)," & "195 (BC_7, FLASH_IO1, BIDIR, X, 196, 1, Z)," & "194 (BC_1, *, CONTROL, 1)," & "193 (BC_7, FLASH_IO0, BIDIR, X, 194, 1, Z)," & "192 (BC_1, *, CONTROL, 1)," & "191 (BC_7, FLASH_ALE, BIDIR, X, 192, 1, Z)," & "190 (BC_1, *, CONTROL, 1)," & "189 (BC_7, FLASH_CE_N, BIDIR, X, 190, 1, Z)," & "188 (BC_1, *, CONTROL, 1)," & "187 (BC_7, FLASH_WR_N, BIDIR, X, 188, 1, Z)," & "186 (BC_1, *, CONTROL, 1)," & "185 (BC_7, FLASH_RD_N, BIDIR, X, 186, 1, Z)," & "184 (BC_1, *, CONTROL, 1)," & "183 (BC_7, FLASH_CLE, BIDIR, X, 184, 1, Z)," & "182 (BC_1, *, CONTROL, 1)," & "181 (BC_7, FLASH_RDY, BIDIR, X, 182, 1, Z)," & "180 (BC_1, *, CONTROL, 1)," & "179 (BC_7, MS_SCLK, BIDIR, X, 180, 1, Z)," & "178 (BC_1, *, CONTROL, 1)," & "177 (BC_7, MS_BS, BIDIR, X, 178, 1, Z)," & "176 (BC_1, *, CONTROL, 1)," & "175 (BC_7, MS_DIO0, BIDIR, X, 176, 1, Z)," & "174 (BC_1, *, CONTROL, 1)," & "173 (BC_7, MS_DIO1, BIDIR, X, 174, 1, Z)," & "172 (BC_1, *, CONTROL, 1)," & "171 (BC_7, MS_DIO2, BIDIR, X, 172, 1, Z)," & "170 (BC_1, *, CONTROL, 1)," & "169 (BC_7, MS_DIO3, BIDIR, X, 170, 1, Z)," & "168 (BC_1, *, CONTROL, 1)," & "167 (BC_7, GPI11, BIDIR, X, 168, 1, Z)," & "166 (BC_1, *, CONTROL, 1)," & "165 (BC_7, GPI10_U4_RX, BIDIR, X, 166, 1, Z)," & "164 (BC_1, *, CONTROL, 1)," & "163 (BC_7, GPI09_KEY_COL7, BIDIR, X, 164, 1, Z)," & "162 (BC_1, *, CONTROL, 1)," & "161 (BC_7, GPI08_KEY_COL6_SPI2_BUSY, BIDIR, X, 162, 1, Z)," & "160 (BC_1, *, CONTROL, 1)," & "159 (BC_7, GPI07, BIDIR, X, 160, 1, Z)," & "158 (BC_1, *, CONTROL, 1)," & "157 (BC_7, GPI06_HSTIM_CAP, BIDIR, X, 158, 1, Z)," & "156 (BC_1, *, CONTROL, 1)," & "155 (BC_7, GPI05, BIDIR, X, 156, 1, Z)," & "154 (BC_1, *, CONTROL, 1)," & "153 (BC_7, GPI04_SPI1_BUSY, BIDIR, X, 154, 1, Z)," & "152 (BC_1, *, CONTROL, 1)," & "151 (BC_7, GPI03, BIDIR, X, 152, 1, Z)," & "150 (BC_1, *, CONTROL, 1)," & "149 (BC_7, GPI02, BIDIR, X, 150, 1, Z)," & "148 (BC_1, *, CONTROL, 1)," & "147 (BC_7, GPI01_SERVICE_N, BIDIR, X, 148, 1, Z)," & "146 (BC_1, *, CONTROL, 1)," & "145 (BC_7, GPI00, BIDIR, X, 146, 1, Z)," & "144 (BC_1, *, CONTROL, 1)," & "143 (BC_7, GPO23_U2_HRTS, BIDIR, X, 144, 1, Z)," & "142 (BC_1, *, CONTROL, 1)," & "141 (BC_7, GPO22_U7_HRTS, BIDIR, X, 142, 1, Z)," & "140 (BC_1, *, CONTROL, 1)," & "139 (BC_7, GPO21_U4_TX, BIDIR, X, 140, 1, Z)," & "138 (BC_1, *, CONTROL, 1)," & "137 (BC_7, GPO20, BIDIR, X, 138, 1, Z)," & "136 (BC_1, *, CONTROL, 1)," & "135 (BC_7, GPO19, BIDIR, X, 136, 1, Z)," & "134 (BC_1, *, CONTROL, 1)," & "133 (BC_7, GPO18, BIDIR, X, 134, 1, Z)," & "132 (BC_1, *, CONTROL, 1)," & "131 (BC_7, GPO17, BIDIR, X, 132, 1, Z)," & "130 (BC_1, *, CONTROL, 1)," & "129 (BC_7, GPO16, BIDIR, X, 130, 1, Z)," & "128 (BC_1, *, CONTROL, 1)," & "127 (BC_7, GPO15, BIDIR, X, 128, 1, Z)," & "126 (BC_1, *, CONTROL, 1)," & "125 (BC_7, GPO14, BIDIR, X, 126, 1, Z)," & "124 (BC_1, *, CONTROL, 1)," & "123 (BC_7, GPO13, BIDIR, X, 124, 1, Z)," & "122 (BC_1, *, CONTROL, 1)," & "121 (BC_7, GPO12, BIDIR, X, 122, 1, Z)," & "120 (BC_1, *, CONTROL, 1)," & "119 (BC_7, GPO11, BIDIR, X, 120, 1, Z)," & "118 (BC_1, *, CONTROL, 1)," & "117 (BC_7, GPO10, BIDIR, X, 118, 1, Z)," & "116 (BC_1, *, CONTROL, 1)," & "115 (BC_7, GPO09, BIDIR, X, 116, 1, Z)," & "114 (BC_1, *, CONTROL, 1)," & "113 (BC_7, GPO08, BIDIR, X, 114, 1, Z)," & "112 (BC_1, *, CONTROL, 1)," & "111 (BC_7, GPO07, BIDIR, X, 112, 1, Z)," & "110 (BC_1, *, CONTROL, 1)," & "109 (BC_7, GPO06, BIDIR, X, 110, 1, Z)," & "108 (BC_1, *, CONTROL, 1)," & "107 (BC_7, GPO05, BIDIR, X, 108, 1, Z)," & "106 (BC_1, *, CONTROL, 1)," & "105 (BC_7, GPO04, BIDIR, X, 106, 1, Z)," & "104 (BC_1, *, CONTROL, 1)," & "103 (BC_7, GPO03, BIDIR, X, 104, 1, Z)," & "102 (BC_1, *, CONTROL, 1)," & "101 (BC_7, GPO02, BIDIR, X, 102, 1, Z)," & "100 (BC_1, *, CONTROL, 1)," & "99 (BC_7, GPO01, BIDIR, X, 100, 1, Z)," & "98 (BC_1, *, CONTROL, 1)," & "97 (BC_7, GPO00_TST_CLK1, BIDIR, X, 98, 1, Z)," & "96 (BC_1, *, CONTROL, 1)," & "95 (BC_7, GPIO05, BIDIR, X, 96, 1, Z)," & "94 (BC_1, *, CONTROL, 1)," & "93 (BC_7, GPIO04, BIDIR, X, 94, 1, Z)," & "92 (BC_1, *, CONTROL, 1)," & "91 (BC_7, GPIO03_KEY_ROW7, BIDIR, X, 92, 1, Z)," & "90 (BC_1, *, CONTROL, 1)," & "89 (BC_7, GPIO02_KEY_ROW6, BIDIR, X, 90, 1, Z)," & "88 (BC_1, *, CONTROL, 1)," & "87 (BC_7, GPIO01, BIDIR, X, 88, 1, Z)," & "86 (BC_1, *, CONTROL, 1)," & "85 (BC_7, GPIO00, BIDIR, X, 86, 1, Z)," & "84 (BC_1, *, CONTROL, 1)," & "83 (BC_7, JTAG1_RTCK, BIDIR, X, 84, 1, Z)," & "82 (BC_1, *, CONTROL, 1)," & "81 (BC_7, U1_TX, BIDIR, X, 82, 1, Z)," & "80 (BC_1, *, CONTROL, 1)," & "79 (BC_7, U1_RX_PIO_INP15, BIDIR, X, 80, 1, Z)," & "78 (BC_1, *, CONTROL, 1)," & "77 (BC_7, U2_TX, BIDIR, X, 78, 1, Z)," & "76 (BC_1, *, CONTROL, 1)," & "75 (BC_7, U2_RX_PIO_INP17, BIDIR, X, 76, 1, Z)," & "74 (BC_1, *, CONTROL, 1)," & "73 (BC_7, U2_HCTS_PIO_INP16, BIDIR, X, 74, 1, Z)," & "72 (BC_1, *, CONTROL, 1)," & "71 (BC_7, U3_TX, BIDIR, X, 72, 1, Z)," & "70 (BC_1, *, CONTROL, 1)," & "69 (BC_7, U3_RX_PIO_INP18, BIDIR, X, 70, 1, Z)," & "68 (BC_1, *, CONTROL, 1)," & "67 (BC_7, U5_TX, BIDIR, X, 68, 1, Z)," & "66 (BC_1, *, CONTROL, 1)," & "65 (BC_7, U5_RX_PIO_INP20, BIDIR, X, 66, 1, Z)," & "64 (BC_1, *, CONTROL, 1)," & "63 (BC_7, U6_IRTX, BIDIR, X, 64, 1, Z)," & "62 (BC_1, *, CONTROL, 1)," & "61 (BC_7, U6_IRRX_PIO_INP21, BIDIR, X, 62, 1, Z)," & "60 (BC_1, *, CONTROL, 1)," & "59 (BC_7, U7_TX, BIDIR, X, 60, 1, Z)," & "58 (BC_1, *, CONTROL, 1)," & "57 (BC_7, U7_RX_PIO_INP23, BIDIR, X, 58, 1, Z)," & "56 (BC_1, *, CONTROL, 1)," & "55 (BC_7, U7_HCTS_PIO_INP22, BIDIR, X, 56, 1, Z)," & "54 (BC_1, *, CONTROL, 1)," & "53 (BC_7, KEY_ROW5, BIDIR, X, 54, 1, Z)," & "52 (BC_1, *, CONTROL, 1)," & "51 (BC_7, KEY_ROW4, BIDIR, X, 52, 1, Z)," & "50 (BC_1, *, CONTROL, 1)," & "49 (BC_7, KEY_ROW3, BIDIR, X, 50, 1, Z)," & "48 (BC_1, *, CONTROL, 1)," & "47 (BC_7, KEY_ROW2, BIDIR, X, 48, 1, Z)," & "46 (BC_1, *, CONTROL, 1)," & "45 (BC_7, KEY_ROW1, BIDIR, X, 46, 1, Z)," & "44 (BC_1, *, CONTROL, 1)," & "43 (BC_7, KEY_ROW0, BIDIR, X, 44, 1, Z)," & "42 (BC_1, *, CONTROL, 1)," & "41 (BC_7, KEY_COL5, BIDIR, X, 42, 1, Z)," & "40 (BC_1, *, CONTROL, 1)," & "39 (BC_7, KEY_COL4, BIDIR, X, 40, 1, Z)," & "38 (BC_1, *, CONTROL, 1)," & "37 (BC_7, KEY_COL3, BIDIR, X, 38, 1, Z)," & "36 (BC_1, *, CONTROL, 1)," & "35 (BC_7, KEY_COL2, BIDIR, X, 36, 1, Z)," & "34 (BC_1, *, CONTROL, 1)," & "33 (BC_7, KEY_COL1, BIDIR, X, 34, 1, Z)," & "32 (BC_1, *, CONTROL, 1)," & "31 (BC_7, KEY_COL0, BIDIR, X, 32, 1, Z)," & "30 (BC_1, *, CONTROL, 1)," & "29 (BC_7, PWM_OUT1, BIDIR, X, 30, 1, Z)," & "28 (BC_1, *, CONTROL, 1)," & "27 (BC_7, PWM_OUT2, BIDIR, X, 28, 1, Z)," & "26 (BC_1, *, CONTROL, 1)," & "25 (BC_7, SPI1_CLK, BIDIR, X, 26, 1, Z)," & "24 (BC_1, *, CONTROL, 1)," & "23 (BC_7, SPI1_DATIO, BIDIR, X, 24, 1, Z)," & "22 (BC_1, *, CONTROL, 1)," & "21 (BC_7, SPI1_DATIN, BIDIR, X, 22, 1, Z)," & "20 (BC_1, *, CONTROL, 1)," & "19 (BC_7, SPI2_CLK, BIDIR, X, 20, 1, Z)," & "18 (BC_1, *, CONTROL, 1)," & "17 (BC_7, SPI2_DATIO, BIDIR, X, 18, 1, Z)," & "16 (BC_1, *, CONTROL, 1)," & "15 (BC_7, SPI2_DATIN, BIDIR, X, 16, 1, Z)," & "14 (BC_1, RESET_N, INPUT, X)," & "13 (BC_1, I2C1_SDA, INPUT, X)," & "12 (BC_1, I2C1_SDA, OUTPUT2, 1, 12, 1, WEAK1)," & "11 (BC_1, I2C1_SCL, INPUT, X)," & "10 (BC_1, I2C1_SCL, OUTPUT2, 1, 10, 1, WEAK1)," & "9 (BC_1, I2C2_SCL, INPUT, X)," & "8 (BC_1, I2C2_SCL, OUTPUT2, 1, 8, 1, WEAK1)," & "7 (BC_1, I2C2_SDA, INPUT, X)," & "6 (BC_1, I2C2_SDA, OUTPUT2, 1, 6, 1, WEAK1)," & "5 (BC_1, USB_I2C_SDA, INPUT, X)," & "4 (BC_1, USB_I2C_SDA, OUTPUT2, 1, 4, 1, WEAK1)," & "3 (BC_1, USB_I2C_SCL, INPUT, X)," & "2 (BC_1, USB_I2C_SCL, OUTPUT2, 1, 2, 1, WEAK1)," & "1 (BC_1, *, INTERNAL, X)," & "0 (BC_1, *, INTERNAL, 1)"; end LPC3180FEL320_01;