-- ***************************************************************************** -- BSDL file for design RTL8211DN_V10 -- Created by Synopsys Version A-2007.12-SP5 (Jul 18, 2008) -- Designer: ic_designer -- Company: Realtek -- Date: Wed Dec 30 20:35:44 2009 -- ***************************************************************************** entity chip is -- This section identifies the default device package selected. generic (PHYSICAL_PIN_MAP: string:= "RL6116_QFN88"); -- This section declares all the ports in the design. port ( TCK : in bit; TDI : in bit; TMS : in bit; COL : inout bit; CRS : inout bit; GTX_CLK : inout bit; INT : inout bit; LED0 : inout bit; LED1 : inout bit; LED2 : inout bit; LED3 : inout bit; MDC : inout bit; MDIO : inout bit; PME : inout bit; RXC : inout bit; RXD0 : inout bit; RXD1 : inout bit; RXD2 : inout bit; RXD3 : inout bit; RXD4 : inout bit; RXD5 : inout bit; RXD6 : inout bit; RXD7 : inout bit; RXDV : inout bit; RXER : inout bit; TXCLK : inout bit; TXD0 : inout bit; TXD1 : inout bit; TXD2 : inout bit; TXD3 : inout bit; TXD4 : inout bit; TXD5 : inout bit; TXD6 : inout bit; TXD7 : inout bit; TXEN : inout bit; TXER : inout bit; TDO : out bit; -- PHYRSTB : linkage bit; -- Commented by L.K.(StarTest) PHYRSTB : in bit; -- Added by L.K.(StarTest) PKG48PIN : linkage bit ); use STD_1149_1_2001.all; attribute COMPONENT_CONFORMANCE of chip: entity is "STD_1149_1_2001"; attribute PIN_MAP of chip: entity is PHYSICAL_PIN_MAP; -- This section specifies the pin map for each port. This information is -- extracted from the port-to-pin map file that was read in using the -- "read_pin_map" command. constant RL6116_QFN88: PIN_MAP_STRING := "TCK : 63," & "TDI : 65," & "TMS : 62," & "COL : 45," & "CRS : 46," & "GTX_CLK : 48," & "INT : 75," & "LED0 : 68," & "LED1 : 69," & "LED2 : 70," & "LED3 : 71," & "MDC : 72," & "MDIO : 73," & "PME : 74," & "RXC : 38," & "RXD0 : 33," & "RXD1 : 35," & "RXD2 : 36," & "RXD3 : 37," & "RXD4 : 39," & "RXD5 : 41," & "RXD6 : 42," & "RXD7 : 43," & "RXDV : 32," & "RXER : 44," & "TXCLK : 56," & "TXD0 : 50," & "TXD1 : 53," & "TXD2 : 54," & "TXD3 : 55," & "TXD4 : 57," & "TXD5 : 58," & "TXD6 : 59," & "TXD7 : 60," & "TXEN : 49," & "TXER : 61," & "PHYRSTB : 52," & -- Added by L.K.(StarTest) "TDO : 64"; -- This section specifies the TAP ports. For the TAP TCK port, the parameters in -- the brackets are: -- First Field : Maximum TCK frequency. -- Second Field: Allowable states TCK may be stopped in. attribute TAP_SCAN_CLOCK of TCK: signal is (10.0e6, BOTH); attribute TAP_SCAN_IN of TDI: signal is true; attribute TAP_SCAN_MODE of TMS: signal is true; attribute TAP_SCAN_OUT of TDO: signal is true; -- Specifies the compliance enable patterns for the design. It lists a set of -- design ports and the values that they should be set to, in order to enable -- compliance to IEEE Std 1149.1 attribute COMPLIANCE_PATTERNS of chip: entity is "(PHYRSTB) (1)"; -- Specifies the number of bits in the instruction register. attribute INSTRUCTION_LENGTH of chip: entity is 5; -- Specifies the boundary-scan instructions implemented in the design and their -- opcodes. attribute INSTRUCTION_OPCODE of chip: entity is "BYPASS (11111)," & "EXTEST (01000)," & "SAMPLE (10000)," & "PRELOAD (10000)," & "CLAMP (00010)"; -- Specifies the bit pattern that is loaded into the instruction register when -- the TAP controller passes through the Capture-IR state. The standard mandates -- that the two LSBs must be "01". The remaining bits are design specific. attribute INSTRUCTION_CAPTURE of chip: entity is "00001"; -- This section specifies the test data register placed between TDI and TDO for -- each implemented instruction. attribute REGISTER_ACCESS of chip: entity is "BYPASS (BYPASS, CLAMP)," & "BOUNDARY (EXTEST, SAMPLE, PRELOAD)"; -- Specifies the length of the boundary scan register. attribute BOUNDARY_LENGTH of chip: entity is 66; -- The following list specifies the characteristics of each cell in the boundary -- scan register from TDI to TDO. The following is a description of the label -- fields: -- num : Is the cell number. -- cell : Is the cell type as defined by the standard. -- port : Is the design port name. Control cells do not have a port -- name. -- function: Is the function of the cell as defined by the standard. Is one -- of input, output2, output3, bidir, control or controlr. -- safe : Specifies the value that the BSR cell should be loaded with -- for safe operation when the software might otherwise choose a -- random value. -- ccell : The control cell number. Specifies the control cell that -- drives the output enable for this port. -- disval : Specifies the value that is loaded into the control cell to -- disable the output enable for the corresponding port. -- rslt : Resulting state. Shows the state of the driver when it is -- disabled. attribute BOUNDARY_REGISTER of chip: entity is -- -- num cell port function safe [ccell disval rslt] -- "65 (BC_2, *, control, 0), " & "64 (BC_7, INT, bidir, X, 65, 0, Z), " & "63 (BC_2, *, control, 0), " & "62 (BC_7, PME, bidir, X, 63, 0, Z), " & "61 (BC_2, *, control, 0), " & "60 (BC_7, MDIO, bidir, X, 61, 0, PULL1)," & "59 (BC_2, *, control, 0), " & "58 (BC_7, MDC, bidir, X, 59, 0, PULL1)," & "57 (BC_2, *, control, 0), " & "56 (BC_7, LED3, bidir, X, 57, 0, PULL0)," & "55 (BC_2, *, control, 0), " & "54 (BC_7, LED2, bidir, X, 55, 0, PULL0)," & "53 (BC_2, *, control, 0), " & "52 (BC_7, LED1, bidir, X, 53, 0, PULL0)," & "51 (BC_2, *, control, 0), " & "50 (BC_7, LED0, bidir, X, 51, 0, PULL1)," & "49 (BC_2, *, control, 0), " & "48 (BC_7, TXER, bidir, X, 49, 0, Z), " & "47 (BC_2, *, control, 0), " & "46 (BC_7, TXD7, bidir, X, 47, 0, Z), " & "45 (BC_2, *, control, 0), " & "44 (BC_7, TXD6, bidir, X, 45, 0, Z), " & "43 (BC_2, *, control, 0), " & "42 (BC_7, TXD5, bidir, X, 43, 0, Z), " & "41 (BC_2, *, control, 0), " & "40 (BC_7, TXD4, bidir, X, 41, 0, Z), " & "39 (BC_2, *, control, 0), " & "38 (BC_7, TXCLK, bidir, X, 39, 0, PULL1)," & "37 (BC_2, *, control, 0), " & "36 (BC_7, TXD3, bidir, X, 37, 0, Z), " & "35 (BC_2, *, control, 0), " & "34 (BC_7, TXD2, bidir, X, 35, 0, Z), " & "33 (BC_2, *, control, 0), " & "32 (BC_7, TXD1, bidir, X, 33, 0, Z), " & "31 (BC_2, *, control, 0), " & "30 (BC_7, TXD0, bidir, X, 31, 0, Z), " & "29 (BC_2, *, control, 0), " & "28 (BC_7, TXEN, bidir, X, 29, 0, Z), " & "27 (BC_2, *, control, 0), " & "26 (BC_7, GTX_CLK, bidir, X, 27, 0, Z), " & "25 (BC_2, *, control, 0), " & "24 (BC_7, CRS, bidir, X, 25, 0, PULL0)," & "23 (BC_2, *, control, 0), " & "22 (BC_7, COL, bidir, X, 23, 0, PULL0)," & "21 (BC_2, *, control, 0), " & "20 (BC_7, RXER, bidir, X, 21, 0, PULL1)," & "19 (BC_2, *, control, 0), " & "18 (BC_7, RXD7, bidir, X, 19, 0, PULL1)," & "17 (BC_2, *, control, 0), " & "16 (BC_7, RXD6, bidir, X, 17, 0, PULL1)," & "15 (BC_2, *, control, 0), " & "14 (BC_7, RXD5, bidir, X, 15, 0, PULL0)," & "13 (BC_2, *, control, 0), " & "12 (BC_7, RXD4, bidir, X, 13, 0, PULL1)," & "11 (BC_2, *, control, 0), " & "10 (BC_7, RXC, bidir, X, 11, 0, Z), " & "9 (BC_2, *, control, 0), " & "8 (BC_7, RXD3, bidir, X, 9, 0, Z), " & "7 (BC_2, *, control, 0), " & "6 (BC_7, RXD2, bidir, X, 7, 0, Z), " & "5 (BC_2, *, control, 0), " & "4 (BC_7, RXD1, bidir, X, 5, 0, Z), " & "3 (BC_2, *, control, 0), " & "2 (BC_7, RXD0, bidir, X, 3, 0, Z), " & "1 (BC_2, *, control, 0), " & "0 (BC_7, RXDV, bidir, X, 1, 0, Z) "; end chip;