-- *************************************************************************** -- Quad-Core Intel(R) Xeon(R) Processor 5300 Series Boundary Scan Descriptor Language -- (BSDL) Model, Version 1.0. -- -- -- -- -- *************************************************************************** -- Information in this document is provided in connection with Intel products. -- No license, express or implied, by estoppel or otherwise, to any -- intellectual property rights is granted by this document. Except as -- provided in Intel's Terms and Conditions of Sale for such products, -- Intel assumes no liability whatsoever, and Intel disclaims any express or -- implied warranty, relating to sale and/or use of Intel products including -- liability or warranties relating to fitness for a particular purpose, -- merchantability, or infringement of any patent, copyright or other -- intellectual property right. Intel products are not intended for use in -- medical, life saving, or life sustaining applications. -- -- Intel may make changes to specifications and product descriptions at any -- time, without notice. -- -- The Quad-Core Intel(R) Xeon(R) Processor 5300 Series may contain design defects or errors -- known as errata which may cause the product to deviate from published -- specifications. Current characterized errata are available on request. -- -- Contact your local Intel sales office or your distributor to obtain the -- latest specifications and before placing your product order. -- -- Copyright (c) Intel Corporation 2006. Third-party brands and names are the -- property of their respective owners. -- *************************************************************************** -- entity QuadCoreXeon5300 is generic(PHYSICAL_PIN_MAP : string := "CTN_FCLGA6"); port ( A20MB : in bit; -- Compatibility - address 20 mask AB : inout bit_vector(35 downto 3); -- Address - address bus ADSB : inout bit; -- Request - address strobe ADSTBB : inout bit_vector(1 downto 0); -- Request - address bus strobe APB : inout bit_vector(1 downto 0); -- Address - address bus parity BCLK : in bit_vector(1 downto 0); -- Pwr/Clk - system bus clock BINITB : inout bit; -- Error - bus initialization error BNRB : inout bit; -- Arbitration - block next request BPMB : inout bit_vector(5 downto 0); -- Diagnostic - performance monitoring break points BPMB_2 : inout bit_vector(3 downto 0); -- Diagnostic - performance monitoring break points BPRIB : in bit; -- Arbitration - priority agent bus arbitration BRB : inout bit_vector(1 downto 0); -- Arbitration - symmetric agent bus arbitration BSEL : out bit_vector(2 downto 0); -- Pwr/Clk - selects processor input clock frequency COMP : linkage bit_vector(3 downto 0); -- Pwr/Clk - slew and impedence compensator DB : inout bit_vector(63 downto 0); -- Data - data bus DBRB : out bit; -- Diagnostic - data bus reset for debug interposer DBSYB : inout bit; -- Data - data bus busy DEFERB : in bit; -- Snoop - defer signal DBIB : inout bit_vector(3 downto 0); -- Data - dynamic data bus inversion DPB : inout bit_vector(3 downto 0); -- Data - data bus parity DRDYB : inout bit; -- Data - data phase data ready DSTBNB : inout bit_vector(3 downto 0); -- Data - data bus differential strobe DSTBPB : inout bit_vector(3 downto 0); -- Data - data bus differential strobe FERRB : out bit; -- Compatibility - floating point error, pending break event FORCEPRB : in bit; -- Pwr/Clk - force thermal control circuit GTLREF_ADD_MID : linkage bit; -- Analog Pin - signal reference level for input address bus GTLREF_ADD_END : linkage bit; -- Analog Pin - signal reference level for input address bus GTLREF_DATA_MID : linkage bit; -- Analog Pin - signal reference level for input data bus GTLREF_DATA_END : linkage bit; -- Analog Pin - signal reference level for input data bus HITB : inout bit; -- Snoop - snoop hit HITMB : inout bit; -- Snoop - snoop hit modified IERRB : out bit; -- Error - internal processor error IGNNEB : in bit; -- Compatibility - ignore numuric errors INITB : in bit; -- Exec Control - processor initialization LINT0 : in bit; -- APIC - local APIC interrupt, INTR LINT1 : in bit; -- APIC - local APIC interrupt, NMI LL_ID : out bit_vector(1 downto 0); -- Pwr/Clk - loadline slope select LOCKB : inout bit; -- Arbitration - locked transactions MCERRB : inout bit; -- Error - machine check error MS_ID : out bit_vector(1 downto 0); -- Pwr/Clk - market segment PECI : inout bit; -- Pwr/Clk - thermal monitor PROCHOTB : out bit; -- Pwr/Clk - thermal sensor PWRGOOD : in bit; -- Pwr/Clk - system power good REQB : inout bit_vector(4 downto 0); -- Request - request command RESETB : in bit; -- Control - system reset RSB : in bit_vector(2 downto 0); -- Response - response status RSPB : in bit; -- Response - response status parity RSVD : inout bit_vector(42 downto 0); -- Reserved - reserved SKTOCCB : out bit; -- Socket occupied SMIB : in bit; -- Compatibility - system management interrupt STPCLKB : in bit; -- Pwr/Clk - processor stop clock control TCK : in bit; -- Diagnostic - tap clock TDI : in bit; -- Diagnostic - tap data in TDO : out bit; -- Diagnostic - tap data out TESTHI00 : in bit; -- Reserved - reserved TESTHI01 : in bit; -- Reserved - reserved TESTHI02 : in bit; -- Reserved - reserved TESTHI03 : in bit; -- Reserved - reserved TESTHI04 : in bit; -- Reserved - reserved TESTHI05 : in bit; -- Reserved - reserved TESTHI06 : in bit; -- Reserved - reserved TESTHI07 : in bit; -- Reserved - reserved TESTHI10 : in bit; -- Reserved - reserved TESTHI11 : in bit; -- Reserved - reserved TESTIN1 : in bit; -- Reserved - reserved TESTIN2 : in bit; -- Reserved - reserved THERMTRIPB : out bit; -- Pwr/Clk - thermal sensor TMS : in bit; -- Diagnostic - tap mode select TRDYB : in bit; -- Response - target ready TRSTB : in bit; -- Diagnostic - tap reset VCC : linkage bit_vector(222 downto 0); -- Power VCCPLL : linkage bit; -- Power - VCC_DIE_SENSE : linkage bit; -- Power - Sense the die VCC power plane VCC_DIE_SENSE_2 : linkage bit; -- Power - Sense the die VCC power plane VID : out bit_vector(6 downto 1); -- Pwr/Clk - power supply voltage selection VID_SELECT : out bit; -- Power - proper VID table select VSS : linkage bit_vector(266 downto 0); -- Power VSS_DIE_SENSE : linkage bit; -- Power - Sense the die VSS power plane VSS_DIE_SENSE_2 : linkage bit; -- Power - Sense the die VSS power plane VTT : linkage bit_vector(21 downto 0); -- Power VTT_OUT : linkage bit_vector(1 downto 0); -- Power VTT_SEL : out bit ); use STD_1149_1_1994.all; use QuadCoreXeon5300_cells.all; attribute COMPONENT_CONFORMANCE of QuadCoreXeon5300 : entity is "STD_1149_1_1993" ; attribute PIN_MAP of QuadCoreXeon5300 : entity is PHYSICAL_PIN_MAP; constant CTN_FCLGA6 : PIN_MAP_STRING := -- Define PinOut "A20MB : K3," & "AB : ( AJ6, AJ5, AH5, AH4, AG5, AG4, AG6, AF4," & -- 35 to 28 " AF5, AB4, AC5, AB5, AA5, AD6, AA4, Y4," & -- 27 to 20 " Y6, W6, AB6, W5, V4, V5, U4, U5," & -- 19 to 12 " T4, U6, T5, R4, M4, L4, L5, P6," & -- 11 to 4 " M5)," & -- 3 to 3 "ADSB : D2," & "ADSTBB : ( AD5, R6)," & -- 1 to 0 "APB : ( U3, U2)," & -- 1 to 0 "BCLK : ( G28, F28)," & -- 1 to 0 "BINITB : AD3," & "BNRB : C2," & "BPMB : ( AG3, AF2, AG2, AD2, AJ1, AJ2)," & -- 5 to 0 "BPMB_2 : ( G3, G4, C9, G1)," & -- 3 to 0 "BPRIB : G8," & "BRB : ( H5, F3)," & -- 1 to 0 "BSEL : ( G30, H30, G29)," & -- 2 to 0 "COMP : ( R1, G2, T1, A13)," & -- 3 to 0 "DB : ( B22, A22, A19, B19, B21, C21, B18, A17," & -- 63 to 56 " B16, C18, B15, C14, C15, A14, D17, D20," & -- 55 to 48 " G22, D22, E22, G21, F21, E21, F20, E19," & -- 47 to 40 " E18, F18, F17, G17, G18, E16, E15, G16," & -- 39 to 32 " G15, F15, G14, F14, G13, E13, D13, F12," & -- 31 to 24 " F11, D10, E10, D7, E9, F9, F8, G9," & -- 23 to 16 " D11, C12, B12, D8, C11, B10, A11, A10," & -- 15 to 8 " A7, B7, B6, A5, C6, A4, C5, B4)," & -- 7 to 0 "DBRB : AC2," & "DBSYB : B2," & "DEFERB : G7," & "DBIB : ( C20, D19, G11, A8)," & -- 3 to 0 "DPB : ( J17, H16, H15, J16)," & -- 3 to 0 "DRDYB : C1," & "DSTBNB : ( A16, G20, G12, C8)," & -- 3 to 0 "DSTBPB : ( C17, G19, E12, B9)," & -- 3 to 0 "FERRB : R3," & "FORCEPRB : AK6," & "GTLREF_ADD_MID : F2," & "GTLREF_ADD_END : G10," & "GTLREF_DATA_END: H1," & "GTLREF_DATA_MID: H2," & "HITB : D4," & "HITMB : E4," & "IERRB : AB2," & "IGNNEB : N2," & "INITB : P3," & "LINT0 : K1," & "LINT1 : L1," & "LL_ID : ( AA2, V2)," & -- 1 to 0 "LOCKB : C3," & "MCERRB : AB3," & "MS_ID : ( V1, W1)," & -- 1 to 0 "PECI : G5," & "PROCHOTB : AL2," & "PWRGOOD : N1," & "REQB : ( J6, K6, M6, J5, K4)," & -- 4 to 0 "RESETB : G23," & "RSB : ( A3, F5, B3)," & -- 2 to 0 "RSPB : H4," & "RSVD : ( AK1, AH7, AJ7," & -- 42 to 40 " E1, F6, G6, J2, T2, Y1, Y3, AL1," & -- 39 to 32 " A23, AE3, AM2, AN5, AN6, B13, B23, C23," & -- 31 to 24 " AM6, N5, AE6, E29, E23, D14, E6, D16," & -- 23 to 16 " E24, AH2, AJ3, AK3, E7, D1, F23, F29," & -- 15 to 8 " A24, A20, E5, J3, AE4, AC4, P5, N4)," & -- 7 to 0 "SKTOCCB : AE8," & "SMIB : P2," & "STPCLKB : M3," & "TCK : AE1," & "TDI : AD1," & "TESTIN1 : W2," & "TDO : AF1," & "TESTIN2 : U1," & "TESTHI00 : F26," & "TESTHI01 : W3," & "TESTHI02 : F25," & "TESTHI03 : G25," & "TESTHI04 : G27," & "TESTHI05 : G26," & "TESTHI06 : G24," & "TESTHI07 : F24," & "TESTHI10 : P1," & "TESTHI11 : L2," & "THERMTRIPB : M2," & "TMS : AC1," & "TRDYB : E3," & "TRSTB : AG1," & "VCC : ( AA8, AB8, AC23,AC24,AC25,AC26,AC27,AC28," & " AC29,AC30, AC8,AD23,AD24,AD25,AD26,AD27," & " AD28,AD29,AD30,AD8,AE11, AE12,AE14,AE15," & " AE18,AE19,AE21,AE22,AE23,AE9,AF11, AF12," & " AF14,AF15,AF18,AF19, AF21,AF22,AF8, AF9," & " AG11,AG12,AG14,AG15,AG18,AG19,AG21,AG22," & " AG25,AG26,AG27,AG28,AG29,AG30, AG8, AG9," & " AH11,AH12,AH14,AH15,AH18,AH19,AH21,AH22," & " AH25,AH26,AH27,AH28,AH29,AH30, AH8, AH9," & " AJ11,AJ12,AJ14,AJ15,AJ18,AJ19,AJ21,AJ22," & " AJ25,AJ26, AJ8, AJ9,AK11,AK12,AK14,AK15," & " AK18,AK19,AK21,AK22,AK25,AK26, AK8, AK9," & " AL11,AL12,AL14,AL15,AL18,AL19,AL21,AL22," & " AL25,AL26,AL29,AL30, AL9,AM11,AM12,AM14," & " AM15,AM18,AM19,AM21,AM22,AM25,AM26,AM29," & " AM30, AM8, AM9,AN11,AN12,AN14,AN15,AN18," & " AN19,AN21,AN22,AN25,AN26, AN8, AN9, J10," & " J11, J12, J13, J14, J15, J18, J19, J20," & " J21, J22, J23, J24, J25, J26, J27, J28," & " J29, J30, J8, J9, K23, K24, K25, K26," & " K27, K28, K29, K30, K8, L8, M23, M24," & " M25, M26, M27, M28, M29, M30, M8, N23," & " N24, N25, N26, N27, N28, N29, N30, N8," & " P8, R8, T23, T24, T25, T26, T27, T28," & " T29, T30, T8, U23, U24, U25, U26, U27," & " U28, U29, U30, U8, V8, W23, W24, W25," & " W26, W27, W28, W29, W30, W8, Y23, Y24," & " Y25, Y26, Y27, Y28, Y29, Y30, Y8), " & "VCCPLL : D23," & "VCC_DIE_SENSE : AN3," & "VCC_DIE_SENSE_2: AL8," & "VID : ( AM5, AL4, AK4, AL6, AM3, AL5)," & -- 6 to 1 "VID_SELECT : AN7," & "VSS : ( A12, A15, A18, A2, A21, A6, A9," & " AA23,AA24,AA25,AA26,AA27,AA28,AA29, AA3," & " AA30, AA6, AA7, AB1,AB23,AB24,AB25,AB26," & " AB27,AB28,AB29,AB30, AB7, AC3, AC6, AC7," & " AD4, AD7,AE10,AE13,AE16,AE17, AE2,AE20," & " AE24,AE25,AE26,AE27,AE28,AE29,AE30, AE5," & " AE7,AF10,AF13,AF16,AF17,AF20,AF23,AF24," & " AF25,AF26,AF27,AF28,AF29, AF3,AF30, AF6," & " AF7,AG10,AG13,AG16,AG17,AG20,AG23,AG24," & " AG7, AH1,AH10,AH13,AH16,AH17,AH20,AH23," & " AH24, AH3, AH6,AJ10,AJ13,AJ16,AJ17,AJ20," & " AJ23,AJ24,AJ27,AJ28,AJ29,AJ30, AJ4,AK10," & " AK13,AK16,AK17, AK2,AK20,AK23,AK24,AK27," & " AK28,AK29,AK30, AK5, AK7,AL10,AL13,AL16," & " AL17,AL20,AL23,AL24,AL27,AL28, AL3, AM1," & " AM10,AM13,AM16,AM17,AM20,AM23,AM24,AM27," & " AM28, AM4, AM7, AN1,AN10,AN13,AN16,AN17," & " AN2,AN20,AN23,AN24, B1, B11, B14, B17," & " B20, B24, B5, B8, C10, C13, C16, C19," & " C22, C24, C4, C7, D12, D15, D18, D21," & " D24, D3, D5, D6, D9, E11, E14, E17," & " E2, E20, E25, E26, E27, E28, E8," & " F1, F10, F13, F16, F19, F22, F4, F7," & " H10, H11, H12, H13, H14, H17, H18, " & " H19, H20, H21, H22, H23, H24, H25, H26," & " H27, H28, H29, H3, H6, H7, H8, H9," & " J4, J7, K2, K5, K7, L23, L24, L25," & " L26, L27, L28, L29, L3, L30, L6, L7," & " M1, M7, N3, N6, N7, P23, P24, P25," & " P26, P27, P28, P29, P30, P4, P7, R2," & " R23, R24, R25, R26, R27, R28, R29, R30," & " R5, R7, T3, T6, T7, U7, V23," & " V24, V25, V26, V27, V28, V29, V3, V30," & " V6, V7, W4, W7, Y2, Y5, Y7), " & "VSS_DIE_SENSE : AN4," & "VSS_DIE_SENSE_2: AL7, " & "VTT_OUT : ( AA1, J1)," & "VTT_SEL : F27, " & "VTT : ( A25, A26, B25, B26, B27, B28, B29, B30," & " C25, C26, C27, C28, C29, C30, D25, D26," & " D27, D28, D29, D30, E30, F30) " ; -- -- Scan Port Identification -- attribute Tap_Scan_In of TDI : signal is true; attribute Tap_Scan_Mode of TMS : signal is true; attribute Tap_Scan_Out of TDO : signal is true; attribute Tap_Scan_Reset of TRSTB : signal is true; attribute Tap_Scan_Clock of TCK : signal is (16.0e6, both); attribute Instruction_Length of QuadCoreXeon5300: entity is 7; attribute Instruction_Opcode of QuadCoreXeon5300: entity is " EXTEST ( 0000000 ), " & " SAMPLE ( 0000001 ), " & " IDCODE ( 0000010 ), " & " CLAMP ( 0000100 ), " & " RUNBIST ( 0000111 ), " & " HIGHZ ( 0001000 ), " & " BYPASS ( 1111111 ), " & " Reserved ( 0000011, 0000101, 0000110, 0001001, 0001010, " & " 0001011, 0001100, 0001101, 0001110, 0001111, " & " 0010000, 0010001, 0010010, 0010011, 0010100, " & " 0010101, 0010110, 0010111, 0011000, 0011001, " & " 0011010, 0011011, 0011100, 0011101, 0011110, " & " 0011111, 0100000, 0100001, 0100010, 0100011, " & " 0100100, 0100101, 0100110, 0100111, 0101000, " & " 0101001, 0101010, 0101011, 0101100, 0101101, " & " 0101110, 0101111, 0110000, 0110001, 0110010, " & " 0110011, 0110100, 0110101, 0110110, 0110111, " & " 0111000, 0111001, 0111010, 0111011, 0111100, " & " 0111101, 0111110, 0111111, 1000000, 1000001, " & " 1000010, 1000011, 1000100, 1000101, 1000110, " & " 1000111, 1001000, 1001001, 1001010, 1001011, " & " 1001100, 1001101, 1001110, 1001111, 1010000, " & " 1010001, 1010010, 1010011, 1010100, 1010101, " & " 1010110, 1010111, 1011000, 1011001, 1011010, " & " 1011011, 1011100, 1011101, 1011110, 1011111, " & " 1100000, 1100001, 1100010, 1100011, 1100100, " & " 1100101, 1100110, 1100111, 1101000, 1101001, " & " 1101010, 1101011, 1101100, 1101101, 1101110, " & " 1101111, 1110000, 1110001, 1110010, 1110011, " & " 1110100, 1110101, 1110110, 1110111, 1111000, " & " 1111001, 1111010, 1111011, 1111100, 1111101, " & " 1111110 )" ; attribute Instruction_Capture of QuadCoreXeon5300: entity is "0000001"; attribute Instruction_Private of QuadCoreXeon5300: entity is "Reserved"; -- -- QuadCoreXeon5300 IDCODE Register -- attribute Idcode_Register of QuadCoreXeon5300: entity is "0111" & --version, B-3 step "0000000001011100" & --part number "00000001001" & --manufacturers identity "1"; --required by the standard -- -- QuadCoreXeon5300 Data Register Access -- attribute Register_Access of QuadCoreXeon5300: entity is "BOUNDARY (EXTEST, SAMPLE), " & "DEVICE_ID (IDCODE), " & "BYPASS (HIGHZ, BYPASS)"; -- -- QuadCoreXeon5300 Boundary Scan cells -- -- -- BC_N : Control or bidir -- -- QuadCoreXeon5300 Boundary Register Description -- Cell 0 is closest to TDO -- attribute BOUNDARY_LENGTH of QuadCoreXeon5300: entity is 173; attribute BOUNDARY_REGISTER of QuadCoreXeon5300: entity is -- num cell port function safe [ccell disval rslt] "0 (BC_N, *, control, 0 ),"& "1 (BC_N, BPMB(0), bidir, X, 0, 0, Z),"& "2 (BC_N, BPMB(2), bidir, X, 0, 0, Z),"& "3 (BC_N, BPMB(1), bidir, X, 0, 0, Z),"& "4 (BC_N, BPMB(4), bidir, X, 0, 0, Z),"& "5 (BC_N, BPMB(5), bidir, X, 0, 0, Z),"& "6 (BC_N, BPMB(3), bidir, X, 0, 0, Z),"& "7 (BC_N, BINITB, bidir, X, 0, 0, Z),"& "8 (BC_N, RSPB, input, 1 ),"& "9 (BC_N, APB(0), bidir, X, 0, 0, Z),"& "10 (BC_N, APB(1), bidir, X, 0, 0, Z),"& "11 (BC_N, AB(35), bidir, X, 0, 0, Z),"& "12 (BC_N, AB(34), bidir, X, 0, 0, Z),"& "13 (BC_N, AB(33), bidir, X, 0, 0, Z),"& "14 (BC_N, AB(32), bidir, X, 0, 0, Z),"& "15 (BC_N, AB(30), bidir, X, 0, 0, Z),"& "16 (BC_N, AB(28), bidir, X, 0, 0, Z),"& "17 (BC_N, AB(31), bidir, X, 0, 0, Z),"& "18 (BC_N, AB(29), bidir, X, 0, 0, Z),"& "19 (BC_N, RSVD(3), bidir, X, 0, 0, Z),"& "20 (BC_N, AB(27), bidir, X, 0, 0, Z),"& "21 (BC_N, AB(26), bidir, X, 0, 0, Z),"& "22 (BC_N, RSVD(2), bidir, X, 0, 0, Z),"& "23 (BC_N, ADSTBB(1), bidir, X, 0, 0, Z),"& "24 (BC_N, AB(21), bidir, X, 0, 0, Z),"& "25 (BC_N, AB(24), bidir, X, 0, 0, Z),"& "26 (BC_N, AB(20), bidir, X, 0, 0, Z),"& "27 (BC_N, AB(25), bidir, X, 0, 0, Z),"& "28 (BC_N, AB(18), bidir, X, 0, 0, Z),"& "29 (BC_N, AB(23), bidir, X, 0, 0, Z),"& "30 (BC_N, AB(19), bidir, X, 0, 0, Z),"& "31 (BC_N, AB(22), bidir, X, 0, 0, Z),"& "32 (BC_N, AB(17), bidir, X, 0, 0, Z),"& "33 (BC_N, AB(15), bidir, X, 0, 0, Z),"& "34 (BC_N, AB(16), bidir, X, 0, 0, Z),"& "35 (BC_N, AB(13), bidir, X, 0, 0, Z),"& "36 (BC_N, AB(11), bidir, X, 0, 0, Z),"& "37 (BC_N, AB(14), bidir, X, 0, 0, Z),"& "38 (BC_N, AB(12), bidir, X, 0, 0, Z),"& "39 (BC_N, AB(9), bidir, X, 0, 0, Z),"& "40 (BC_N, AB(8), bidir, X, 0, 0, Z),"& "41 (BC_N, AB(10), bidir, X, 0, 0, Z),"& "42 (BC_N, RSVD(0), bidir, X, 0, 0, Z),"& "43 (BC_N, RSVD(1), bidir, X, 0, 0, Z),"& "44 (BC_N, AB(7), bidir, X, 0, 0, Z),"& "45 (BC_N, ADSTBB(0), bidir, X, 0, 0, Z),"& "46 (BC_N, AB(4), bidir, X, 0, 0, Z),"& "47 (BC_N, REQB(0), bidir, X, 0, 0, Z),"& "48 (BC_N, AB(6), bidir, X, 0, 0, Z),"& "49 (BC_N, AB(5), bidir, X, 0, 0, Z),"& "50 (BC_N, REQB(2), bidir, X, 0, 0, Z),"& "51 (BC_N, AB(3), bidir, X, 0, 0, Z),"& "52 (BC_N, REQB(1), bidir, X, 0, 0, Z),"& "53 (BC_N, REQB(3), bidir, X, 0, 0, Z),"& "54 (BC_N, REQB(4), bidir, X, 0, 0, Z),"& "55 (BC_N, MCERRB, bidir, X, 0, 0, Z),"& "56 (BC_N, BRB(1), bidir, X, 0, 0, Z),"& "57 (BC_N, TRDYB, input, 1 ),"& "58 (BC_N, BRB(0), bidir, X, 0, 0, Z),"& "59 (BC_N, ADSB, bidir, X, 0, 0, Z),"& "60 (BC_N, DBSYB, bidir, X, 0, 0, Z),"& "61 (BC_N, BNRB, bidir, X, 0, 0, Z),"& "62 (BC_N, HITMB, bidir, X, 0, 0, Z),"& "63 (BC_N, RSB(1), input, 1 ),"& "64 (BC_N, RSB(0), input, 1 ),"& "65 (BC_N, HITB, bidir, X, 0, 0, Z),"& "66 (BC_N, LOCKB, bidir, X, 0, 0, Z),"& "67 (BC_N, DEFERB, input, 1 ),"& "68 (BC_N, BPRIB, input, 1 ),"& "69 (BC_N, RSB(2), input, 1 ),"& "70 (BC_N, RESETB, input, 1 ),"& "71 (BC_N, PECI, bidir, X, 0, 0, Z),"& "72 (BC_N, *, internal, 1 ),"& "73 (BC_N, IGNNEB, input, 1 ),"& "74 (BC_N, STPCLKB, input, 1 ),"& "75 (BC_N, INITB, input, 1 ),"& "76 (BC_N, SMIB, input, 1 ),"& "77 (BC_N, FERRB, output3, X, 0, 0, Z),"& "78 (BC_N, LINT0, input, 1 ),"& "79 (BC_N, TESTHI11, input, 1 ),"& "80 (BC_N, LINT1, input, 1 ),"& "81 (BC_N, TESTHI10, input, 1 ),"& "82 (BC_N, A20MB, input, 1 ),"& "83 (BC_N, THERMTRIPB, output3, X, 0, 0, Z),"& "84 (BC_N, BCLK(0), input, 1 ),"& "85 (BC_N, DB(62), bidir, X, 87, 0, Z),"& "86 (BC_N, DB(63), bidir, X, 87, 0, Z),"& "87 (BC_N, *, control, 0 ),"& "88 (BC_N, DB(59), bidir, X, 87, 0, Z),"& "89 (BC_N, DB(60), bidir, X, 87, 0, Z),"& "90 (BC_N, DB(61), bidir, X, 87, 0, Z),"& "91 (BC_N, DB(56), bidir, X, 87, 0, Z),"& "92 (BC_N, DBIB(3), bidir, X, 87, 0, Z),"& "93 (BC_N, DB(58), bidir, X, 87, 0, Z),"& "94 (BC_N, DB(57), bidir, X, 87, 0, Z),"& "95 (BC_N, DSTBNB(3), bidir, X, 87, 0, Z),"& "96 (BC_N, DSTBPB(3), bidir, X, 87, 0, Z),"& "97 (BC_N, DB(54), bidir, X, 87, 0, Z),"& "98 (BC_N, DB(50), bidir, X, 87, 0, Z),"& "99 (BC_N, DB(55), bidir, X, 87, 0, Z),"& "100 (BC_N, DB(53), bidir, X, 87, 0, Z),"& "101 (BC_N, DB(49), bidir, X, 87, 0, Z),"& "102 (BC_N, DB(48), bidir, X, 87, 0, Z),"& "103 (BC_N, DB(51), bidir, X, 87, 0, Z),"& "104 (BC_N, DB(52), bidir, X, 87, 0, Z),"& "105 (BC_N, DB(45), bidir, X, 87, 0, Z),"& "106 (BC_N, DB(47), bidir, X, 87, 0, Z),"& "107 (BC_N, DB(44), bidir, X, 87, 0, Z),"& "108 (BC_N, DB(43), bidir, X, 87, 0, Z),"& "109 (BC_N, DB(46), bidir, X, 87, 0, Z),"& "110 (BC_N, DB(42), bidir, X, 87, 0, Z),"& "111 (BC_N, DBIB(2), bidir, X, 87, 0, Z),"& "112 (BC_N, DB(41), bidir, X, 87, 0, Z),"& "113 (BC_N, DB(40), bidir, X, 87, 0, Z),"& "114 (BC_N, DSTBNB(2), bidir, X, 87, 0, Z),"& "115 (BC_N, DSTBPB(2), bidir, X, 87, 0, Z),"& "116 (BC_N, DB(35), bidir, X, 87, 0, Z),"& "117 (BC_N, DB(39), bidir, X, 87, 0, Z),"& "118 (BC_N, DB(38), bidir, X, 87, 0, Z),"& "119 (BC_N, DB(36), bidir, X, 87, 0, Z),"& "120 (BC_N, DB(34), bidir, X, 87, 0, Z),"& "121 (BC_N, DB(37), bidir, X, 87, 0, Z),"& "122 (BC_N, DB(32), bidir, X, 87, 0, Z),"& "123 (BC_N, DB(33), bidir, X, 87, 0, Z),"& "124 (BC_N, DPB(3), bidir, X, 87, 0, Z),"& "125 (BC_N, DPB(0), bidir, X, 87, 0, Z),"& "126 (BC_N, DPB(2), bidir, X, 87, 0, Z),"& "127 (BC_N, DPB(1), bidir, X, 87, 0, Z),"& "128 (BC_N, DB(31), bidir, X, 87, 0, Z),"& "129 (BC_N, DB(30), bidir, X, 87, 0, Z),"& "130 (BC_N, DB(28), bidir, X, 87, 0, Z),"& "131 (BC_N, DB(25), bidir, X, 87, 0, Z),"& "132 (BC_N, DB(26), bidir, X, 87, 0, Z),"& "133 (BC_N, DB(29), bidir, X, 87, 0, Z),"& "134 (BC_N, DB(22), bidir, X, 87, 0, Z),"& "135 (BC_N, DB(24), bidir, X, 87, 0, Z),"& "136 (BC_N, DB(27), bidir, X, 87, 0, Z),"& "137 (BC_N, DSTBNB(1), bidir, X, 87, 0, Z),"& "138 (BC_N, DSTBPB(1), bidir, X, 87, 0, Z),"& "139 (BC_N, DB(23), bidir, X, 87, 0, Z),"& "140 (BC_N, DB(21), bidir, X, 87, 0, Z),"& "141 (BC_N, DBIB(1), bidir, X, 87, 0, Z),"& "142 (BC_N, DB(19), bidir, X, 87, 0, Z),"& "143 (BC_N, DB(18), bidir, X, 87, 0, Z),"& "144 (BC_N, DB(20), bidir, X, 87, 0, Z),"& "145 (BC_N, DB(17), bidir, X, 87, 0, Z),"& "146 (BC_N, DB(16), bidir, X, 87, 0, Z),"& "147 (BC_N, DB(15), bidir, X, 87, 0, Z),"& "148 (BC_N, DB(12), bidir, X, 87, 0, Z),"& "149 (BC_N, DB(14), bidir, X, 87, 0, Z),"& "150 (BC_N, DB(13), bidir, X, 87, 0, Z),"& "151 (BC_N, DB(11), bidir, X, 87, 0, Z),"& "152 (BC_N, DB(9), bidir, X, 87, 0, Z),"& "153 (BC_N, DB(8), bidir, X, 87, 0, Z),"& "154 (BC_N, DB(10), bidir, X, 87, 0, Z),"& "155 (BC_N, DBIB(0), bidir, X, 87, 0, Z),"& "156 (BC_N, DSTBNB(0), bidir, X, 87, 0, Z),"& "157 (BC_N, DSTBPB(0), bidir, X, 87, 0, Z),"& "158 (BC_N, DB(6), bidir, X, 87, 0, Z),"& "159 (BC_N, DB(5), bidir, X, 87, 0, Z),"& "160 (BC_N, DB(7), bidir, X, 87, 0, Z),"& "161 (BC_N, DB(3), bidir, X, 87, 0, Z),"& "162 (BC_N, DB(2), bidir, X, 87, 0, Z),"& "163 (BC_N, DB(4), bidir, X, 87, 0, Z),"& "164 (BC_N, DB(1), bidir, X, 87, 0, Z),"& "165 (BC_N, *, internal, X ),"& "166 (BC_N, DB(0), bidir, X, 87, 0, Z),"& "167 (BC_N, DRDYB, bidir, X, 87, 0, Z),"& "168 (BC_N, RSVD(5), bidir, X, 87, 0, Z),"& "169 (BC_N, RSVD(4), bidir, X, 87, 0, Z),"& "170 (BC_N, PROCHOTB, output3, X, 87, 0, Z),"& "171 (BC_N, IERRB, output3, X, 87, 0, Z),"& "172 (BC_N, *, internal, X )"; end QuadCoreXeon5300;