-- M O T O R O L A S S D T J T A G S O F T W A R E -- BSDL File Generated: Wed Jan 5 15:58:16 2000 -- -- Revision History: -- entity DSP56F805FV80 is generic (PHYSICAL_PIN_MAP : string := "FV"); --144LQFP port ( TRST_B: in bit; TDO: out bit; TDI: in bit; TMS: in bit; TCK: in bit; D10: inout bit; D11: inout bit; D12: inout bit; D13: inout bit; D14: inout bit; D15: inout bit; A0: inout bit; POWER_I01: linkage bit; PWMB0: out bit; GROUND_IO1: linkage bit; PWMB1: out bit; A1: inout bit; PWMB2: out bit; A2: inout bit; PWMB3: out bit; A3: inout bit; A4: inout bit; A5: inout bit; PWMB4: out bit; A6: inout bit; PWMB5: out bit; A7: inout bit; ISB0: in bit; A8: inout bit; ISB1: in bit; A9: inout bit; ISB2: in bit; A10: inout bit; FAULTB0: in bit; A11: inout bit; FAULTB1: in bit; A12: inout bit; A13: inout bit; POWER_IO2: linkage bit; PS_B: inout bit; DS_B: inout bit; A14: inout bit; A15: inout bit; GROUND_IO2: linkage bit; WR_B: inout bit; RD_B: inout bit; IREQA_B: in bit; IREQB_B: in bit; FAULTB2: in bit; TCS: linkage bit; FAULTB3: in bit; TC0: inout bit; TC1: inout bit; TXD1: inout bit; VCAPC1: linkage bit; ISA0: in bit; POWER_IO3: linkage bit; ISA1: in bit; GROUND_IO3: linkage bit; ISA2: in bit; RXD1: inout bit; FAULTA0: in bit; MSCAN_TX: out bit; FAULTA1: in bit; MSCAN_RX: in bit; FAULTA2: in bit; FAULTA3: in bit; VRH: linkage bit; ANA0: linkage bit; ANA1: linkage bit; ANA2: linkage bit; ANA3: linkage bit; ANA4: linkage bit; ANA5: linkage bit; ANA6: linkage bit; ANA7: linkage bit; XTAL: linkage bit; EXTAL: linkage bit; VSSA_ADC1: linkage bit; VDDA_ADC1: linkage bit; POWER_IO7: linkage bit; VDDA_CORE1: linkage bit; GROUND_IO8: linkage bit; MPIOB0: inout bit; PHA0: inout bit; MPIOB1: inout bit; PHB0: inout bit; MPIOB2: inout bit; POWER_IO4: linkage bit; MPIOB3: inout bit; GROUND_IO4: linkage bit; MPIOB4: inout bit; INDX0: inout bit; MPIOB5: inout bit; HOME0: inout bit; MPIOB6: inout bit; PWMA0: out bit; MPIOB7: inout bit; PWMA1: out bit; MPIOD0: inout bit; PWMA2: out bit; MPIOD1: inout bit; PWMA3: out bit; MPIOD2: inout bit; PWMA4: out bit; PWMA5: out bit; TXD0: inout bit; RXD0: inout bit; XBOOT: in bit; RESET_B: in bit; DE_B: out bit; CLKO: out bit; TD0: inout bit; TD1: inout bit; POWER_IO5: linkage bit; TD2: inout bit; GROUND_IO5: linkage bit; TD3: inout bit; RSTO_B: out bit; SS_B: inout bit; MPIOD3: inout bit; MISO: inout bit; MPIOD4: inout bit; MOSI: inout bit; SCLK: inout bit; VCAPC2: linkage bit; MPIOD5: inout bit; D0: inout bit; VPP: linkage bit; D1: inout bit; D2: inout bit; INDX1: inout bit; POWER_IO6: linkage bit; PHB1: inout bit; GROUND_IO6: linkage bit; PHA1: inout bit; D3: inout bit; HOME1: inout bit; D4: inout bit; D5: inout bit; D6: inout bit; D7: inout bit; D8: inout bit; D9: inout bit); use STD_1149_1_1994.all; attribute COMPONENT_CONFORMANCE of DSP56F805FV80 : entity is "STD_1149_1_1993"; attribute PIN_MAP of DSP56F805FV80 : entity is PHYSICAL_PIN_MAP; constant FV : PIN_MAP_STRING := "D10: 1, " & "D11: 2, " & "D12: 3, " & "D13: 4, " & "D14: 5, " & "D15: 6, " & "A0: 7, " & "POWER_I01: 8, " & "PWMB0: 9, " & "GROUND_IO1: 10, " & "PWMB1: 11, " & "A1: 12, " & "PWMB2: 13, " & "A2: 14, " & "PWMB3: 15, " & "A3: 16, " & "A4: 17, " & "A5: 18, " & "PWMB4: 19, " & "A6: 20, " & "PWMB5: 21, " & "A7: 22, " & "ISB0: 23, " & "A8: 24, " & "ISB1: 25, " & "A9: 26, " & "ISB2: 27, " & "A10: 28, " & "FAULTB0: 29, " & "A11: 30, " & "FAULTB1: 31, " & "A12: 32, " & "A13: 33, " & "POWER_IO2: 34, " & "PS_B: 35, " & "DS_B: 36, " & "A14: 37, " & "A15: 38, " & "GROUND_IO2: 39, " & "WR_B: 40, " & "RD_B: 41, " & "IREQA_B: 42, " & "IREQB_B: 43, " & "FAULTB2: 44, " & "TCS: 45, " & "FAULTB3: 46, " & "TCK: 47, " & "TC0: 48, " & "TMS: 49, " & "TC1: 50, " & "TDI: 51, " & "TXD1: 52, " & "TDO: 53, " & "TRST_B: 54, " & "VCAPC1: 55, " & "ISA0: 56, " & "POWER_IO3: 57, " & "ISA1: 58, " & "GROUND_IO3: 59, " & "ISA2: 60, " & "RXD1: 61, " & "FAULTA0: 62, " & "MSCAN_TX: 63, " & "FAULTA1: 64, " & "MSCAN_RX: 65, " & "FAULTA2: 66, " & "FAULTA3: 67, " & "VRH: 68, " & "ANA0: 69, " & "ANA1: 70, " & "ANA2: 71, " & "ANA3: 72, " & "ANA4: 73, " & "ANA5: 74, " & "ANA6: 75, " & "ANA7: 76, " & "XTAL: 77, " & "EXTAL: 78, " & "VSSA_ADC1: 79, " & "VDDA_ADC1: 80, " & "POWER_IO7: 81, " & "VDDA_CORE1: 82, " & "GROUND_IO8: 83, " & "MPIOB0: 84, " & "PHA0: 85, " & "MPIOB1: 86, " & "PHB0: 87, " & "MPIOB2: 88, " & "POWER_IO4: 89, " & "MPIOB3: 90, " & "GROUND_IO4: 91, " & "MPIOB4: 92, " & "INDX0: 93, " & "MPIOB5: 94, " & "HOME0: 95, " & "MPIOB6: 96, " & "PWMA0: 97, " & "MPIOB7: 98, " & "PWMA1: 99, " & "MPIOD0: 100, " & "PWMA2: 101, " & "MPIOD1: 102, " & "PWMA3: 103, " & "MPIOD2: 104, " & "PWMA4: 105, " & "PWMA5: 106, " & "TXD0: 107, " & "RXD0: 108, " & "XBOOT: 109, " & "RESET_B: 110, " & "DE_B: 111, " & "CLKO: 112, " & "TD0: 113, " & "TD1: 114, " & "POWER_IO5: 115, " & "TD2: 116, " & "GROUND_IO5: 117, " & "TD3: 118, " & "RSTO_B: 119, " & "SS_B: 120, " & "MPIOD3: 121, " & "MISO: 122, " & "MPIOD4: 123, " & "MOSI: 124, " & "SCLK: 125, " & "VCAPC2: 126, " & "MPIOD5: 127, " & "D0: 128, " & "VPP: 129, " & "D1: 130, " & "D2: 131, " & "INDX1: 132, " & "POWER_IO6: 133, " & "PHB1: 134, " & "GROUND_IO6: 135, " & "PHA1: 136, " & "D3: 137, " & "HOME1: 138, " & "D4: 139, " & "D5: 140, " & "D6: 141, " & "D7: 142, " & "D8: 143, " & "D9: 144 "; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_RESET of TRST_B : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH); attribute INSTRUCTION_LENGTH of DSP56F805FV80 : entity is 4; attribute INSTRUCTION_OPCODE of DSP56F805FV80 : entity is "EXTEST (0000)," & "SAMPLE (0001)," & "IDCODE (0010)," & "CLAMP (0101)," & "HIGHZ (0100)," & "EXTEST_PULLUP (0011)," & "ENABLE_ONCE (0110)," & "DEBUG_REQUEST (0111)," & "BYPASS (1111)"; attribute INSTRUCTION_CAPTURE of DSP56F805FV80 : entity is "XX01"; attribute INSTRUCTION_PRIVATE of DSP56F805FV80 : entity is "ENABLE_ONCE, DEBUG_REQUEST "; attribute IDCODE_REGISTER of DSP56F805FV80 : entity is "00010001111100100101000000011101"; attribute REGISTER_ACCESS of DSP56F805FV80 : entity is "BOUNDARY (EXTEST_PULLUP)," & "BYPASS (ENABLE_ONCE," & "DEBUG_REQUEST)"; attribute BOUNDARY_LENGTH of DSP56F805FV80 : entity is 338; attribute BOUNDARY_REGISTER of DSP56F805FV80 : entity is -- num cell port func safe [ccell dis rslt] "337 (BC_1, D9, input, X)," & "336 (BC_1, D9, output3, X, 335, 1, Z)," & "335 (BC_1, *, control, 1)," & "334 (BC_1, *, internal, 1)," & "333 (BC_1, D8, input, X)," & "332 (BC_1, D8, output3, X, 331, 1, Z)," & "331 (BC_1, *, control, 1)," & "330 (BC_1, *, internal, 1)," & "329 (BC_1, D7, input, X)," & "328 (BC_1, D7, output3, X, 327, 1, Z)," & "327 (BC_1, *, control, 1)," & "326 (BC_1, *, internal, 1)," & "325 (BC_1, D6, input, X)," & "324 (BC_1, D6, output3, X, 323, 1, Z)," & "323 (BC_1, *, control, 1)," & "322 (BC_1, *, internal, 1)," & "321 (BC_1, D5, input, X)," & "320 (BC_1, D5, output3, X, 319, 1, Z)," & "319 (BC_1, *, control, 1)," & "318 (BC_1, *, internal, 1)," & -- num cell port func safe [ccell dis rslt] "317 (BC_1, D4, input, X)," & "316 (BC_1, D4, output3, X, 315, 1, Z)," & "315 (BC_1, *, control, 1)," & "314 (BC_1, *, internal, 1)," & "313 (BC_1, HOME1, input, X)," & "312 (BC_1, HOME1, output3, X, 311, 1, Z)," & "311 (BC_1, *, control, 1)," & "310 (BC_1, *, internal, 1)," & "309 (BC_1, D3, input, X)," & "308 (BC_1, D3, output3, X, 307, 1, Z)," & "307 (BC_1, *, control, 1)," & "306 (BC_1, *, internal, 1)," & "305 (BC_1, PHA1, input, X)," & "304 (BC_1, PHA1, output3, X, 303, 1, Z)," & "303 (BC_1, *, control, 1)," & "302 (BC_1, *, internal, 1)," & "301 (BC_1, PHB1, input, X)," & "300 (BC_1, PHB1, output3, X, 299, 1, Z)," & "299 (BC_1, *, control, 1)," & "298 (BC_1, *, internal, 1)," & -- num cell port func safe [ccell dis rslt] "297 (BC_1, INDX1, input, X)," & "296 (BC_1, INDX1, output3, X, 295, 1, Z)," & "295 (BC_1, *, control, 1)," & "294 (BC_1, *, internal, 1)," & "293 (BC_1, D2, input, X)," & "292 (BC_1, D2, output3, X, 291, 1, Z)," & "291 (BC_1, *, control, 1)," & "290 (BC_1, *, internal, 1)," & "289 (BC_1, D1, input, X)," & "288 (BC_1, D1, output3, X, 287, 1, Z)," & "287 (BC_1, *, control, 1)," & "286 (BC_1, *, internal, 1)," & "285 (BC_1, D0, input, X)," & "284 (BC_1, D0, output3, X, 283, 1, Z)," & "283 (BC_1, *, control, 1)," & "282 (BC_1, *, internal, 1)," & "281 (BC_1, MPIOD5, input, X)," & "280 (BC_1, MPIOD5, output3, X, 279, 1, Z)," & "279 (BC_1, *, control, 1)," & "278 (BC_1, *, internal, 1)," & -- num cell port func safe [ccell dis rslt] "277 (BC_1, SCLK, input, X)," & "276 (BC_1, SCLK, output3, X, 275, 1, Z)," & "275 (BC_1, *, control, 1)," & "274 (BC_1, *, internal, 1)," & "273 (BC_1, MOSI, input, X)," & "272 (BC_1, MOSI, output3, X, 271, 1, Z)," & "271 (BC_1, *, control, 1)," & "270 (BC_1, *, internal, 1)," & "269 (BC_1, MPIOD4, input, X)," & "268 (BC_1, MPIOD4, output3, X, 267, 1, Z)," & "267 (BC_1, *, control, 1)," & "266 (BC_1, *, internal, 1)," & "265 (BC_1, MISO, input, X)," & "264 (BC_1, MISO, output3, X, 263, 1, Z)," & "263 (BC_1, *, control, 1)," & "262 (BC_1, *, internal, 1)," & "261 (BC_1, MPIOD3, input, X)," & "260 (BC_1, MPIOD3, output3, X, 259, 1, Z)," & "259 (BC_1, *, control, 1)," & "258 (BC_1, *, internal, 1)," & -- num cell port func safe [ccell dis rslt] "257 (BC_1, SS_B, input, X)," & "256 (BC_1, SS_B, output3, X, 255, 1, Z)," & "255 (BC_1, *, control, 1)," & "254 (BC_1, *, internal, 1)," & "253 (BC_1, RSTO_B, output3, X, 252, 1, Z)," & "252 (BC_1, *, control, 1)," & "251 (BC_1, TD3, input, X)," & "250 (BC_1, TD3, output3, X, 249, 1, Z)," & "249 (BC_1, *, control, 1)," & "248 (BC_1, *, internal, 1)," & "247 (BC_1, TD2, input, X)," & "246 (BC_1, TD2, output3, X, 245, 1, Z)," & "245 (BC_1, *, control, 1)," & "244 (BC_1, *, internal, 1)," & "243 (BC_1, TD1, input, X)," & "242 (BC_1, TD1, output3, X, 241, 1, Z)," & "241 (BC_1, *, control, 1)," & "240 (BC_1, *, internal, 1)," & "239 (BC_1, TD0, input, X)," & "238 (BC_1, TD0, output3, X, 237, 1, Z)," & -- num cell port func safe [ccell dis rslt] "237 (BC_1, *, control, 1)," & "236 (BC_1, *, internal, 1)," & "235 (BC_1, CLKO, output3, X, 234, 1, Z)," & "234 (BC_1, *, control, 1)," & "233 (BC_1, DE_B, output3, X, 232, 1, Z)," & "232 (BC_1, *, control, 1)," & "231 (BC_1, RESET_B, input, X)," & "230 (BC_1, XBOOT, input, X)," & "229 (BC_1, RXD0, input, X)," & "228 (BC_1, RXD0, output3, X, 227, 1, Z)," & "227 (BC_1, *, control, 1)," & "226 (BC_1, *, internal, 1)," & "225 (BC_1, TXD0, input, X)," & "224 (BC_1, TXD0, output3, X, 223, 1, Z)," & "223 (BC_1, *, control, 1)," & "222 (BC_1, *, internal, 1)," & "221 (BC_1, PWMA5, output3, X, 220, 1, Z)," & "220 (BC_1, *, control, 1)," & "219 (BC_1, PWMA4, output3, X, 218, 1, Z)," & "218 (BC_1, *, control, 1)," & -- num cell port func safe [ccell dis rslt] "217 (BC_1, MPIOD2, input, X)," & "216 (BC_1, MPIOD2, output3, X, 215, 1, Z)," & "215 (BC_1, *, control, 1)," & "214 (BC_1, *, internal, 1)," & "213 (BC_1, PWMA3, output3, X, 212, 1, Z)," & "212 (BC_1, *, control, 1)," & "211 (BC_1, MPIOD1, input, X)," & "210 (BC_1, MPIOD1, output3, X, 209, 1, Z)," & "209 (BC_1, *, control, 1)," & "208 (BC_1, *, internal, 1)," & "207 (BC_1, PWMA2, output3, X, 206, 1, Z)," & "206 (BC_1, *, control, 1)," & "205 (BC_1, MPIOD0, input, X)," & "204 (BC_1, MPIOD0, output3, X, 203, 1, Z)," & "203 (BC_1, *, control, 1)," & "202 (BC_1, *, internal, 1)," & "201 (BC_1, PWMA1, output3, X, 200, 1, Z)," & "200 (BC_1, *, control, 1)," & "199 (BC_1, MPIOB7, input, X)," & "198 (BC_1, MPIOB7, output3, X, 197, 1, Z)," & -- num cell port func safe [ccell dis rslt] "197 (BC_1, *, control, 1)," & "196 (BC_1, *, internal, 1)," & "195 (BC_1, PWMA0, output3, X, 194, 1, Z)," & "194 (BC_1, *, control, 1)," & "193 (BC_1, MPIOB6, input, X)," & "192 (BC_1, MPIOB6, output3, X, 191, 1, Z)," & "191 (BC_1, *, control, 1)," & "190 (BC_1, *, internal, 1)," & "189 (BC_1, HOME0, input, X)," & "188 (BC_1, HOME0, output3, X, 187, 1, Z)," & "187 (BC_1, *, control, 1)," & "186 (BC_1, *, internal, 1)," & "185 (BC_1, MPIOB5, input, X)," & "184 (BC_1, MPIOB5, output3, X, 183, 1, Z)," & "183 (BC_1, *, control, 1)," & "182 (BC_1, *, internal, 1)," & "181 (BC_1, INDX0, input, X)," & "180 (BC_1, INDX0, output3, X, 179, 1, Z)," & "179 (BC_1, *, control, 1)," & "178 (BC_1, *, internal, 1)," & -- num cell port func safe [ccell dis rslt] "177 (BC_1, MPIOB4, input, X)," & "176 (BC_1, MPIOB4, output3, X, 175, 1, Z)," & "175 (BC_1, *, control, 1)," & "174 (BC_1, *, internal, 1)," & "173 (BC_1, MPIOB3, input, X)," & "172 (BC_1, MPIOB3, output3, X, 171, 1, Z)," & "171 (BC_1, *, control, 1)," & "170 (BC_1, *, internal, 0)," & "169 (BC_1, MPIOB2, input, X)," & "168 (BC_1, MPIOB2, output3, X, 167, 1, Z)," & "167 (BC_1, *, control, 1)," & "166 (BC_1, *, internal, 1)," & "165 (BC_1, PHB0, input, X)," & "164 (BC_1, PHB0, output3, X, 163, 1, Z)," & "163 (BC_1, *, control, 1)," & "162 (BC_1, *, internal, 1)," & "161 (BC_1, MPIOB1, input, X)," & "160 (BC_1, MPIOB1, output3, X, 159, 1, Z)," & "159 (BC_1, *, control, 1)," & "158 (BC_1, *, internal, 1)," & -- num cell port func safe [ccell dis rslt] "157 (BC_1, PHA0, input, X)," & "156 (BC_1, PHA0, output3, X, 155, 1, Z)," & "155 (BC_1, *, control, 1)," & "154 (BC_1, *, internal, 1)," & "153 (BC_1, MPIOB0, input, X)," & "152 (BC_1, MPIOB0, output3, X, 151, 1, Z)," & "151 (BC_1, *, control, 1)," & "150 (BC_1, *, internal, 1)," & "149 (BC_1, FAULTA3, input, X)," & "148 (BC_1, FAULTA2, input, X)," & "147 (BC_1, MSCAN_RX, input, X)," & "146 (BC_1, FAULTA1, input, X)," & "145 (BC_1, MSCAN_TX, output2, 1, 145, 1, Weak1)," & "144 (BC_1, FAULTA0, input, X)," & "143 (BC_1, RXD1, input, X)," & "142 (BC_1, RXD1, output3, X, 141, 1, Z)," & "141 (BC_1, *, control, 1)," & "140 (BC_1, *, internal, 1)," & "139 (BC_1, ISA2, input, X)," & "138 (BC_1, ISA1, input, X)," & -- num cell port func safe [ccell dis rslt] "137 (BC_1, ISA0, input, X)," & "136 (BC_1, TXD1, input, X)," & "135 (BC_1, TXD1, output3, X, 134, 1, Z)," & "134 (BC_1, *, control, 1)," & "133 (BC_1, *, internal, 1)," & "132 (BC_1, TC1, input, X)," & "131 (BC_1, TC1, output3, X, 130, 1, Z)," & "130 (BC_1, *, control, 1)," & "129 (BC_1, *, internal, 1)," & "128 (BC_1, TC0, input, X)," & "127 (BC_1, TC0, output3, X, 126, 1, Z)," & "126 (BC_1, *, control, 1)," & "125 (BC_1, *, internal, 1)," & "124 (BC_1, FAULTB3, input, X)," & "123 (BC_1, FAULTB2, input, X)," & "122 (BC_1, IREQB_B, input, X)," & "121 (BC_1, IREQA_B, input, X)," & "120 (BC_1, RD_B, input, X)," & "119 (BC_1, RD_B, output3, X, 118, 1, Z)," & "118 (BC_1, *, control, 1)," & -- num cell port func safe [ccell dis rslt] "117 (BC_1, *, internal, 1)," & "116 (BC_1, WR_B, input, X)," & "115 (BC_1, WR_B, output3, X, 114, 1, Z)," & "114 (BC_1, *, control, 1)," & "113 (BC_1, *, internal, 1)," & "112 (BC_1, A15, input, X)," & "111 (BC_1, A15, output3, X, 110, 1, Z)," & "110 (BC_1, *, control, 1)," & "109 (BC_1, *, internal, 1)," & "108 (BC_1, A14, input, X)," & "107 (BC_1, A14, output3, X, 106, 1, Z)," & "106 (BC_1, *, control, 1)," & "105 (BC_1, *, internal, 1)," & "104 (BC_1, DS_B, input, X)," & "103 (BC_1, DS_B, output3, X, 102, 1, Z)," & "102 (BC_1, *, control, 1)," & "101 (BC_1, *, internal, 1)," & "100 (BC_1, PS_B, input, X)," & " 99 (BC_1, PS_B, output3, X, 98, 1, Z)," & " 98 (BC_1, *, control, 1)," & -- num cell port func safe [ccell dis rslt] " 97 (BC_1, *, internal, 1)," & " 96 (BC_1, A13, input, X)," & " 95 (BC_1, A13, output3, X, 94, 1, Z)," & " 94 (BC_1, *, control, 1)," & " 93 (BC_1, *, internal, 1)," & " 92 (BC_1, A12, input, X)," & " 91 (BC_1, A12, output3, X, 90, 1, Z)," & " 90 (BC_1, *, control, 1)," & " 89 (BC_1, *, internal, 1)," & " 88 (BC_1, FAULTB1, input, X)," & " 87 (BC_1, A11, input, X)," & " 86 (BC_1, A11, output3, X, 85, 1, Z)," & " 85 (BC_1, *, control, 1)," & " 84 (BC_1, *, internal, 1)," & " 83 (BC_1, FAULTB0, input, X)," & " 82 (BC_1, A10, input, X)," & " 81 (BC_1, A10, output3, X, 80, 1, Z)," & " 80 (BC_1, *, control, 1)," & " 79 (BC_1, *, internal, 1)," & " 78 (BC_1, ISB2, input, X)," & -- num cell port func safe [ccell dis rslt] " 77 (BC_1, A9, input, X)," & " 76 (BC_1, A9, output3, X, 75, 1, Z)," & " 75 (BC_1, *, control, 1)," & " 74 (BC_1, *, internal, 1)," & " 73 (BC_1, ISB1, input, X)," & " 72 (BC_1, A8, input, X)," & " 71 (BC_1, A8, output3, X, 70, 1, Z)," & " 70 (BC_1, *, control, 1)," & " 69 (BC_1, *, internal, 1)," & " 68 (BC_1, ISB0, input, X)," & " 67 (BC_1, A7, input, X)," & " 66 (BC_1, A7, output3, X, 65, 1, Z)," & " 65 (BC_1, *, control, 1)," & " 64 (BC_1, *, internal, 1)," & " 63 (BC_1, PWMB5, output3, X, 62, 1, Z)," & " 62 (BC_1, *, control, 1)," & " 61 (BC_1, A6, input, X)," & " 60 (BC_1, A6, output3, X, 59, 1, Z)," & " 59 (BC_1, *, control, 1)," & " 58 (BC_1, *, internal, 1)," & -- num cell port func safe [ccell dis rslt] " 57 (BC_1, PWMB4, output3, X, 56, 1, Z)," & " 56 (BC_1, *, control, 1)," & " 55 (BC_1, A5, input, X)," & " 54 (BC_1, A5, output3, X, 53, 1, Z)," & " 53 (BC_1, *, control, 1)," & " 52 (BC_1, *, internal, 1)," & " 51 (BC_1, A4, input, X)," & " 50 (BC_1, A4, output3, X, 49, 1, Z)," & " 49 (BC_1, *, control, 1)," & " 48 (BC_1, *, internal, 1)," & " 47 (BC_1, A3, input, X)," & " 46 (BC_1, A3, output3, X, 45, 1, Z)," & " 45 (BC_1, *, control, 1)," & " 44 (BC_1, *, internal, 1)," & " 43 (BC_1, PWMB3, output3, X, 42, 1, Z)," & " 42 (BC_1, *, control, 1)," & " 41 (BC_1, A2, input, X)," & " 40 (BC_1, A2, output3, X, 39, 1, Z)," & " 39 (BC_1, *, control, 1)," & " 38 (BC_1, *, internal, 1)," & -- num cell port func safe [ccell dis rslt] " 37 (BC_1, PWMB2, output3, X, 36, 1, Z)," & " 36 (BC_1, *, control, 1)," & " 35 (BC_1, A1, input, X)," & " 34 (BC_1, A1, output3, X, 33, 1, Z)," & " 33 (BC_1, *, control, 1)," & " 32 (BC_1, *, internal, 1)," & " 31 (BC_1, PWMB1, output3, X, 30, 1, Z)," & " 30 (BC_1, *, control, 1)," & " 29 (BC_1, PWMB0, output3, X, 28, 1, Z)," & " 28 (BC_1, *, control, 1)," & " 27 (BC_1, A0, input, X)," & " 26 (BC_1, A0, output3, X, 25, 1, Z)," & " 25 (BC_1, *, control, 1)," & " 24 (BC_1, *, internal, 1)," & " 23 (BC_1, D15, input, X)," & " 22 (BC_1, D15, output3, X, 21, 1, Z)," & " 21 (BC_1, *, control, 1)," & " 20 (BC_1, *, internal, 1)," & " 19 (BC_1, D14, input, X)," & " 18 (BC_1, D14, output3, X, 17, 1, Z)," & -- num cell port func safe [ccell dis rslt] " 17 (BC_1, *, control, 1)," & " 16 (BC_1, *, internal, 1)," & " 15 (BC_1, D13, input, X)," & " 14 (BC_1, D13, output3, X, 13, 1, Z)," & " 13 (BC_1, *, control, 1)," & " 12 (BC_1, *, internal, 1)," & " 11 (BC_1, D12, input, X)," & " 10 (BC_1, D12, output3, X, 9, 1, Z)," & " 9 (BC_1, *, control, 1)," & " 8 (BC_1, *, internal, 1)," & " 7 (BC_1, D11, input, X)," & " 6 (BC_1, D11, output3, X, 5, 1, Z)," & " 5 (BC_1, *, control, 1)," & " 4 (BC_1, *, internal, 1)," & " 3 (BC_1, D10, input, X)," & " 2 (BC_1, D10, output3, X, 1, 1, Z)," & " 1 (BC_1, *, control, 1)," & " 0 (BC_1, *, internal, 1)"; end DSP56F805FV80;