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BSDL File: DSP56F827 Download View details  


-- M O T O R O L A   S S D T   J T A G   S O F T W A R E
-- BSDL File Generated: Mon Apr 16 16:07:13 2001
--
-- Revision History:
--

entity DSP56F827 is 
	generic (PHYSICAL_PIN_MAP : string := "P128LQFP");

	port (POWER_IO10:	linkage	bit;
	     GROUND_IO10:	linkage	bit;
	              D7:	inout	bit;
	              D8:	inout	bit;
	              D9:	inout	bit;
	             D10:	inout	bit;
	             D11:	inout	bit;
	             D12:	inout	bit;
	             D13:	inout	bit;
	             D14:	inout	bit;
	             D15:	inout	bit;
	            RD_B:	inout	bit;
	            WR_B:	inout	bit;
	            DS_B:	inout	bit;
	            PS_B:	inout	bit;
	     POWER_CORE3:	linkage	bit;
	    GROUND_CORE3:	linkage	bit;
	              A0:	inout	bit;
	              A1:	inout	bit;
	              A2:	inout	bit;
	              A3:	inout	bit;
	              A4:	inout	bit;
	              A5:	inout	bit;
	              A6:	inout	bit;
	              A7:	inout	bit;
	       POWER_IO7:	linkage	bit;
	      GROUND_IO7:	linkage	bit;
	              A8:	inout	bit;
	              A9:	inout	bit;
	             A10:	inout	bit;
	             A11:	inout	bit;
	             A12:	inout	bit;
	             A13:	inout	bit;
	             A14:	inout	bit;
	             A15:	inout	bit;
	           XBOOT:	in	bit;
	         IREQA_B:	in	bit;
	            DE_B:	out	bit;
	         RESET_B:	in	bit;
	             TCS:	linkage	bit;
	             TCK:	in	bit;
	          TRST_B:	in	bit;
	             TMS:	in	bit;
	             TDO:	out	bit;
	             TDI:	in	bit;
	         IREQB_B:	in	bit;
	            STCK:	inout	bit;
	            STFS:	inout	bit;
	             STD:	inout	bit;
	            SRCK:	inout	bit;
	            SRFS:	inout	bit;
	             SRD:	inout	bit;
	       POWER_IO5:	linkage	bit;
	            CLKO:	out	bit;
	      GROUND_IO5:	linkage	bit;
	           EXTAL:	linkage	bit;
	            XTAL:	linkage	bit;
	        VSSA_PLL:	linkage	bit;
	        VDDA_PLL:	linkage	bit;
	        VSSA_ADC:	linkage	bit;
	          VREFLO:	linkage	bit;
	           VREFP:	linkage	bit;
	           VREFN:	linkage	bit;
	          VREFHI:	linkage	bit;
	         VREFMID:	linkage	bit;
	        VDDA_ADC:	linkage	bit;
	            ANA0:	linkage	bit;
	            ANA1:	linkage	bit;
	            ANA2:	linkage	bit;
	            ANA3:	linkage	bit;
	            ANA4:	linkage	bit;
	            ANA5:	linkage	bit;
	            ANA6:	linkage	bit;
	            ANA7:	linkage	bit;
	            ANA8:	linkage	bit;
	            ANA9:	linkage	bit;
	    GROUND_CORE2:	linkage	bit;
	     POWER_CORE2:	linkage	bit;
	       POWER_IO3:	linkage	bit;
	      GROUND_IO3:	linkage	bit;
	            PCS2:	out	bit;
	            PCS3:	out	bit;
	            PCS4:	out	bit;
	            PCS5:	out	bit;
	            PCS6:	out	bit;
	            PCS7:	out	bit;
	             VPP:	linkage	bit;
	          MPIOD7:	inout	bit;
	          MPIOD6:	inout	bit;
	          MPIOD5:	inout	bit;
	          MPIOD4:	inout	bit;
	          MPIOD3:	inout	bit;
	          MPIOD2:	inout	bit;
	          MPIOD1:	inout	bit;
	          MPIOD0:	inout	bit;
	            SS_B:	inout	bit;
	            MISO:	inout	bit;
	            MOSI:	inout	bit;
	            SCLK:	inout	bit;
	            RXD2:	inout	bit;
	            TXD2:	inout	bit;
	            RXD1:	in	bit;
	            TXD1:	inout	bit;
	            RXD0:	inout	bit;
	            TXD0:	inout	bit;
	             TA3:	inout	bit;
	             TA2:	inout	bit;
	             TA1:	inout	bit;
	             TA0:	inout	bit;
	       POWER_IO1:	linkage	bit;
	      GROUND_IO1:	linkage	bit;
	    GROUND_CORE1:	linkage	bit;
	     POWER_CORE1:	linkage	bit;
	          MPIOB7:	inout	bit;
	          MPIOB6:	inout	bit;
	          MPIOB5:	inout	bit;
	          MPIOB4:	inout	bit;
	          MPIOB3:	inout	bit;
	          MPIOB2:	inout	bit;
	          MPIOB1:	inout	bit;
	          MPIOB0:	inout	bit;
	              D0:	inout	bit;
	              D1:	inout	bit;
	              D2:	inout	bit;
	              D3:	inout	bit;
	              D4:	inout	bit;
	              D5:	inout	bit;
	              D6:	inout	bit);

	use STD_1149_1_1994.all;

	attribute COMPONENT_CONFORMANCE of DSP56F827 : entity is "STD_1149_1_1993";

	attribute PIN_MAP of DSP56F827 : entity is PHYSICAL_PIN_MAP;

	constant P128LQFP : PIN_MAP_STRING := 
	"D4:             1, " &
	"D5:             2, " &
	"D6:             3, " &
	"POWER_IO10:     4, " &
	"GROUND_IO10:    5, " &
	"D7:             6, " &
	"D8:             7, " &
	"D9:             8, " &
	"D10:            9, " &
	"D11:            10, " &
	"D12:            11, " &
	"D13:            12, " &
	"D14:            13, " &
	"D15:            14, " &
	"RD_B:           15, " &
	"WR_B:           16, " &
	"DS_B:           17, " &
	"PS_B:           18, " &
	"POWER_CORE3:    19, " &
	"GROUND_CORE3:   20, " &
	"A0:             21, " &
	"A1:             22, " &
	"A2:             23, " &
	"A3:             24, " &
	"A4:             25, " &
	"A5:             26, " &
	"A6:             27, " &
	"A7:             28, " &
	"POWER_IO7:      29, " &
	"GROUND_IO7:     30, " &
	"A8:             31, " &
	"A9:             32, " &
	"A10:            33, " &
	"A11:            34, " &
	"A12:            35, " &
	"A13:            36, " &
	"A14:            37, " &
	"A15:            38, " &
	"XBOOT:          39, " &
	"IREQA_B:        40, " &
	"DE_B:           41, " &
	"RESET_B:        42, " &
	"TCS:            43, " &
	"TCK:            44, " &
	"TRST_B:         45, " &
	"TMS:            46, " &
	"TDO:            47, " &
	"TDI:            48, " &
	"IREQB_B:        49, " &
	"STCK:           50, " &
	"STFS:           51, " &
	"STD:            52, " &
	"SRCK:           53, " &
	"SRFS:           54, " &
	"SRD:            55, " &
	"POWER_IO5:      56, " &
	"CLKO:           57, " &
	"GROUND_IO5:     58, " &
	"EXTAL:          59, " &
	"XTAL:           60, " &
	"VSSA_PLL:       61, " &
	"VDDA_PLL:       62, " &
	"VSSA_ADC:       63, " &
	"VREFLO:         64, " &
	"VREFP:          65, " &
	"VREFN:          66, " &
	"VREFHI:         67, " &
	"VREFMID:        68, " &
	"VDDA_ADC:       69, " &
	"ANA0:           70, " &
	"ANA1:           71, " &
	"ANA2:           72, " &
	"ANA3:           73, " &
	"ANA4:           74, " &
	"ANA5:           75, " &
	"ANA6:           76, " &
	"ANA7:           77, " &
	"ANA8:           78, " &
	"ANA9:           79, " &
	"GROUND_CORE2:   80, " &
	"POWER_CORE2:    81, " &
	"POWER_IO3:      82, " &
	"GROUND_IO3:     83, " &
	"PCS2:           84, " &
	"PCS3:           85, " &
	"PCS4:           86, " &
	"PCS5:           87, " &
	"PCS6:           88, " &
	"PCS7:           89, " &
	"VPP:            90, " &
	"MPIOD7:         91, " &
	"MPIOD6:         92, " &
	"MPIOD5:         93, " &
	"MPIOD4:         94, " &
	"MPIOD3:         95, " &
	"MPIOD2:         96, " &
	"MPIOD1:         97, " &
	"MPIOD0:         98, " &
	"SS_B:           99, " &
	"MISO:           100, " &
	"MOSI:           101, " &
	"SCLK:           102, " &
	"RXD2:           103, " &
	"TXD2:           104, " &
	"RXD1:           105, " &
	"TXD1:           106, " &
	"RXD0:           107, " &
	"TXD0:           108, " &
	"TA3:            109, " &
	"TA2:            110, " &
	"TA1:            111, " &
	"TA0:            112, " &
	"POWER_IO1:      113, " &
	"GROUND_IO1:     114, " &
	"GROUND_CORE1:   115, " &
	"POWER_CORE1:    116, " &
	"MPIOB7:         117, " &
	"MPIOB6:         118, " &
	"MPIOB5:         119, " &
	"MPIOB4:         120, " &
	"MPIOB3:         121, " &
	"MPIOB2:         122, " &
	"MPIOB1:         123, " &
	"MPIOB0:         124, " &
	"D0:             125, " &
	"D1:             126, " &
	"D2:             127, " &
	"D3:             128 "; 

	attribute TAP_SCAN_IN    of     TDI : signal is true;
	attribute TAP_SCAN_OUT   of     TDO : signal is true;
	attribute TAP_SCAN_MODE  of     TMS : signal is true;
	attribute TAP_SCAN_RESET of  TRST_B : signal is true;
	attribute TAP_SCAN_CLOCK of     TCK : signal is (20.0e6, BOTH);

	attribute INSTRUCTION_LENGTH of DSP56F827 : entity is 4;

	attribute INSTRUCTION_OPCODE of DSP56F827 : entity is 
	   "EXTEST       	(0000)," &
	   "SAMPLE       	(0001)," &
	   "IDCODE       	(0010)," &
	   "CLAMP        	(0101)," &
	   "HIGHZ        	(0100)," &
	   "EXTEST_PULLUP	(0011)," &
	   "ENABLE_ONCE  	(0110)," &
	   "DEBUG_REQUEST	(0111)," &
	   "BYPASS       	(1111)";

	attribute INSTRUCTION_CAPTURE of DSP56F827 : entity is "XX01";
	attribute INSTRUCTION_PRIVATE of DSP56F827 : entity is 
	   "ENABLE_ONCE, DEBUG_REQUEST ";

	attribute IDCODE_REGISTER   of DSP56F827 : entity is 
	   "00000001111100111011000000011101";

	attribute REGISTER_ACCESS of DSP56F827 : entity is 
           "BOUNDARY   (EXTEST_PULLUP)," &
	   "BYPASS   (ENABLE_ONCE, DEBUG_REQUEST)" ;

	attribute BOUNDARY_LENGTH of DSP56F827 : entity is 305;

	attribute BOUNDARY_REGISTER of DSP56F827 : entity is 
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   "304     (BC_1, D7,            input,         X)," &
	   "303     (BC_1, D7,            output3,       X,      302,   1,   PULL1)," &
	   "302     (BC_1, *,             control,       1)," &
	   "301     (BC_1, *,             internal,      1)," &
	   "300     (BC_1, D8,            input,         X)," &
	   "299     (BC_1, D8,            output3,       X,      298,   1,   PULL1)," &
	   "298     (BC_1, *,             control,       1)," &
	   "297     (BC_1, *,             internal,      1)," &
	   "296     (BC_1, D9,            input,         X)," &
	   "295     (BC_1, D9,            output3,       X,     294,   1,   PULL1)," &
	   "294    (BC_1, *,             control,       1)," &
	   "293    (BC_1, *,             internal,      1)," &
	   "292    (BC_1, D10,           input,         X)," &
	   "291    (BC_1, D10,           output3,       X,     290,   1,   PULL1)," &
	   "290    (BC_1, *,             control,       1)," &
	   "289    (BC_1, *,             internal,      1)," &
	   "288    (BC_1, D11,           input,         X)," &
	   "287    (BC_1, D11,           output3,       X,     286,   1,   PULL1)," &
	   "286    (BC_1, *,             control,       1)," &
	   "285    (BC_1, *,             internal,      1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   "284    (BC_1, D12,           input,         X)," &
	   "283    (BC_1, D12,           output3,       X,     282,   1,   PULL1)," &
	   "282    (BC_1, *,             control,       1)," &
	   "281    (BC_1, *,             internal,      1)," &
	   "280    (BC_1, D13,           input,         X)," &
	   "279    (BC_1, D13,           output3,       X,     278,   1,   PULL1)," &
	   "278    (BC_1, *,             control,       1)," &
	   "277    (BC_1, *,             internal,      1)," &
	   "276    (BC_1, D14,           input,         X)," &
	   "275    (BC_1, D14,           output3,       X,     274,   1,   PULL1)," &
	   "274    (BC_1, *,             control,       1)," &
	   "273    (BC_1, *,             internal,      1)," &
	   "272    (BC_1, D15,           input,         X)," &
	   "271    (BC_1, D15,           output3,       X,     270,   1,   PULL1)," &
	   "270    (BC_1, *,             control,       1)," &
	   "269    (BC_1, *,             internal,      1)," &
	   "268    (BC_1, RD_B,          input,         X)," &
	   "267    (BC_1, RD_B,          output3,       X,     266,   1,   PULL1)," &
	   "266    (BC_1, *,             control,       1)," &
	   "265    (BC_1, *,             internal,      1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   "264    (BC_1, WR_B,          input,         X)," &
	   "263    (BC_1, WR_B,          output3,       X,     262,   1,   PULL1)," &
	   "262    (BC_1, *,             control,       1)," &
	   "261    (BC_1, *,             internal,      1)," &
	   "260    (BC_1, DS_B,          input,         X)," &
	   "259    (BC_1, DS_B,          output3,       X,     258,   1,   PULL1)," &
	   "258    (BC_1, *,             control,       1)," &
	   "257    (BC_1, *,             internal,      1)," &
	   "256    (BC_1, PS_B,          input,         X)," &
	   "255    (BC_1, PS_B,          output3,       X,     254,   1,   PULL1)," &
	   "254    (BC_1, *,             control,       1)," &
	   "253    (BC_1, *,             internal,      1)," &
	   "252    (BC_1, A0,            input,         X)," &
	   "251    (BC_1, A0,            output3,       X,     250,   1,   PULL1)," &
	   "250    (BC_1, *,             control,       1)," &
	   "249    (BC_1, *,             internal,      1)," &
	   "248    (BC_1, A1,            input,         X)," &
	   "247    (BC_1, A1,            output3,       X,     246,   1,   PULL1)," &
	   "246    (BC_1, *,             control,       1)," &
	   "245    (BC_1, *,             internal,      1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   "244    (BC_1, A2,            input,         X)," &
	   "243    (BC_1, A2,            output3,       X,     242,   1,   PULL1)," &
	   "242    (BC_1, *,             control,       1)," &
	   "241    (BC_1, *,             internal,      1)," &
	   "240    (BC_1, A3,            input,         X)," &
	   "239    (BC_1, A3,            output3,       X,     238,   1,   PULL1)," &
	   "238    (BC_1, *,             control,       1)," &
	   "237    (BC_1, *,             internal,      1)," &
	   "236    (BC_1, A4,            input,         X)," &
	   "235    (BC_1, A4,            output3,       X,     234,   1,   PULL1)," &
	   "234    (BC_1, *,             control,       1)," &
	   "233    (BC_1, *,             internal,      1)," &
	   "232    (BC_1, A5,            input,         X)," &
	   "231    (BC_1, A5,            output3,       X,     230,   1,   PULL1)," &
	   "230    (BC_1, *,             control,       1)," &
	   "229    (BC_1, *,             internal,      1)," &
	   "228    (BC_1, A6,            input,         X)," &
	   "227    (BC_1, A6,            output3,       X,     226,   1,   PULL1)," &
	   "226    (BC_1, *,             control,       1)," &
	   "225    (BC_1, *,             internal,      1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   "224    (BC_1, A7,            input,         X)," &
	   "223    (BC_1, A7,            output3,       X,     222,   1,   PULL1)," &
	   "222    (BC_1, *,             control,       1)," &
	   "221    (BC_1, *,             internal,      1)," &
	   "220    (BC_1, A8,            input,         X)," &
	   "219    (BC_1, A8,            output3,       X,     218,   1,   PULL1)," &
	   "218    (BC_1, *,             control,       1)," &
	   "217    (BC_1, *,             internal,      1)," &
	   "216    (BC_1, A9,            input,         X)," &
	   "215    (BC_1, A9,            output3,       X,     214,   1,   PULL1)," &
	   "214    (BC_1, *,             control,       1)," &
	   "213    (BC_1, *,             internal,      1)," &
	   "212    (BC_1, A10,           input,         X)," &
	   "211    (BC_1, A10,           output3,       X,     210,   1,   PULL1)," &
	   "210    (BC_1, *,             control,       1)," &
	   "209    (BC_1, *,             internal,      1)," &
	   "208    (BC_1, A11,           input,         X)," &
	   "207    (BC_1, A11,           output3,       X,     206,   1,   PULL1)," &
	   "206    (BC_1, *,             control,       1)," &
	   "205    (BC_1, *,             internal,      1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   "204   (BC_1, A12,           input,         X)," &
	   "203   (BC_1, A12,           output3,       X,    202,   1,   PULL1)," &
	   "202   (BC_1, *,             control,       1)," &
	   "201   (BC_1, *,             internal,      1)," &
	   "200   (BC_1, A13,           input,         X)," &
	   "199   (BC_1, A13,           output3,       X,    198,   1,   PULL1)," &
	   "198   (BC_1, *,             control,       1)," &
	   "197   (BC_1, *,             internal,      1)," &
	   "196   (BC_1, A14,           input,         X)," &
	   "195   (BC_1, A14,           output3,       X,    194,   1,   PULL1)," &
	   "194   (BC_1, *,             control,       1)," &
	   "193   (BC_1, *,             internal,      1)," &
	   "192   (BC_1, A15,           input,         X)," &
	   "191   (BC_1, A15,           output3,       X,    190,   1,   PULL1)," &
	   "190   (BC_1, *,             control,       1)," &
	   "189   (BC_1, *,             internal,      1)," &
	   "188   (BC_1, XBOOT,         input,         X)," &
	   "187   (BC_1, IREQA_B,       input,         X)," &
	   "186   (BC_1, DE_B,          output3,       X,    185,   1,   Z)," &
	   "185   (BC_1, *,             control,       1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   "184   (BC_1, RESET_B,       input,         X)," &
	   "183   (BC_1, IREQB_B,       input,         X)," &
	   "182   (BC_1, STCK,          input,         X)," &
	   "181   (BC_1, STCK,          output3,       X,    180,   1,   PULL1)," &
	   "180   (BC_1, *,             control,       1)," &
	   "179   (BC_1, *,             internal,      1)," &
	   "178   (BC_1, STFS,          input,         X)," &
	   "177   (BC_1, STFS,          output3,       X,    176,   1,   PULL1)," &
	   "176   (BC_1, *,             control,       1)," &
	   "175   (BC_1, *,             internal,      1)," &
	   "174   (BC_1, STD,           input,         X)," &
	   "173   (BC_1, STD,           output3,       X,    172,   1,   PULL1)," &
	   "172   (BC_1, *,             control,       1)," &
	   "171   (BC_1, *,             internal,      1)," &
	   "170   (BC_1, SRCK,          input,         X)," &
	   "169   (BC_1, SRCK,          output3,       X,    168,   1,   PULL1)," &
	   "168   (BC_1, *,             control,       1)," &
	   "167   (BC_1, *,             internal,      1)," &
	   "166   (BC_1, SRFS,          input,         X)," &
	   "165   (BC_1, SRFS,          output3,       X,    164,   1,   PULL1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   "164   (BC_1, *,             control,       1)," &
	   "163   (BC_1, *,             internal,      1)," &
	   "162   (BC_1, SRD,           input,         X)," &
	   "161   (BC_1, SRD,           output3,       X,    160,   1,   PULL1)," &
	   "160   (BC_1, *,             control,       1)," &
	   "159   (BC_1, *,             internal,      1)," &
	   "158   (BC_1, CLKO,          output3,       X,    157,   1,   Z)," &
	   "157   (BC_1, *,             control,       1)," &
	   "156   (BC_1, PCS2,          output3,       X,    155,   1,   Z)," &
	   "155   (BC_1, *,             control,       1)," &
	   "154   (BC_1, PCS3,          output3,       X,    153,   1,   Z)," &
	   "153   (BC_1, *,             control,       1)," &
	   "152   (BC_1, PCS4,          output3,       X,    151,   1,   Z)," &
	   "151   (BC_1, *,             control,       1)," &
	   "150   (BC_1, PCS5,          output3,       X,    149,   1,   Z)," &
	   "149   (BC_1, *,             control,       1)," &
	   "148   (BC_1, PCS6,          output3,       X,    147,   1,   Z)," &
	   "147   (BC_1, *,             control,       1)," &
	   "146   (BC_1, PCS7,          output3,       X,    145,   1,   Z)," &
	   "145   (BC_1, *,             control,       1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   "144   (BC_1, MPIOD7,        input,         X)," &
	   "143   (BC_1, MPIOD7,        output3,       X,    142,   1,   PULL1)," &
	   "142   (BC_1, *,             control,       1)," &
	   "141   (BC_1, *,             internal,      1)," &
	   "140   (BC_1, MPIOD6,        input,         X)," &
	   "139   (BC_1, MPIOD6,        output3,       X,    138,   1,   PULL1)," &
	   "138   (BC_1, *,             control,       1)," &
	   "137   (BC_1, *,             internal,      1)," &
	   "136   (BC_1, MPIOD5,        input,         X)," &
	   "135   (BC_1, MPIOD5,        output3,       X,    134,   1,   PULL1)," &
	   "134   (BC_1, *,             control,       1)," &
	   "133   (BC_1, *,             internal,      1)," &
	   "132   (BC_1, MPIOD4,        input,         X)," &
	   "131   (BC_1, MPIOD4,        output3,       X,    130,   1,   PULL1)," &
	   "130   (BC_1, *,             control,       1)," &
	   "129   (BC_1, *,             internal,      1)," &
	   "128   (BC_1, MPIOD3,        input,         X)," &
	   "127   (BC_1, MPIOD3,        output3,       X,    126,   1,   PULL1)," &
	   "126   (BC_1, *,             control,       1)," &
	   "125   (BC_1, *,             internal,      1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   "124   (BC_1, MPIOD2,        input,         X)," &
	   "123   (BC_1, MPIOD2,        output3,       X,    122,   1,   PULL1)," &
	   "122   (BC_1, *,             control,       1)," &
	   "121   (BC_1, *,             internal,      1)," &
	   "120   (BC_1, MPIOD1,        input,         X)," &
	   "119   (BC_1, MPIOD1,        output3,       X,    118,   1,   PULL1)," &
	   "118   (BC_1, *,             control,       1)," &
	   "117   (BC_1, *,             internal,      1)," &
	   "116   (BC_1, MPIOD0,        input,         X)," &
	   "115   (BC_1, MPIOD0,        output3,       X,    114,   1,   PULL1)," &
	   "114   (BC_1, *,             control,       1)," &
	   "113   (BC_1, *,             internal,      1)," &
	   "112   (BC_1, SS_B,          input,         X)," &
	   "111   (BC_1, SS_B,          output3,       X,    110,   1,   PULL1)," &
	   "110   (BC_1, *,             control,       1)," &
	   "109   (BC_1, *,             internal,      1)," &
	   "108   (BC_1, MISO,          input,         X)," &
	   "107   (BC_1, MISO,          output3,       X,    106,   1,   PULL1)," &
	   "106   (BC_1, *,             control,       1)," &
	   "105   (BC_1, *,             internal,      1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   "104   (BC_1, MOSI,          input,         X)," &
	   "103   (BC_1, MOSI,          output3,       X,    102,   1,   PULL1)," &
	   "102   (BC_1, *,             control,       1)," &
	   "101   (BC_1, *,             internal,      1)," &
	   "100   (BC_1, SCLK,          input,         X)," &
	   " 99   (BC_1, SCLK,          output3,       X,     98,   1,   PULL1)," &
	   " 98   (BC_1, *,             control,       1)," &
	   " 97   (BC_1, *,             internal,      1)," &
	   " 96   (BC_1, RXD2,          input,         X)," &
	   " 95   (BC_1, RXD2,          output3,       X,     94,   1,   PULL1)," &
	   " 94   (BC_1, *,             control,       1)," &
	   " 93   (BC_1, *,             internal,      1)," &
	   " 92   (BC_1, TXD2,          input,         X)," &
	   " 91   (BC_1, TXD2,          output3,       X,     90,   1,   PULL1)," &
	   " 90   (BC_1, *,             control,       1)," &
	   " 89   (BC_1, *,             internal,      1)," &
	   " 88   (BC_1, RXD1,          input,         X)," &
	   " 87   (BC_1, TXD1,          input,         X)," &
	   " 86   (BC_1, TXD1,          output3,       X,     85,   1,   PULL1)," &
	   " 85   (BC_1, *,             control,       1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   " 84   (BC_1, *,             internal,      1)," &
	   " 83   (BC_1, RXD0,          input,         X)," &
	   " 82   (BC_1, RXD0,          output3,       X,     81,   1,   PULL1)," &
	   " 81   (BC_1, *,             control,       1)," &
	   " 80   (BC_1, *,             internal,      1)," &
	   " 79   (BC_1, TXD0,          input,         X)," &
	   " 78   (BC_1, TXD0,          output3,       X,     77,   1,   PULL1)," &
	   " 77   (BC_1, *,             control,       1)," &
	   " 76   (BC_1, *,             internal,      1)," &
	   " 75   (BC_1, TA3,           input,         X)," &
	   " 74   (BC_1, TA3,           output3,       X,     73,   1,   PULL1)," &
	   " 73   (BC_1, *,             control,       1)," &
	   " 72   (BC_1, *,             internal,      1)," &
	   " 71   (BC_1, TA2,           input,         X)," &
	   " 70   (BC_1, TA2,           output3,       X,     69,   1,   PULL1)," &
	   " 69   (BC_1, *,             control,       1)," &
	   " 68   (BC_1, *,             internal,      1)," &
	   " 67   (BC_1, TA1,           input,         X)," &
	   " 66   (BC_1, TA1,           output3,       X,     65,   1,   PULL1)," &
	   " 65   (BC_1, *,             control,       1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   " 64   (BC_1, *,             internal,      1)," &
	   " 63   (BC_1, TA0,           input,         X)," &
	   " 62   (BC_1, TA0,           output3,       X,     61,   1,   PULL1)," &
	   " 61   (BC_1, *,             control,       1)," &
	   " 60   (BC_1, *,             internal,      1)," &
	   " 59   (BC_1, MPIOB7,        input,         X)," &
	   " 58   (BC_1, MPIOB7,        output3,       X,     57,   1,   PULL1)," &
	   " 57   (BC_1, *,             control,       1)," &
	   " 56   (BC_1, *,             internal,      1)," &
	   " 55   (BC_1, MPIOB6,        input,         X)," &
	   " 54   (BC_1, MPIOB6,        output3,       X,     53,   1,   PULL1)," &
	   " 53   (BC_1, *,             control,       1)," &
	   " 52   (BC_1, *,             internal,      1)," &
	   " 51   (BC_1, MPIOB5,        input,         X)," &
	   " 50   (BC_1, MPIOB5,        output3,       X,     49,   1,   PULL1)," &
	   " 49   (BC_1, *,             control,       1)," &
	   " 48   (BC_1, *,             internal,      1)," &
	   " 47   (BC_1, MPIOB4,        input,         X)," &
	   " 46   (BC_1, MPIOB4,        output3,       X,     45,   1,   PULL1)," &
	   " 45   (BC_1, *,             control,       1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   " 44   (BC_1, *,             internal,      0)," &
	   " 43   (BC_1, MPIOB3,        input,         X)," &
	   " 42   (BC_1, MPIOB3,        output3,       X,     41,   1,   PULL1)," &
	   " 41   (BC_1, *,             control,       1)," &
	   " 40   (BC_1, *,             internal,      1)," &
	   " 39   (BC_1, MPIOB2,        input,         X)," &
	   " 38   (BC_1, MPIOB2,        output3,       X,     37,   1,   PULL1)," &
	   " 37   (BC_1, *,             control,       1)," &
	   " 36   (BC_1, *,             internal,      1)," &
	   " 35   (BC_1, MPIOB1,        input,         X)," &
	   " 34   (BC_1, MPIOB1,        output3,       X,     33,   1,   PULL1)," &
	   " 33   (BC_1, *,             control,       1)," &
	   " 32   (BC_1, *,             internal,      1)," &
	   " 31   (BC_1, MPIOB0,        input,         X)," &
	   " 30   (BC_1, MPIOB0,        output3,       X,     29,   1,   PULL1)," &
	   " 29   (BC_1, *,             control,       1)," &
	   " 28   (BC_1, *,             internal,      1)," &
	   " 27   (BC_1, D0,            input,         X)," &
	   " 26   (BC_1, D0,            output3,       X,     25,   1,   PULL1)," &
	   " 25   (BC_1, *,             control,       1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   " 24   (BC_1, *,             internal,      1)," &
	   " 23   (BC_1, D1,            input,         X)," &
	   " 22   (BC_1, D1,            output3,       X,     21,   1,   PULL1)," &
	   " 21   (BC_1, *,             control,       1)," &
	   " 20   (BC_1, *,             internal,      1)," &
	   " 19   (BC_1, D2,            input,         X)," &
	   " 18   (BC_1, D2,            output3,       X,     17,   1,   PULL1)," &
	   " 17   (BC_1, *,             control,       1)," &
	   " 16   (BC_1, *,             internal,      1)," &
	   " 15   (BC_1, D3,            input,         X)," &
	   " 14   (BC_1, D3,            output3,       X,     13,   1,   PULL1)," &
	   " 13   (BC_1, *,             control,       1)," &
	   " 12   (BC_1, *,             internal,      1)," &
	   " 11   (BC_1, D4,            input,         X)," &
	   " 10   (BC_1, D4,            output3,       X,      9,   1,   PULL1)," &
	   "  9   (BC_1, *,             control,       1)," &
	   "  8   (BC_1, *,             internal,      1)," &
	   "  7   (BC_1, D5,            input,         X)," &
	   "  6   (BC_1, D5,            output3,       X,      5,   1,   PULL1)," &
	   "  5   (BC_1, *,             control,       1)," &
	-- num    cell   port    func          safe [ccell  dis  rslt]
	   "  4   (BC_1, *,             internal,      1)," &
	   "  3   (BC_1, D6,            input,         X)," &
	   "  2   (BC_1, D6,            output3,       X,      1,   1,   PULL1)," &
	   "  1   (BC_1, *,             control,       1)," &
	   "  0   (BC_1, *,             internal,      1)";

end DSP56F827;

This library contains 7716 BSDL files (for 6087 distinct entities) from 66 vendors
Last BSDL model (chip) was added on Oct 17, 2017 16:06
info@bsdl.info