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BSDL File: TSI310 Download View details  


--  STD_1149_1_1994    VHDL Package and Package Body
--
-- Company:  Integrated Device Technology, Inc.
-- Title: Tsi310 PCI/x * PCI/x Bridge 304 ball H-PBGA BSDL
-- BSDL Version 1994
-- File No.: 35B6000_BS001_06
-- Security level : Public	Release status: Formal Issue
-- Group ownership: Apps Eng	Revision Date:  AUG 04 2004
-- Generated by	  : Andre Pirnat
-- Released by    : Andre Pirnat
-- Revision history:
--
--    status    rev no   Date		Reviser/Group		 Description
--   --------   ------	 --------	------------------  --------------
--    Formal	01 	 Apr 30/03 	Apps Eng	    initial creation
--    formal    02       July 30/03     Apps Eng          - correct control cell assignments
--                                                        - correct part number attribute
--    Formal    05       Aug 4/04       Apps Eng          - Correct cell format
--    Formal    06       Sep 3/09       Apps Eng          - Updated with IDT formatting
--
-- Give pin mapping declarations
--
--------------------------------------------------------------------------
--
-- Edited by Anthony Sparks, JTAG Technologies, Inc. 8/1/03
--
-- Added internal cell at bit position 0 of boundary register
-- Renumbered cells - increment by 1
-- changed boundary length to 377
--
--------------------------------------------------------------------------
entity tsi310 is 
    generic (PHYSICAL_PIN_MAP : string := "HPBGA_304_23x23");
-- Port List

port (
P_AD		 : inout	bit_vector(0 to 63);
P_CBE		 : inout	bit_vector(0 to 7);
P_CLK		 : in		bit;
P_DEVSEL	 : inout	bit;
P_FRAME		 : inout	bit;
P_GNT		 : in		bit;
P_IDSEL 	 : in		bit;
P_IRDY		 : inout	bit;
P_LOCK		 : in		bit;
P_DRVR_MODE	 : in		bit;
P_PAR		 : inout	bit;
P_PAR64		 : inout	bit;
P_CFG_BUSY	 : in		bit;
P_PERR		 : inout	bit;
P_REQ64		 : inout	bit;
P_REQ		 : out		bit;
P_RST		 : in		bit;
P_SERR		 : out		bit;
P_STOP		 : inout	bit;
P_TRDY		 : inout	bit;
S_ACK64		 : inout	bit;
S_REQ64		 : inout	bit;
S_AD		 : inout	bit_vector(0 to 63);
S_CBE		 : inout	bit_vector(0 to 7);
S_CLK		 : in		bit;
S_CLK_STABLE     : in		bit;
S_DEVSEL	 : inout	bit;
S_FRAME		 : inout	bit;
S_GNT1REQ	 : out		bit;
S_GNT	 	 : out		bit_vector(2 to 6);
S_INT_ARB_EN     : in		bit;
S_IRDY	 	 : inout	bit;
S_LOCK		 : inout	bit;
S_DRVR_MODE	 : in		bit;
S_PAR		 : inout	bit;
S_PAR64		 : inout	bit;
S_PCIXCAP	 : in		bit;
S_PCIXCAP_PU     : out		bit;
S_PERR	 	 : inout	bit;
S_REQ1GNT	 : in		bit;
S_REQ	 	 : in		bit_vector(2 to 6);
S_RST		 : out	 	bit;
S_SEL100	 : in		bit;
S_SERR	 	 : in		bit;
S_STOP	 	 : inout	bit;
S_TRDY	 	 : inout	bit;
BAR_EN	 	 : in		bit;
RESERVED2	 : in		bit;
XCLK_OUT	 : out		bit;
S_IDSEL		 : in		bit;
P_64_BIT_DEVICE	 : in	        bit;
IDSEL_REROUTE_EN : in	        bit;
OPAQUE_EN	 : in		bit;
T_MODECTL        : linkage      bit;
T_RI             : linkage      bit;
T_DI1            : linkage      bit;
T_DI2            : linkage      bit;
TEST_CEO	 : linkage      bit;
VDD		 : linkage      bit_vector (1 to 16);
VDD2		 : linkage      bit_vector (1 to 26);
GND		 : linkage      bit_vector (1 to 48);
P_VDDA	         : linkage      bit;
S_VDDA           : linkage      bit;
JTG_TCK		 : in		bit;
JTG_TDI		 : in		bit;
JTG_TDO		 : out		bit;
JTG_TRST_b	 : in		bit;
JTG_TMS		 : in		bit
);

   use STD_1149_1_1994.all;

-- use LVS_BSCAN_CELLS.all;   -- don't know what this is for!

   attribute COMPONENT_CONFORMANCE of tsi310: entity is "STD_1149_1_1993";


--Pin mappings

    attribute PIN_MAP of tsi310: entity is PHYSICAL_PIN_MAP;

    constant HPBGA_304_23x23: PIN_MAP_STRING:= 
"GND        : (A1,A6,A10,A11,A14,A18,A23,B2,B22,C3,C21,D4,D8,D12,D16,D20,F1,F23, " &
              "H4,H20,K1,K23,L23,M4,M20,N1,P1,P23,T4,T20,V1,V23,Y4,Y8,Y12,Y16,Y20, " &
	      "AA3,AA21,AB2,AB22,AC1,AC6,AC10,AC13,AC14,AC18,AC23),"&
"P_AD       : (B13,C13,B14,C15,A19,B16,C16,A20,B17,C17,C19,D18,F22,F20,G22,B20, " &
               "G21,H22,H21,J22,J21,K22,D23,K21,E23,K20,G23,L22,L21,M22,M21,J23,L1, " &
	           "J1,J2,H1,G1,J3,E1,H2,H3,G3,F2,B1,F3,E3,F4,D2,C2,B5,B6,D6,B7,C7,B3, " &
	           "B8,A3,B9,C9,B10,A4,C10,D10,B11)," &
"P_CBE      : (A13,B18,D14,A15,A5,C11,B12,A7) , " &
"VDD2       : (A8,A12,A22,C5,D5,D7,D17,D19,E4,E20,G4,G20,H23,M1,T1, " &
               "U4,U20,W4,W20,Y5,Y7,Y17,Y19,AC2,AC12,AC16), " &
"VDD        : (D9,D11,D13,D15,J4,J20,L4,L20,N4,N20,R4,R20,Y9,Y11,Y13,Y15) , " &
"S_AD       : (AA9,AB9,AC9,AC11,AB11,AC15,AA12,AA13,AC17,AB15,AA16,Y18,AB18,AA20,V20,W21,V21,V22,U21,U22,T22, "&
               "W23,R21,T23,R22,N23,P20,M23,P21,P22,N21,N22,K4,K3,K2,L3,L2,R1,M3,M2,N3,N2,U1,P4,W1,P3,Y1,P2, "&
		       "R3,R2,T3,T2,U3,U2,V4,V2,Y3,Y6,AA5,AA6,AB6,AA7,AB7,AB8), " &
"S_GNT      	: (AB1,Y2,AC5,AB4,AC4), "&
"S_REQ      	: (AA2,W2,AB3,AB5,AC3), "&
"S_CBE      	: (AB12,AB16,AB14,AA15,AC8,AA11,AB10,Y10), " &
"P_PAR64    	: A9  , " &
"P_IRDY	    	: A16 , " &
"P_FRAME    	: A17 , " &
"P_VDDA	    	: A21 , " &
"P_SERR     	: B4  , " &
"P_TRDY		: B15 , " &
"P_IDSEL	: B19 , " &
"P_REQ		: B21 , " &
"JTG_TDO	: B23 , " &
"T_MODECTL	: C1  , " &
"P_STOP		: C4  , " &
"P_CFG_BUSY	: C6  , " &
"P_PERR		: C8  , " &
"P_REQ64	: C12 , " &
"P_LOCK		: C14 , " &
"P_PAR		: C18 , " &
"P_GNT		: C20 , " &
"JTG_TDI	: C22 , " &
"JTG_TRST_b	: C23 , " &
"RESERVED2	: D1  , " &
"XCLK_OUT	: D3  , " &
"P_DEVSEL	: D21 , " &
"JTG_TMS	: D22 , " &
"P_DRVR_MODE 	: E2 , " &
"P_CLK		: E21 , " &
"P_RST		: E22 , " &
"JTG_TCK	: F21 , " &
"BAR_EN		: G2  , " &
"S_PCIXCAP	: R23 , " &
"S_INT_ARB_EN 	: T21 , " &
"S_RST		: U23 , " &
"S_SEL100	: V3  , " &
"S_CLK_STABLE 	: W3 , " &
"T_RI		: W22 , " &
"S_TRDY		: Y14 , " &
"T_DI1		: Y21 , " &
"P_64_BIT_DEVICE : Y22 , " &
"S_PCIXCAP_PU	 : AA1 , " &
"T_DI2		: AA4 , " &
"S_ACK64	: AA8 , " &
"S_PAR64	: AA10 , " &
"S_FRAME	: AA14 , " &
"S_PAR		: AA17 , " &
"OPAQUE_EN	: AA18 , " &
"S_GNT1REQ	: AA19 , " &
"S_IDSEL	: AA22 , " &
"S_REQ1GNT	: AA23 , " &
"S_REQ64	: AB13 , " &
"S_PERR		: AB17 , " &
"S_SERR		: AB19 , " &
"S_STOP		: AB20 , " &
"S_VDDA		: AB21 , " &
"S_CLK		: AB23 , " &
"S_DRVR_MODE 	: AC7 , " &
"S_IRDY		: AC19 , " &
"S_LOCK		: AC20 , " &
"S_DEVSEL	: AC21 , " &
"IDSEL_REROUTE_EN : AC22 , " &
"TEST_CEO   	: Y23 " ;


-- TAP control declarations

   attribute TAP_SCAN_RESET of JTG_TRST_b: signal is true;
   attribute TAP_SCAN_IN    of JTG_TDI : signal is true;
   attribute TAP_SCAN_MODE  of JTG_TMS : signal is true;
   attribute TAP_SCAN_OUT   of JTG_TDO : signal is true;
   attribute TAP_SCAN_CLOCK of JTG_TCK : signal is (2.5e+07, BOTH);

   attribute INSTRUCTION_LENGTH of tsi310: entity is 4;
 
   attribute INSTRUCTION_OPCODE of tsi310: entity is
      "IDCODE   (0110)," &
      "BYPASS   (1111)," &
      "EXTEST	(0000)," &
      "SAMPLE   (0100)," &
      "HIGHZ    (0101)" ;
 
   attribute INSTRUCTION_CAPTURE of tsi310: entity is 
   "xx01";
 
   attribute IDCODE_REGISTER of tsi310: entity is
      "0010"             & -- version 2
      "0100100101000000" & -- part number  4940
      "00000100100"      & -- manufacturer's identity 048
      "1";                 -- required by 1149.1
 
   attribute REGISTER_ACCESS of tsi310: entity is
      "BYPASS (HIGHZ)" ;

--Boundary scan definition
    attribute BOUNDARY_LENGTH of tsi310: entity is 377;
    attribute BOUNDARY_REGISTER of tsi310: entity is
	
-- Boundary Scan Register Bit Map
-- Bit	Cell Type	Port Name    Function   Tristate
-- Position					Control Cell
"0   (BC_2 , *        , INTERNAL, x),"&
"1   (BC_7 , P_AD(0)  , BIDIR , x, 209 , 0 , Z ) ,"&
"2   (BC_7 , P_AD(1)  , BIDIR , x, 210 , 0 , Z ) ,"&
"3   (BC_7 , P_AD(2)  , BIDIR , x, 211 , 0 , Z ) ,"&
"4   (BC_7 , P_AD(3)  , BIDIR , x, 212 , 0 , Z ) ,"&
"5   (BC_7 , P_AD(4)  , BIDIR , x, 213 , 0 , Z ) ,"&
"6   (BC_7 , P_AD(5)  , BIDIR , x, 214 , 0 , Z ) ,"&
"7   (BC_7 , P_AD(6)  , BIDIR , x, 215 , 0 , Z ) ,"&
"8   (BC_7 , P_AD(7)  , BIDIR , x, 216 , 0 , Z ) ,"&
"9   (BC_7 , P_AD(8)  , BIDIR , x, 217 , 0 , Z ) ,"&
"10  (BC_7 , P_AD(9)  , BIDIR , x, 218 , 0 , Z ) ,"&
"11  (BC_7 , P_AD(10) , BIDIR , x, 219 , 0 , Z ) ,"&
"12  (BC_7 , P_AD(11) , BIDIR , x, 220 , 0 , Z ) ,"&
"13  (BC_7 , P_AD(12) , BIDIR , x, 221 , 0 , Z ) ,"&
"14  (BC_7 , P_AD(13) , BIDIR , x, 222 , 0 , Z ) ,"&
"15  (BC_7 , P_AD(14) , BIDIR , x, 223 , 0 , Z ) ,"&
"16  (BC_7 , P_AD(15) , BIDIR , x, 224 , 0 , Z ) ,"&
"17  (BC_7 , P_AD(16) , BIDIR , x, 225 , 0 , Z ) ,"&
"18  (BC_7 , P_AD(17) , BIDIR , x, 226 , 0 , Z ) ,"&
"19  (BC_7 , P_AD(18) , BIDIR , x, 227 , 0 , Z ) ,"&
"20  (BC_7 , P_AD(19) , BIDIR , x, 228 , 0 , Z ) ,"&
"21  (BC_7 , P_AD(20) , BIDIR , x, 229 , 0 , Z ) ,"&
"22  (BC_7 , P_AD(21) , BIDIR , x, 230 , 0 , Z ) ,"&
"23  (BC_7 , P_AD(22) , BIDIR , x, 231 , 0 , Z ) ,"&
"24  (BC_7 , P_AD(23) , BIDIR , x, 232 , 0 , Z ) ,"&
"25  (BC_7 , P_AD(24) , BIDIR , x, 233 , 0 , Z ) ,"&
"26  (BC_7 , P_AD(25) , BIDIR , x, 234 , 0 , Z ) ,"&
"27  (BC_7 , P_AD(26) , BIDIR , x, 235 , 0 , Z ) ,"&
"28  (BC_7 , P_AD(27) , BIDIR , x, 236 , 0 , Z ) ,"&
"29  (BC_7 , P_AD(28) , BIDIR , x, 237 , 0 , Z ) ,"&
"30  (BC_7 , P_AD(29) , BIDIR , x, 238 , 0 , Z ) ,"&
"31  (BC_7 , P_AD(30) , BIDIR , x, 239 , 0 , Z ) ,"&
"32  (BC_7 , P_AD(31) , BIDIR , x, 240 , 0 , Z ) ,"&
"33  (BC_7 , P_AD(32) , BIDIR , x, 241 , 0 , Z ) ,"&
"34  (BC_7 , P_AD(33) , BIDIR , x, 242 , 0 , Z ) ,"&
"35  (BC_7 , P_AD(34) , BIDIR , x, 243 , 0 , Z ) ,"&
"36  (BC_7 , P_AD(35) , BIDIR , x, 244 , 0 , Z ) ,"&
"37  (BC_7 , P_AD(36) , BIDIR , x, 245 , 0 , Z ) ,"&
"38  (BC_7 , P_AD(37) , BIDIR , x, 246 , 0 , Z ) ,"&
"39  (BC_7 , P_AD(38) , BIDIR , x, 247 , 0 , Z ) ,"&
"40  (BC_7 , P_AD(39) , BIDIR , x, 248 , 0 , Z ) ,"&
"41  (BC_7 , P_AD(40) , BIDIR , x, 249 , 0 , Z ) ,"&
"42  (BC_7 , P_AD(41) , BIDIR , x, 250 , 0 , Z ) ,"&
"43  (BC_7 , P_AD(42) , BIDIR , x, 251 , 0 , Z ) ,"&
"44  (BC_7 , P_AD(43) , BIDIR , x, 252 , 0 , Z ) ,"&
"45  (BC_7 , P_AD(44) , BIDIR , x, 253 , 0 , Z ) ,"&
"46  (BC_7 , P_AD(45) , BIDIR , x, 254 , 0 , Z ) ,"&
"47  (BC_7 , P_AD(46) , BIDIR , x, 255 , 0 , Z ) ,"&
"48  (BC_7 , P_AD(47) , BIDIR , x, 256 , 0 , Z ) ,"&
"49  (BC_7 , P_AD(48) , BIDIR , x, 257 , 0 , Z ) ,"&
"50  (BC_7 , P_AD(49) , BIDIR , x, 258 , 0 , Z ) ,"&
"51  (BC_7 , P_AD(50) , BIDIR , x, 259 , 0 , Z ) ,"&
"52  (BC_7 , P_AD(51) , BIDIR , x, 260 , 0 , Z ) ,"&
"53  (BC_7 , P_AD(52) , BIDIR , x, 261 , 0 , Z ) ,"&
"54  (BC_7 , P_AD(53) , BIDIR , x, 262 , 0 , Z ) ,"&
"55  (BC_7 , P_AD(54) , BIDIR , x, 263 , 0 , Z ) ,"&
"56  (BC_7 , P_AD(55) , BIDIR , x, 264 , 0 , Z ) ,"&
"57  (BC_7 , P_AD(56) , BIDIR , x, 265 , 0 , Z ) ,"&
"58  (BC_7 , P_AD(57) , BIDIR , x, 266 , 0 , Z ) ,"&
"59  (BC_7 , P_AD(58) , BIDIR , x, 267 , 0 , Z ) ,"&
"60  (BC_7 , P_AD(59) , BIDIR , x, 268 , 0 , Z ) ,"&
"61  (BC_7 , P_AD(60) , BIDIR , x, 269 , 0 , Z ) ,"&
"62  (BC_7 , P_AD(61) , BIDIR , x, 270 , 0 , Z ) ,"&
"63  (BC_7 , P_AD(62) , BIDIR , x, 271 , 0 , Z ) ,"&
"64  (BC_7 , P_AD(63) , BIDIR , x, 272 , 0 , Z ) ,"&
"65  (BC_7 , P_CBE(0) , BIDIR , x, 273 , 0 , Z ) ,"&
"66  (BC_7 , P_CBE(1) , BIDIR , x, 274 , 0 , Z ) ,"&
"67  (BC_7 , P_CBE(2) , BIDIR , x, 275 , 0 , Z ) ,"&
"68  (BC_7 , P_CBE(3) , BIDIR , x, 276 , 0 , Z ) ,"&
"69  (BC_7 , P_CBE(4) , BIDIR , x, 277 , 0 , Z ) ,"&
"70  (BC_7 , P_CBE(5) , BIDIR , x, 278 , 0 , Z ) ,"&
"71  (BC_7 , P_CBE(6) , BIDIR , x, 279 , 0 , Z ) ,"&
"72  (BC_7 , P_CBE(7) , BIDIR , x, 280 , 0 , Z ) ,"&
"73  (BC_4   , P_CLK    , INPUT , 0 ) ,"&
"74  (BC_7 , P_DEVSEL , BIDIR , x, 281 , 0 , Z ) ,"&
"75  (BC_7 , P_FRAME  , BIDIR , x, 282 , 0 , Z ) ,"&
"76  (BC_3 , P_GNT , INPUT , 1 ) ,"&
"77  (BC_3 , P_IDSEL , INPUT , 1) ,"&
"78  (BC_7 , P_IRDY , BIDIR , x, 283 , 0 , Z ) ,"&
"79  (BC_3 , P_LOCK , INPUT , 1) ,"&
"80  (BC_3 , P_DRVR_MODE ,  INPUT , 0) ,"&
"81  (BC_7 , P_PAR    , BIDIR , x, 284 , 0 , Z ) ,"&
"82  (BC_7 , P_PAR64  , BIDIR , x, 285 , 0 , Z ) ,"&
"83  (BC_3 , P_CFG_BUSY , INPUT , 0 ) ,"&
"84  (BC_7 , P_PERR   , BIDIR , x, 286 , 0 , Z ) ,"&
"85  (BC_7 , P_REQ64  , BIDIR , x, 287 , 0 , Z ) ,"&
"86  (BC_1 , P_REQ    , OUTPUT3 , x, 288 , 0 , Z ) ,"&
"87  (BC_3 , P_RST    , INPUT , 0 ) ,"&
"88  (BC_1 , P_SERR   , OUTPUT3 , x, 289 , 0 , Z ) ,"&
"89  (BC_7 , P_STOP   , BIDIR , x, 290 , 0 , Z ) ,"&
"90  (BC_7 , P_TRDY   , BIDIR , x, 291 , 0 , Z ) ,"&
"91  (BC_7 , S_ACK64  , BIDIR , x, 292 , 0 , Z ) ,"&
"92  (BC_7 , S_AD(0)  , BIDIR , x, 293 , 0 , Z ) ,"&
"93  (BC_7 , S_AD(1)  , BIDIR , x, 294 , 0 , Z ) ,"&
"94  (BC_7 , S_AD(2)  , BIDIR , x, 295 , 0 , Z ) ,"&
"95  (BC_7 , S_AD(3)  , BIDIR , x, 296 , 0 , Z ) ,"&
"96  (BC_7 , S_AD(4)  , BIDIR , x, 297 , 0 , Z ) ,"&
"97  (BC_7 , S_AD(5)  , BIDIR , x, 298 , 0 , Z ) ,"&
"98  (BC_7 , S_AD(6)  , BIDIR , x, 299 , 0 , Z ) ,"&
"99  (BC_7 , S_AD(7)  , BIDIR , x,  300 , 0 , Z ) ,"&
"100  (BC_7 , S_AD(8)  , BIDIR , x,301 , 0 , Z ) ,"&
"101 (BC_7 , S_AD(9)  , BIDIR , x,  302, 0 , Z ) ,"&
"102 (BC_7 , S_AD(10) ,  BIDIR , x, 303  , 0 , Z ) ,"&
"103 (BC_7 , S_AD(11) ,  BIDIR , x, 304  , 0 , Z ) ,"&
"104 (BC_7 , S_AD(12) ,  BIDIR , x, 305 , 0 , Z ) ,"&
"105 (BC_7 , S_AD(13) ,  BIDIR , x, 306 , 0 , Z ) ,"&
"106 (BC_7 , S_AD(14) ,  BIDIR , x, 307 , 0 , Z ) ,"&
"107 (BC_7 , S_AD(15) ,  BIDIR , x, 308 , 0 , Z ) ,"&
"108 (BC_7 , S_AD(16) ,  BIDIR , x, 309 , 0 , Z ) ,"&
"109 (BC_7 , S_AD(17) ,  BIDIR , x, 310 , 0 , Z ) ,"&
"110 (BC_7 , S_AD(18) ,  BIDIR , x, 311 , 0 , Z ) ,"&
"111 (BC_7 , S_AD(19) ,  BIDIR , x, 312 , 0 , Z ) ,"&
"112 (BC_7 , S_AD(20) ,  BIDIR , x, 313 , 0 , Z ) ,"&
"113 (BC_7 , S_AD(21) ,  BIDIR , x, 314 , 0 , Z ) ,"&
"114 (BC_7 , S_AD(22) ,  BIDIR , x, 315 , 0 , Z ) ,"&
"115 (BC_7 , S_AD(23) ,  BIDIR , x, 316 , 0 , Z ) ,"&
"116 (BC_7 , S_AD(24) ,  BIDIR , x, 317 , 0 , Z ) ,"&
"117 (BC_7 , S_AD(25) ,  BIDIR , x, 318 , 0 , Z ) ,"&
"118 (BC_7 , S_AD(26) ,  BIDIR , x, 319 , 0 , Z ) ,"&
"119 (BC_7 , S_AD(27) ,  BIDIR , x, 320 , 0 , Z ) ,"&
"120 (BC_7 , S_AD(28) ,  BIDIR , x, 321 , 0 , Z ) ,"&
"121 (BC_7 , S_AD(29) ,  BIDIR , x, 322 , 0 , Z ) ,"&
"122 (BC_7 , S_AD(30) ,  BIDIR , x, 323 , 0 , Z ) ,"&
"123 (BC_7 , S_AD(31) ,  BIDIR , x, 324 , 0 , Z ) ,"&
"124 (BC_7 , S_AD(32) ,  BIDIR , x, 325 , 0 , Z ) ,"&
"125 (BC_7 , S_AD(33) ,  BIDIR , x, 326 , 0 , Z ) ,"&
"126 (BC_7 , S_AD(34) ,  BIDIR , x, 327 , 0 , Z ) ,"&
"127 (BC_7 , S_AD(35) ,  BIDIR , x, 328 , 0 , Z ) ,"&
"128 (BC_7 , S_AD(36) ,  BIDIR , x, 329 , 0 , Z ) ,"&
"129 (BC_7 , S_AD(37) ,  BIDIR , x, 330 , 0 , Z ) ,"&
"130 (BC_7 , S_AD(38) ,  BIDIR , x, 331 , 0 , Z ) ,"&
"131 (BC_7 , S_AD(39) ,  BIDIR , x, 332 , 0 , Z ) ,"&
"132 (BC_7 , S_AD(40) ,  BIDIR , x, 333 , 0 , Z ) ,"&
"133 (BC_7 , S_AD(41) ,  BIDIR , x, 334 , 0 , Z ) ,"&
"134 (BC_7 , S_AD(42) ,  BIDIR , x, 335 , 0 , Z ) ,"&
"135 (BC_7 , S_AD(43) ,  BIDIR , x, 336 , 0 , Z ) ,"&
"136 (BC_7 , S_AD(44) ,  BIDIR , x, 337 , 0 , Z ) ,"&
"137 (BC_7 , S_AD(45) ,  BIDIR , x, 338 , 0 , Z ) ,"&
"138 (BC_7 , S_AD(46) ,  BIDIR , x, 339 , 0 , Z ) ,"&
"139 (BC_7 , S_AD(47) ,  BIDIR , x, 340 , 0 , Z ) ,"&
"140 (BC_7 , S_AD(48) ,  BIDIR , x, 341 , 0 , Z ) ,"&
"141 (BC_7 , S_AD(49) ,  BIDIR , x, 342 , 0 , Z ) ,"&
"142 (BC_7 , S_AD(50) ,  BIDIR , x, 343 , 0 , Z ) ,"&
"143 (BC_7 , S_AD(51) ,  BIDIR , x, 344 , 0 , Z ) ,"&
"144 (BC_7 , S_AD(52) ,  BIDIR , x, 345 , 0 , Z ) ,"&
"145 (BC_7 , S_AD(53) ,  BIDIR , x, 346 , 0 , Z ) ,"&
"146 (BC_7 , S_AD(54) ,  BIDIR , x, 347 , 0 , Z ) ,"&
"147 (BC_7 , S_AD(55) ,  BIDIR , x, 348 , 0 , Z ) ,"&
"148 (BC_7 , S_AD(56) ,  BIDIR , x, 349 , 0 , Z ) ,"&
"149 (BC_7 , S_AD(57) ,  BIDIR , x, 350 , 0 , Z ) ,"&
"150 (BC_7 , S_AD(58) ,  BIDIR , x, 351 , 0 , Z ) ,"&
"151 (BC_7 , S_AD(59) ,  BIDIR , x, 352 , 0 , Z ) ,"&
"152 (BC_7 , S_AD(60) ,  BIDIR , x, 353 , 0 , Z ) ,"&
"153 (BC_7 , S_AD(61) ,  BIDIR , x, 354 , 0 , Z ) ,"&
"154 (BC_7 , S_AD(62) ,  BIDIR , x, 355 , 0 , Z ) ,"&
"155 (BC_7 , S_AD(63) ,  BIDIR , x, 356 , 0 , Z ) ,"&
"156 (BC_7 , S_CBE(0) ,  BIDIR , x, 357 , 0 , Z ) ,"&
"157 (BC_7 , S_CBE(1) ,  BIDIR , x, 358 , 0 , Z ) ,"&
"158 (BC_7 , S_CBE(2) ,  BIDIR , x, 359 , 0 , Z ) ,"&
"159 (BC_7 , S_CBE(3) ,  BIDIR , x, 360 , 0 , Z ) ,"&
"160 (BC_7 , S_CBE(4) ,  BIDIR , x, 361 , 0 , Z ) ,"&
"161 (BC_7 , S_CBE(5) ,  BIDIR , x, 362 , 0 , Z ) ,"&
"162 (BC_7 , S_CBE(6) ,  BIDIR , x, 363 , 0 , Z ) ,"&
"163 (BC_7 , S_CBE(7) ,  BIDIR , x, 364 , 0 , Z ) ,"&
"164 (BC_4 , S_CLK    ,  INPUT , 0) ,"&
"165 (BC_3 , S_CLK_STABLE ,  INPUT , 1) ,"&
"166 (BC_7 , S_DEVSEL ,  BIDIR , x, 365 , 0 , Z ) ,"&
"167 (BC_7 , S_FRAME  ,  BIDIR , x, 366 , 0 , Z ) ,"&
"168 (BC_1 , S_GNT1REQ ,  OUTPUT3 , x, 202 , 0 , Z ) ,"&
"169 (BC_1 , S_GNT(2) , OUTPUT3 , x, 203 , 0 , Z  ) ,"&
"170 (BC_1 , S_GNT(3) , OUTPUT3 , x, 204 , 0 , Z  ) ,"&
"171 (BC_1 , S_GNT(4) , OUTPUT3 , x, 205 , 0 , Z  ) ,"&
"172 (BC_1 , S_GNT(5) , OUTPUT3 , x, 206 , 0 , Z  ) ,"&
"173 (BC_1 , S_GNT(6) , OUTPUT3 , x, 207 , 0 , Z  ) ,"&
"174 (BC_3 , S_INT_ARB_EN ,  INPUT , 1) ,"&
"175 (BC_7 , S_IRDY , BIDIR , x, 367 , 0 , Z ) ,"&
"176 (BC_7 , S_LOCK , BIDIR , x, 368 , 0 , Z ) ,"&
"177 (BC_3 , S_DRVR_MODE ,  INPUT , 0) ,"&
"178 (BC_7 , S_PAR , BIDIR , x, 369 , 0 , Z ) ,"&
"179 (BC_7 , S_PAR64 , BIDIR , x, 370 , 0 , Z ) ,"&
"180 (BC_3 , S_PCIXCAP ,  INPUT , x) ,"&
"181 (BC_1 , S_PCIXCAP_PU ,  OUTPUT3 , x, 376 , 0 , Z ) ,"&
"182 (BC_7 , S_PERR , BIDIR , x, 371 , 0 , Z ) ,"&
"183 (BC_3 , S_REQ1GNT , INPUT , 1) ,"&
"184 (BC_3 , S_REQ(2) , INPUT , 1) ,"&
"185 (BC_3 , S_REQ(3) , INPUT , 1) ,"&
"186 (BC_3 , S_REQ(4) , INPUT , 1) ,"&
"187 (BC_3 , S_REQ(5) , INPUT , 1) ,"&
"188 (BC_7 , S_REQ64 ,  BIDIR , x, 372 , 0 , Z ) ,"&
"189 (BC_3 , S_REQ(6) , INPUT , 1) ,"&
"190 (BC_2 , S_RST , OUTPUT2 , 0) ,"&
"191 (BC_3 , S_SEL100 , INPUT , x) ,"&
"192 (BC_3 , S_SERR ,  INPUT , 1) ,"&
"193 (BC_7 , S_STOP , BIDIR , x, 373 , 0 , Z ) ,"&
"194 (BC_7 , S_TRDY , BIDIR , x, 374 , 0 , Z ) ,"&
"195 (BC_3 , BAR_EN , INPUT , 1) ,"&
"196 (BC_3 , RESERVED2 , INPUT , x) ,"&
"197 (BC_1 , XCLK_OUT , OUTPUT3 , x, 375 , 0 , Z ) ,"&
"198 (BC_3 , S_IDSEL , INPUT , 1) ,"&
"199 (BC_3 , P_64_BIT_DEVICE ,  INPUT , 1) ,"&
"200 (BC_3 , IDSEL_REROUTE_EN , INPUT , 0) ,"&
"201 (BC_3 , OPAQUE_EN ,  INPUT , 0) ,"&
"202 (BC_2 , * , CONTROL , 0) ,"&
"203 (BC_2 , * , CONTROL , 0) ,"&
"204 (BC_2 , * , CONTROL , 0) ,"&
"205 (BC_2 , * , CONTROL , 0) ,"&
"206 (BC_2 , * , CONTROL , 0) ,"&
"207 (BC_2 , * , CONTROL , 0) ,"&
"208 (BC_2 , * , INTERNAL , 0) ,"&
"209 (BC_2 , * , CONTROL , 0) ,"&
"210 (BC_2 , * , CONTROL , 0) ,"&
"211 (BC_2 , * , CONTROL , 0) ,"&
"212 (BC_2 , * , CONTROL , 0) ,"&
"213 (BC_2 , * , CONTROL , 0) ,"&
"214 (BC_2 , * , CONTROL , 0) ,"&
"215 (BC_2 , * , CONTROL , 0) ,"&
"216 (BC_2 , * , CONTROL , 0) ,"&
"217 (BC_2 , * , CONTROL , 0) ,"&
"218 (BC_2 , * , CONTROL , 0) ,"&
"219 (BC_2 , * , CONTROL , 0) ,"&
"220 (BC_2 , * , CONTROL , 0) ,"&
"221 (BC_2 , * , CONTROL , 0) ,"&
"222 (BC_2 , * , CONTROL , 0) ,"&
"223 (BC_2 , * , CONTROL , 0) ,"&
"224 (BC_2 , * , CONTROL , 0) ,"&
"225 (BC_2 , * , CONTROL , 0) ,"&
"226 (BC_2 , * , CONTROL , 0) ,"&
"227 (BC_2 , * , CONTROL , 0) ,"&
"228 (BC_2 , * , CONTROL , 0) ,"&
"229 (BC_2 , * , CONTROL , 0) ,"&
"230 (BC_2 , * , CONTROL , 0) ,"&
"231 (BC_2 , * , CONTROL , 0) ,"&
"232 (BC_2 , * , CONTROL , 0) ,"&
"233 (BC_2 , * , CONTROL , 0) ,"&
"234 (BC_2 , * , CONTROL , 0) ,"&
"235 (BC_2 , * , CONTROL , 0) ,"&
"236 (BC_2 , * , CONTROL , 0) ,"&
"237 (BC_2 , * , CONTROL , 0) ,"&
"238 (BC_2 , * , CONTROL , 0) ,"&
"239 (BC_2 , * , CONTROL , 0) ,"&
"240 (BC_2 , * , CONTROL , 0) ,"&
"241 (BC_2 , * , CONTROL , 0) ,"&
"242 (BC_2 , * , CONTROL , 0) ,"&
"243 (BC_2 , * , CONTROL , 0) ,"&
"244 (BC_2 , * , CONTROL , 0) ,"&
"245 (BC_2 , * , CONTROL , 0) ,"&
"246 (BC_2 , * , CONTROL , 0) ,"&
"247 (BC_2 , * , CONTROL , 0) ,"&
"248 (BC_2 , * , CONTROL , 0) ,"&
"249 (BC_2 , * , CONTROL , 0) ,"&
"250 (BC_2 , * , CONTROL , 0) ,"&
"251 (BC_2 , * , CONTROL , 0) ,"&
"252 (BC_2 , * , CONTROL , 0) ,"&
"253 (BC_2 , * , CONTROL , 0) ,"&
"254 (BC_2 , * , CONTROL , 0) ,"&
"255 (BC_2 , * , CONTROL , 0) ,"&
"256 (BC_2 , * , CONTROL , 0) ,"&
"257 (BC_2 , * , CONTROL , 0) ,"&
"258 (BC_2 , * , CONTROL , 0) ,"&
"259 (BC_2 , * , CONTROL , 0) ,"&
"260 (BC_2 , * , CONTROL , 0) ,"&
"261 (BC_2 , * , CONTROL , 0) ,"&
"262 (BC_2 , * , CONTROL , 0) ,"&
"263 (BC_2 , * , CONTROL , 0) ,"&
"264 (BC_2 , * , CONTROL , 0) ,"&
"265 (BC_2 , * , CONTROL , 0) ,"&
"266 (BC_2 , * , CONTROL , 0) ,"&
"267 (BC_2 , * , CONTROL , 0) ,"&
"268 (BC_2 , * , CONTROL , 0) ,"&
"269 (BC_2 , * , CONTROL , 0) ,"&
"270 (BC_2 , * , CONTROL , 0) ,"&
"271 (BC_2 , * , CONTROL , 0) ,"&
"272 (BC_2 , * , CONTROL , 0) ,"&
"273 (BC_2 , * , CONTROL , 0) ,"&
"274 (BC_2 , * , CONTROL , 0) ,"&
"275 (BC_2 , * , CONTROL , 0) ,"&
"276 (BC_2 , * , CONTROL , 0) ,"&
"277 (BC_2 , * , CONTROL , 0) ,"&
"278 (BC_2 , * , CONTROL , 0) ,"&
"279 (BC_2 , * , CONTROL , 0) ,"&
"280 (BC_2 , * , CONTROL , 0) ,"&
"281 (BC_2 , * , CONTROL , 0) ,"&
"282 (BC_2 , * , CONTROL , 0) ,"&
"283 (BC_2 , * , CONTROL , 0) ,"&
"284 (BC_2 , * , CONTROL , 0) ,"&
"285 (BC_2 , * , CONTROL , 0) ,"&
"286 (BC_2 , * , CONTROL , 0) ,"&
"287 (BC_2 , * , CONTROL , 0) ,"&
"288 (BC_2 , * , CONTROL , 0) ,"&
"289 (BC_2 , * , CONTROL , 0) ,"&
"290 (BC_2 , * , CONTROL , 0) ,"&
"291 (BC_2 , * , CONTROL , 0) ,"&
"292 (BC_2 , * , CONTROL , 0) ,"&
"293 (BC_2 , * , CONTROL , 0) ,"&
"294 (BC_2 , * , CONTROL , 0) ,"&
"295 (BC_2 , * , CONTROL , 0) ,"&
"296 (BC_2 , * , CONTROL , 0) ,"&
"297 (BC_2 , * , CONTROL , 0) ,"&
"298 (BC_2 , * , CONTROL , 0) ,"&
"299 (BC_2 , * , CONTROL , 0) ,"&
"300 (BC_2 , * , CONTROL , 0) ,"&
"301 (BC_2 , * , CONTROL , 0) ,"&
"302 (BC_2 , * , CONTROL , 0) ,"&
"303 (BC_2 , * , CONTROL , 0) ,"&
"304 (BC_2 , * , CONTROL , 0) ,"&
"305 (BC_2 , * , CONTROL , 0) ,"&
"306 (BC_2 , * , CONTROL , 0) ,"&
"307 (BC_2 , * , CONTROL , 0) ,"&
"308 (BC_2 , * , CONTROL , 0) ,"&
"309 (BC_2 , * , CONTROL , 0) ,"&
"310 (BC_2 , * , CONTROL , 0) ,"&
"311 (BC_2 , * , CONTROL , 0) ,"&
"312 (BC_2 , * , CONTROL , 0) ,"&
"313 (BC_2 , * , CONTROL , 0) ,"&
"314 (BC_2 , * , CONTROL , 0) ,"&
"315 (BC_2 , * , CONTROL , 0) ,"&
"316 (BC_2 , * , CONTROL , 0) ,"&
"317 (BC_2 , * , CONTROL , 0) ,"&
"318 (BC_2 , * , CONTROL , 0) ,"&
"319 (BC_2 , * , CONTROL , 0) ,"&
"320 (BC_2 , * , CONTROL , 0) ,"&
"321 (BC_2 , * , CONTROL , 0) ,"&
"322 (BC_2 , * , CONTROL , 0) ,"&
"323 (BC_2 , * , CONTROL , 0) ,"&
"324 (BC_2 , * , CONTROL , 0) ,"&
"325 (BC_2 , * , CONTROL , 0) ,"&
"326 (BC_2 , * , CONTROL , 0) ,"&
"327 (BC_2 , * , CONTROL , 0) ,"&
"328 (BC_2 , * , CONTROL , 0) ,"&
"329 (BC_2 , * , CONTROL , 0) ,"&
"330 (BC_2 , * , CONTROL , 0) ,"&
"331 (BC_2 , * , CONTROL , 0) ,"&
"332 (BC_2 , * , CONTROL , 0) ,"&
"333 (BC_2 , * , CONTROL , 0) ,"&
"334 (BC_2 , * , CONTROL , 0) ,"&
"335 (BC_2 , * , CONTROL , 0) ,"&
"336 (BC_2 , * , CONTROL , 0) ,"&
"337 (BC_2 , * , CONTROL , 0) ,"&
"338 (BC_2 , * , CONTROL , 0) ,"&
"339 (BC_2 , * , CONTROL , 0) ,"&
"340 (BC_2 , * , CONTROL , 0) ,"&
"341 (BC_2 , * , CONTROL , 0) ,"&
"342 (BC_2 , * , CONTROL , 0) ,"&
"343 (BC_2 , * , CONTROL , 0) ,"&
"344 (BC_2 , * , CONTROL , 0) ,"&
"345 (BC_2 , * , CONTROL , 0) ,"&
"346 (BC_2 , * , CONTROL , 0) ,"&
"347 (BC_2 , * , CONTROL , 0) ,"&
"348 (BC_2 , * , CONTROL , 0) ,"&
"349 (BC_2 , * , CONTROL , 0) ,"&
"350 (BC_2 , * , CONTROL , 0) ,"&
"351 (BC_2 , * , CONTROL , 0) ,"&
"352 (BC_2 , * , CONTROL , 0) ,"&
"353 (BC_2 , * , CONTROL , 0) ,"&
"354 (BC_2 , * , CONTROL , 0) ,"&
"355 (BC_2 , * , CONTROL , 0) ,"&
"356 (BC_2 , * , CONTROL , 0) ,"&
"357 (BC_2 , * , CONTROL , 0) ,"&
"358 (BC_2 , * , CONTROL , 0) ,"&
"359 (BC_2 , * , CONTROL , 0) ,"&
"360 (BC_2 , * , CONTROL , 0) ,"&
"361 (BC_2 , * , CONTROL , 0) ,"&
"362 (BC_2 , * , CONTROL , 0) ,"&
"363 (BC_2 , * , CONTROL , 0) ,"&
"364 (BC_2 , * , CONTROL , 0) ,"&
"365 (BC_2 , * , CONTROL , 0) ,"&
"366 (BC_2 , * , CONTROL , 0) ,"&
"367 (BC_2 , * , CONTROL , 0) ,"&
"368 (BC_2 , * , CONTROL , 0) ,"&
"369 (BC_2 , * , CONTROL , 0) ,"&
"370 (BC_2 , * , CONTROL , 0) ,"&
"371 (BC_2 , * , CONTROL , 0) ,"&
"372 (BC_2 , * , CONTROL , 0) ,"&
"373 (BC_2 , * , CONTROL , 0) ,"&
"374 (BC_2 , * , CONTROL , 0) ,"&
"375 (BC_2 , * , CONTROL , 0) ,"&
"376 (BC_2 , * , CONTROL , 0) ";
end tsi310;




-- Miscellaneous

--  attribute PORT_GROUPING : string;
--  attribute INTEST_EXECUTION : string;
--  subtype BSDL_EXTENSION is string;

--   attribute COMPLIANCE_PATTERNS of tsi310 : entity is
--      "(TEST_CEO) (0)";

--  attribute DESIGN_WARNING : string;
-- end STD_1149_1_1994;  -- End of 1149.1-1994 Package


-- package body STD_1149_1_1994 is   -- Standard Boundary Cells


-- end STD_1149_1_1994;  -- End of 1149.1-1994 Package Body





This library contains 10173 BSDL files (for 7437 distinct entities) from 70 vendors
Last BSDL model (XC3S50_TQ144) was added on Feb 19, 2018 15:08
info@bsdl.info