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BSDL File: DS21455CSBGA Download View details  


-- File Name    :DS21455CSBGA.BSD
-- Created by    :Dallas Semiconductor
-- Documentation  :DS21455 series data sheets
--
-- 
--
-- BSDL Revision  :1.1
--
-- Date created    :03/11/2004
-- Date modified  :03/11/2004
-- Device        :DS21455CSBGA
-- Package        :256-pin CSBGA
-- 
--      IMPORTANT NOTICE
--
-- Dallas Semiconductor customers are advised to obtain the latest version of 
-- device specifications before relying on any published information contained 
-- herein. Dallas Semiconductor assumes no responsibility or liability arising 
-- out of the application of any information described herein.
--
--
--                      IMPORTANT NOTICE ABOUT THE REVISION
--
-- Dallas Semiconductor customers are advised to check the revision of the
-- device they will be using.  All the codes for the device revisions are
-- herein this BSDL file.
--
-- The characters "/", "(", ")" and "*" have been removed from signal names for 
-- compatibility with BSDL file format.
-- 
-- 
entity DS21455CSBGA is
generic (PHYSICAL_PIN_MAP : string := "CSBGA_256");

port (
A0  : in bit ;
A1  : in bit ;
A2  : in bit ;
A3  : in bit ;
A4  : in bit ;
A5  : in bit ;
A6  : in bit ;
A7_ALE_AS  : in bit ;
BPCLK1  : buffer bit ;
BPCLK2  : buffer bit ;
BPCLK3  : buffer bit ;
BPCLK4  : buffer bit ;
BTS  : in bit ;
CS1  : in bit ;
CS2  : in bit ;
CS3  : in bit ;
CS4  : in bit ;
D0_AD0  : inout bit;
D1_AD1  : inout bit;
D2_AD2  : inout bit;
D3_AD3  : inout bit;
D4_AD4  : inout bit;
D5_AD5  : inout bit;
D6_AD6  : inout bit;
D7_AD7  : inout bit;
ESIBRD1  : inout bit;
ESIBRD2  : inout bit;
ESIBRD3  : inout bit;
ESIBRD4  : inout bit;
ESIBS0_1  : inout bit;
ESIBS0_2  : inout bit;
ESIBS0_3  : inout bit;
ESIBS0_4  : inout bit;
ESIBS1_1  : inout bit;
ESIBS1_2  : inout bit;
ESIBS1_3  : inout bit;
ESIBS1_4  : inout bit;
INT  : out bit;
JTCLK  : in bit ;
JTDI  : in bit ;
JTDO  : out bit;
JTMS  : in bit ;
JTRST  : in bit ;
LIUC_TPD  : in bit ;
MUX  : in bit ;
RCHBLK1  : buffer bit;
RCHBLK2  : buffer bit;
RCHBLK3  : buffer bit;
RCHBLK4  : buffer bit;
RCHCLK1  : buffer bit;
RCHCLK2  : buffer bit;
RCHCLK3  : buffer bit;
RCHCLK4  : buffer bit;
RCLK1  : buffer bit;
RCLK2  : buffer bit;
RCLK3  : buffer bit;
RCLK4  : buffer bit;
RCLKI1  : in bit ;
RCLKI2  : in bit ;
RCLKI3  : in bit ;
RCLKI4  : in bit ;
RCLKO1  : buffer bit;
RCLKO2  : buffer bit;
RCLKO3  : buffer bit;
RCLKO4  : buffer bit;
RD_DS  : in bit ;
RFSYNC1  : buffer bit;
RFSYNC2  : buffer bit;
RFSYNC3  : buffer bit;
RFSYNC4  : buffer bit;
RLCLK1  : buffer bit;
RLCLK2  : buffer bit;
RLCLK3  : buffer bit;
RLCLK4  : buffer bit;
RLINK1  : buffer bit;
RLINK2  : buffer bit;
RLINK3  : buffer bit;
RLINK4  : buffer bit;
RLOS_LOTC1  : buffer bit;
RLOS_LOTC2  : buffer bit;
RLOS_LOTC3  : buffer bit;
RLOS_LOTC4  : buffer bit;
RMSYNC1  : buffer bit;
RMSYNC2  : buffer bit;
RMSYNC3  : buffer bit;
RMSYNC4  : buffer bit;
RNEGI1  : in bit ;
RNEGI2  : in bit ;
RNEGI3  : in bit ;
RNEGI4  : in bit ;
RNEGO1  : buffer bit;
RNEGO2  : buffer bit;
RNEGO3  : buffer bit;
RNEGO4  : buffer bit;
RPOSI1  : in bit ;
RPOSI2  : in bit ;
RPOSI3  : in bit ;
RPOSI4  : in bit ;
RPOSO1  : buffer bit;
RPOSO2  : buffer bit;
RPOSO3  : buffer bit;
RPOSO4  : buffer bit;
RSER1  : buffer bit;
RSER2  : buffer bit;
RSER3  : buffer bit;
RSER4  : buffer bit;
RSIG1  : buffer bit;
RSIG2  : buffer bit;
RSIG3  : buffer bit;
RSIG4  : buffer bit;
RSIGF1  : buffer bit;
RSIGF2  : buffer bit;
RSIGF3  : buffer bit;
RSIGF4  : buffer bit;
RSYNC1  : inout bit;
RSYNC2  : inout bit;
RSYNC3  : inout bit;
RSYNC4  : inout bit;
RSYSCLK1  : in bit ;
RSYSCLK2  : in bit ;
RSYSCLK3  : in bit ;
RSYSCLK4  : in bit ;
TCHBLK1  : buffer bit;
TCHBLK2  : buffer bit;
TCHBLK3  : buffer bit;
TCHBLK4  : buffer bit;
TCHCLK1  : buffer bit;
TCHCLK2  : buffer bit;
TCHCLK3  : buffer bit;
TCHCLK4  : buffer bit;
TCLK1  : in bit;
TCLK2  : in bit;
TCLK3  : in bit;
TCLK4  : in bit;
TCLKI1  : in bit ;
TCLKI2  : in bit ;
TCLKI3  : in bit ;
TCLKI4  : in bit ;
TCLKO1  : buffer bit;
TCLKO2  : buffer bit;
TCLKO3  : buffer bit;
TCLKO4  : buffer bit;
TLCLK1  : buffer bit;
TLCLK2  : buffer bit;
TLCLK3  : buffer bit;
TLCLK4  : buffer bit;
TLINK1  : in bit;
TLINK2  : in bit;
TLINK3  : in bit;
TLINK4  : in bit;
TNEGI1  : in bit ;
TNEGI2  : in bit ;
TNEGI3  : in bit ;
TNEGI4  : in bit ;
TNEGO1  : buffer bit;
TNEGO2  : buffer bit;
TNEGO3  : buffer bit;
TNEGO4  : buffer bit;
TPOSI1  : in bit ;
TPOSI2  : in bit ;
TPOSI3  : in bit ;
TPOSI4  : in bit ;
TPOSO1  : buffer bit;
TPOSO2  : buffer bit;
TPOSO3  : buffer bit;
TPOSO4  : buffer bit;
TSER1  : in bit;
TSER2  : in bit;
TSER3  : in bit;
TSER4  : in bit;
TSIG1  : in bit;
TSIG2  : in bit;
TSIG3  : in bit;
TSIG4  : in bit;
TSSYNC1  : in bit;
TSSYNC2  : in bit;
TSSYNC3  : in bit;
TSSYNC4  : in bit;
TSTRST  : in bit;
TSYNC1  : inout bit;
TSYNC2  : inout bit;
TSYNC3  : inout bit;
TSYNC4  : inout bit;
TSYSCLK1  : in bit;
TSYSCLK2  : in bit;
TSYSCLK3  : in bit;
TSYSCLK4  : in bit;
WR_R_W  : in bit ;
RVDD    :linkage bit_vector(1 to 4);
RVSS    :linkage bit_vector(1 to 8);
TVDD    :linkage bit_vector(1 to 4);
TVSS    :linkage bit_vector(1 to 4);
VDD    :linkage bit_vector(1 to 16);
VSS    :linkage bit_vector(1 to 12);
NoConnect  :linkage bit_vector(1 to 2)
);

use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DS21455CSBGA : entity is
  "STD_1149_1_1993";


attribute PIN_MAP of DS21455CSBGA : entity is PHYSICAL_PIN_MAP;

constant CSBGA_256 : PIN_MAP_STRING :=

"A0  :U3  ,"&
"A1  :L17  ,"&
"A2  :V2  ,"&
"A3  :T4  ,"&
"A4  :V8  ,"&
"A5  :H4  ,"&
"A6  :U8  ,"&
"A7_ALE_AS:P4  ,"&
"BPCLK1  :M1  ,"&
"BPCLK2  :H17  ,"&
"BPCLK3  :F4  ,"&
"BPCLK4  :V13  ,"&
"BTS  :P2  ,"&
"CS1  :P3  ,"&
"CS2  :A14  ,"&
"CS3  :B5  ,"&
"CS4  :K17  ,"&
"D0_AD0  :U11  ,"&
"D1_AD1  :J19  ,"&
"D2_AD2  :W15  ,"&
"D3_AD3  :U7  ,"&
"D4_AD4  :U9  ,"&
"D5_AD5  :U5  ,"&
"D6_AD6  :V4  ,"&
"D7_AD7  :U4  ,"&
"ESIBRD1:J4  ,"&
"ESIBRD2:C13  ,"&
"ESIBRD3:C3  ,"&
"ESIBRD4:U13  ,"&
"ESIBS0_1:W6  ,"&
"ESIBS0_2:F18  ,"&
"ESIBS0_3:D7  ,"&
"ESIBS0_4:T20  ,"&
"ESIBS1_1:V9  ,"&
"ESIBS1_2:B17  ,"&
"ESIBS1_3:A6  ,"&
"ESIBS1_4:J20  ,"&
"INT  :U1  ,"&
"JTCLK  :Y15  ,"&
"JTDI  :N1  ,"&
"JTDO  :V19  ,"&
"JTMS  :W13  ,"&
"JTRST  :V18  ,"&
"LIUC_TPD:K2  ,"&
"MUX  :U10  ,"&
"RCHBLK1:M2  ,"&
"RCHBLK2:G17  ,"&
"RCHBLK3:G4  ,"&
"RCHBLK4:Y12  ,"&
"RCHCLK1:J1  ,"&
"RCHCLK2:D14  ,"&
"RCHCLK3:F3  ,"&
"RCHCLK4:U14  ,"&
"RCLK1  :N3  ,"&
"RCLK2  :B13  ,"&
"RCLK3  :E3  ,"&
"RCLK4  :M18  ,"&
"RCLKI1  :M4  ,"&
"RCLKI2  :A15  ,"&
"RCLKI3  :A4  ,"&
"RCLKI4  :R17  ,"&
"RCLKO1  :M3  ,"&
"RCLKO2  :C14  ,"&
"RCLKO3  :B4  ,"&
"RCLKO4  :T17  ,"&
"RD_DS  :N2  ,"&
"RFSYNC1:K4  ,"&
"RFSYNC2:D17  ,"&
"RFSYNC3:A2  ,"&
"RFSYNC4:V14  ,"&
"RLCLK1  :F1  ,"&
"RLCLK2  :A12  ,"&
"RLCLK3  :D3  ,"&
"RLCLK4  :K18  ,"&
"RLINK1  :G2  ,"&
"RLINK2  :A13  ,"&
"RLINK3  :A3  ,"&
"RLINK4  :U12  ,"&
"RLOS_LOTC1:H2  ,"&
"RLOS_LOTC2:E17  ,"&
"RLOS_LOTC3:E1  ,"&
"RLOS_LOTC4:V11  ,"&
"RMSYNC1:L1  ,"&
"RMSYNC2:D16  ,"&
"RMSYNC3:F2  ,"&
"RMSYNC4:W16  ,"&
"RNEGI1  :R3  ,"&
"RNEGI2  :D13  ,"&
"RNEGI3  :A1  ,"&
"RNEGI4  :P17  ,"&
"RNEGO1  :L3  ,"&
"RNEGO2  :B15  ,"&
"RNEGO3  :C2  ,"&
"RNEGO4  :U17  ,"&
"RPOSI1  :R4  ,"&
"RPOSI2  :B14  ,"&
"RPOSI3  :B2  ,"&
"RPOSI4  :V15  ,"&
"RPOSO1  :L4  ,"&
"RPOSO2  :A16  ,"&
"RPOSO3  :B1  ,"&
"RPOSO4  :U15  ,"&
"RSER1  :J2  ,"&
"RSER2  :D15  ,"&
"RSER3  :E2  ,"&
"RSER4  :W17  ,"&
"RSIG1  :L2  ,"&
"RSIG2  :B16  ,"&
"RSIG3  :C1  ,"&
"RSIG4  :Y18  ,"&
"RSIGF1  :K1  ,"&
"RSIGF2  :C15  ,"&
"RSIGF3  :D2  ,"&
"RSIGF4  :V16  ,"&
"RSYNC1  :G1  ,"&
"RSYNC2  :D12  ,"&
"RSYNC3  :D1  ,"&
"RSYNC4  :V12  ,"&
"RSYSCLK1:H1  ,"&
"RSYSCLK2:F17  ,"&
"RSYSCLK3:G3  ,"&
"RSYSCLK4:W14  ,"&
"TCHBLK1:W1  ,"&
"TCHBLK2:F20  ,"&
"TCHBLK3:C11  ,"&
"TCHBLK4:U20  ,"&
"TCHCLK1:V10  ,"&
"TCHCLK2:A18  ,"&
"TCHCLK3:B8  ,"&
"TCHCLK4:L18  ,"&
"TCLK1  :Y9  ,"&
"TCLK2  :B19  ,"&
"TCLK3  :B10  ,"&
"TCLK4  :M19  ,"&
"TCLKI1  :V6  ,"&
"TCLKI2  :D19  ,"&
"TCLKI3  :C8  ,"&
"TCLKI4  :P20  ,"&
"TCLKO1  :W7  ,"&
"TCLKO2  :E18  ,"&
"TCLKO3  :A7  ,"&
"TCLKO4  :P19  ,"&
"TLCLK1  :V3  ,"&
"TLCLK2  :E20  ,"&
"TLCLK3  :D6  ,"&
"TLCLK4  :T18  ,"&
"TLINK1  :W5  ,"&
"TLINK2  :E19  ,"&
"TLINK3  :C6  ,"&
"TLINK4  :T19  ,"&
"TNEGI1  :R1  ,"&
"TNEGI2  :F19  ,"&
"TNEGI3  :D8  ,"&
"TNEGI4  :R20  ,"&
"TNEGO1  :T3  ,"&
"TNEGO2  :B20  ,"&
"TNEGO3  :D9  ,"&
"TNEGO4  :N20  ,"&
"TPOSI1  :W3  ,"&
"TPOSI2  :C20  ,"&
"TPOSI3  :A8  ,"&
"TPOSI4  :R19  ,"&
"TPOSO1  :V7  ,"&
"TPOSO2  :C19  ,"&
"TPOSO3  :C9  ,"&
"TPOSO4  :N19  ,"&
"TSER1  :W9  ,"&
"TSER2  :C17  ,"&
"TSER3  :C10  ,"&
"TSER4  :K20  ,"&
"TSIG1  :W10  ,"&
"TSIG2  :C18  ,"&
"TSIG3  :A10  ,"&
"TSIG4  :L19  ,"&
"TSSYNC1:W12  ,"&
"TSSYNC2:B18  ,"&
"TSSYNC3:D10  ,"&
"TSSYNC4:K19  ,"&
"TSTRST  :U16  ,"&
"TSYNC1  :V1  ,"&
"TSYNC2  :D20  ,"&
"TSYNC3  :C7  ,"&
"TSYNC4  :R18  ,"&
"TSYSCLK1:W11  ,"&
"TSYSCLK2:A19  ,"&
"TSYSCLK3:A11  ,"&
"TSYSCLK4:N18  ,"&
"WR_R_W  :K3  ,"&
"RVDD  :(P1, J17, E4, W18),"&
"RVSS  :(R2, T2, H19, J18, D4, D5, V20, W19),"&
"TVDD  :(W2, G19, D11, U19),"&
"TVSS:(W4, G18, C5, U18),"&
"VDD: (J3, N4, U2, V5, B12, C12, C16, D18, A9, B3, B6, C4, G20, M17, M20, P18),"&
"VSS: (H3, U6, W8, A17, A20, B11, A5, B7, B9, H20, L20, N17),"&
"NoConnect:(H18, V17)";


--      MAKE SURE THAT ALL THESE NO CONNECTS ARE ON ONE LINE.  OTHERWISE
--      THIS BSDL FILE WILL SHOW SOME ERROR.

-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
--        First Field : Maximum  TCK frequency.
--        Second Field: Allowable states TCK may be stopped in.

attribute TAP_SCAN_IN of JTDI    :signal is true;
attribute TAP_SCAN_MODE of JTMS    :signal is true;
attribute TAP_SCAN_OUT of JTDO    :signal is true;
attribute TAP_SCAN_RESET of JTRST  :signal is true;
attribute TAP_SCAN_CLOCK of JTCLK  :signal is (10.00e6,BOTH);

-- Specifies the number of bits in the instruction register.

attribute INSTRUCTION_LENGTH of DS21455CSBGA  :entity is 3;
   
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.

attribute INSTRUCTION_OPCODE of DS21455CSBGA  :entity is
"EXTEST (000),"&
"BYPASS (111),"&
"SAMPLE (010),"&
"IDCODE (001),"&
"CLAMP (011),"&
--   "USER1  (101)," &
--   "USER2  (110)," &
"HIGHZ (100)";

-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.

attribute INSTRUCTION_CAPTURE of DS21455CSBGA :entity is "001";

-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.

-- 10021143 (HEX)

attribute IDCODE_REGISTER of DS21455CSBGA :entity is
--"0000"&        -- 4-bit Version for A1
"0001"&                       -- 4-bit Version for A2
--"0010"&                       -- 4-bit Version for A3
--"XXXX"&                       -- 4-bit Version for any revision
"0000000000100001"&  -- 16-bit Part Number
"00010100001"&    -- 11-bit Manufacturer's Identity
"1";        -- Mandatory LSB


-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
   
-- attribute REGISTER_ACCESS of DS21448_top: entity is 
--      "BYPASS    (BYPASS, CLAMP, HIGHZ, USER1, USER2)," &
--      "BOUNDARY  (EXTEST, SAMPLE)," &
--      "DEVICE_ID (IDCODE)";
   
-- Specifies the length of the boundary scan register.

attribute BOUNDARY_LENGTH of DS21455CSBGA :entity is 204;
attribute BOUNDARY_REGISTER of DS21455CSBGA :entity is 

--    
--    num   cell   port           function      safe  [ccell  disval  rslt]
--    

"  0  (BC_1,  RCLKO3  ,  output2  ,      X),"&
"  1  (BC_1,  RLINK3  ,  output2  ,      X),"&
"  2  (BC_7,  TSYNC3  ,  bidir  , 0,  3  , 0,  Z),"&
"  3  (BC_2,  *  ,  control  ,      0),"&
"  4  (BC_1,  TSSYNC3  ,  input  ,      X),"&
"  5  (BC_1,  TLCLK3  ,  output2  ,      X),"&
"  6  (BC_1,  TCHCLK3  ,  output2  ,      X),"&
"  7  (BC_1,  TCHBLK3  ,  output2  ,      X),"&
"  8  (BC_7,  RSYNC3  ,  bidir  , 0,  9  , 0,  Z),"&
"  9  (BC_2,  *  ,  control  ,      0),"&
"  10  (BC_1,  RSIGF3  ,  output2  ,      X),"&
"  11  (BC_1,  RMSYNC3  ,  output2  ,      X),"&
"  12  (BC_1,  RLOS_LOTC3  ,  output2  ,      X),"&
"  13  (BC_1,  RLCLK3  ,  output2  ,      X),"&
"  14  (BC_1,  RFSYNC3  ,  output2  ,      X),"&
"  15  (BC_1,  RCHCLK3  ,  output2  ,      X),"&
"  16  (BC_1,  RCHBLK3  ,  output2  ,      X),"&
"  17  (BC_7,  ESIBS1_3  ,  bidir  , 0,  18  , 0,  Z),"&
"  18  (BC_2,  *  ,  control  ,      0),"&
"  19  (BC_7,  ESIBS0_3  ,  bidir  , 0,  20  , 0,  Z),"&
"  20  (BC_2,  *  ,  control  ,      0),"&
"  21  (BC_7,  ESIBRD3  ,  bidir  , 0,  22  , 0,  Z),"&
"  22  (BC_2,  *  ,  control  ,      0),"&
"  23  (BC_1,  RSIG3  ,  output2  ,      X),"&
"  24  (BC_1,  RNEGI3  ,  input  ,      X),"&
"  25  (BC_1,  RPOSI3  ,  input  ,      X),"&
"  26  (BC_1,  RNEGO3  ,  output2  ,      X),"&
"  27  (BC_1,  RPOSO3  ,  output2  ,      X),"&
"  28  (BC_1,  BPCLK3  ,  output2  ,      X),"&
"  29  (BC_1,  RSER3  ,  output2  ,      X),"&
"  30  (BC_1,  RSYSCLK3  ,  input  ,      X),"&
"  31  (BC_1,  TSYSCLK3  ,  input  ,      X),"&
"  32  (BC_1,  CS3  ,  input  ,      X),"&
"  33  (BC_1,  LIUC_TPD  ,  input  ,      X),"&
"  34  (BC_1,  WR_R_W  ,  input  ,      X),"&
"  35  (BC_1,  A5  ,  input  ,      X),"&
"  36  (BC_1,  A1  ,  input  ,      X),"&
"  37  (BC_7,  D1_AD1  ,  bidir  , 0,  133  , 0,  Z),"&
"  38  (BC_1,  RD_DS  ,  input  ,      X),"&
"  39  (BC_1,  BTS  ,  input  ,      X),"&
"  40  (BC_1,  RCLKI2  ,  input  ,      X),"&
"  41  (BC_1,  RCLK2  ,  output2  ,      X),"&
"  42  (BC_1,  TSIG2  ,  input  ,      X),"&
"  43  (BC_1,  TSER2  ,  input  ,      X),"&
"  44  (BC_1,  TLINK2  ,  input  ,      X),"&
"  45  (BC_1,  TCLKI2  ,  input  ,      X),"&
"  46  (BC_1,  TCLK2  ,  input  ,      X),"&
"  47  (BC_1,  TNEGI2  ,  input  ,      X),"&
"  48  (BC_1,  TPOSI2  ,  input  ,      X),"&
"  49  (BC_1,  TCLKO2  ,  output2  ,      X),"&
"  50  (BC_1,  TPOSO2  ,  output2  ,      X),"&
"  51  (BC_1,  TNEGO2  ,  output2  ,      X),"&
"  52  (BC_1,  RCLKO2  ,  output2  ,      X),"&
"  53  (BC_1,  RLINK2  ,  output2  ,      X),"&
"  54  (BC_7,  TSYNC2  ,  bidir  , 0,  55  , 0,  Z),"&
"  55  (BC_2,  *  ,  control  ,      0),"&
"  56  (BC_1,  TSSYNC2  ,  input  ,      X),"&
"  57  (BC_1,  TLCLK2  ,  output2  ,      X),"&
"  58  (BC_1,  TCHCLK2  ,  output2  ,      X),"&
"  59  (BC_1,  TCHBLK2  ,  output2  ,      X),"&
"  60  (BC_7,  RSYNC2  ,  bidir  , 0,  61  , 0,  Z),"&
"  61  (BC_2,  *  ,  control  ,      0),"&
"  62  (BC_1,  RSIGF2  ,  output2  ,      X),"&
"  63  (BC_1,  RMSYNC2  ,  output2  ,      X),"&
"  64  (BC_1,  RLOS_LOTC2  ,  output2  ,      X),"&
"  65  (BC_1,  RLCLK2  ,  output2  ,      X),"&
"  66  (BC_1,  RFSYNC2  ,  output2  ,      X),"&
"  67  (BC_1,  RCHCLK2  ,  output2  ,      X),"&
"  68  (BC_1,  RCHBLK2  ,  output2  ,      X),"&
"  69  (BC_7,  ESIBS1_2  ,  bidir  , 0,  70  , 0,  Z),"&
"  70  (BC_2,  *  ,  control  ,      0),"&
"  71  (BC_7,  ESIBS0_2  ,  bidir  , 0,  72  , 0,  Z),"&
"  72  (BC_2,  *  ,  control  ,      0),"&
"  73  (BC_7,  ESIBRD2  ,  bidir  , 0,  74  , 0,  Z),"&
"  74  (BC_2,  *  ,  control  ,      0),"&
"  75  (BC_1,  RSIG2  ,  output2  ,      X),"&
"  76  (BC_1,  RNEGI2  ,  input  ,      X),"&
"  77  (BC_1,  RPOSI2  ,  input  ,      X),"&
"  78  (BC_1,  RNEGO2  ,  output2  ,      X),"&
"  79  (BC_1,  RPOSO2  ,  output2  ,      X),"&
"  80  (BC_1,  BPCLK2  ,  output2  ,      X),"&
"  81  (BC_1,  RSER2  ,  output2  ,      X),"&
"  82  (BC_1,  RSYSCLK2  ,  input  ,      X),"&
"  83  (BC_1,  TSYSCLK2  ,  input  ,      X),"&
"  84  (BC_1,  CS2  ,  input  ,      X),"&
"  85  (BC_1,  TSTRST  ,  input  ,      X),"&
"  86  (BC_1,  RCLKI4  ,  input  ,      X),"&
"  87  (BC_1,  RCLK4  ,  output2  ,      X),"&
"  88  (BC_1,  TSIG4  ,  input  ,      X),"&
"  89  (BC_1,  TSER4  ,  input  ,      X),"&
"  90  (BC_1,  TLINK4  ,  input  ,      X),"&
"  91  (BC_1,  TCLKI4  ,  input  ,      X),"&
"  92  (BC_1,  TCLK4  ,  input  ,      X),"&
"  93  (BC_1,  TNEGI4  ,  input  ,      X),"&
"  94  (BC_1,  TPOSI4  ,  input  ,      X),"&
"  95  (BC_1,  TCLKO4  ,  output2  ,      X),"&
"  96  (BC_1,  TPOSO4  ,  output2  ,      X),"&
"  97  (BC_1,  TNEGO4  ,  output2  ,      X),"&
"  98  (BC_1,  RCLKO4  ,  output2  ,      X),"&
"  99  (BC_1,  RLINK4  ,  output2  ,      X),"&
"  100  (BC_7,  TSYNC4  ,  bidir  , 0,  101  , 0,  Z),"&
"  101  (BC_2,  *  ,  control  ,      0),"&
"  102  (BC_1,  TSSYNC4  ,  input  ,      X),"&
"  103  (BC_1,  TLCLK4  ,  output2  ,      X),"&
"  104  (BC_1,  TCHCLK4  ,  output2  ,      X),"&
"  105  (BC_1,  TCHBLK4  ,  output2  ,      X),"&
"  106  (BC_7,  RSYNC4  ,  bidir  , 0,  107  , 0,  Z),"&
"  107  (BC_2,  *  ,  control  ,      0),"&
"  108  (BC_1,  RSIGF4  ,  output2  ,      X),"&
"  109  (BC_1,  RMSYNC4  ,  output2  ,      X),"&
"  110  (BC_1,  RLOS_LOTC4  ,  output2  ,      X),"&
"  111  (BC_1,  RLCLK4  ,  output2  ,      X),"&
"  112  (BC_1,  RFSYNC4  ,  output2  ,      X),"&
"  113  (BC_1,  RCHCLK4  ,  output2  ,      X),"&
"  114  (BC_1,  RCHBLK4  ,  output2  ,      X),"&
"  115  (BC_7,  ESIBS1_4  ,  bidir  , 0,  116  , 0,  Z),"&
"  116  (BC_2,  *  ,  control  ,      0),"&
"  117  (BC_7,  ESIBS0_4  ,  bidir  , 0,  118  , 0,  Z),"&
"  118  (BC_2,  *  ,  control  ,      0),"&
"  119  (BC_7,  ESIBRD4  ,  bidir  , 0,  120  , 0,  Z),"&
"  120  (BC_2,  *  ,  control  ,      0),"&
"  121  (BC_1,  RSIG4  ,  output2  ,      X),"&
"  122  (BC_1,  RNEGI4  ,  input  ,      X),"&
"  123  (BC_1,  RPOSI4  ,  input  ,      X),"&
"  124  (BC_1,  RNEGO4  ,  output2  ,      X),"&
"  125  (BC_1,  RPOSO4  ,  output2  ,      X),"&
"  126  (BC_1,  BPCLK4  ,  output2  ,      X),"&
"  127  (BC_1,  RSER4  ,  output2  ,      X),"&
"  128  (BC_1,  RSYSCLK4  ,  input  ,      X),"&
"  129  (BC_1,  TSYSCLK4  ,  input  ,      X),"&
"  130  (BC_1,  CS4  ,  input  ,      X),"&
"  131  (BC_7,  D2_AD2  ,  bidir  , 0,  133  , 0,  Z),"&
"  132  (BC_7,  D0_AD0  ,  bidir  , 0,  133  , 0,  Z),"&
"  133  (BC_2,  *  ,  control  ,      0),"&
"  134  (BC_1,  MUX  ,  input  ,      X),"&
"  135  (BC_7,  D4_AD4  ,  bidir  , 0,  133  , 0,  Z),"&
"  136  (BC_1,  A4  ,  input  ,      X),"&
"  137  (BC_1,  A6  ,  input  ,      X),"&
"  138  (BC_7,  D3_AD3  ,  bidir  , 0,  133  , 0,  Z),"&
"  139  (BC_7,  D5_AD5  ,  bidir  , 0,  133  , 0,  Z),"&
"  140  (BC_1,  RCLKI1  ,  input  ,      X),"&
"  141  (BC_1,  RCLK1  ,  output2  ,      X),"&
"  142  (BC_1,  TSIG1  ,  input  ,      X),"&
"  143  (BC_1,  TSER1  ,  input  ,      X),"&
"  144  (BC_1,  TLINK1  ,  input  ,      X),"&
"  145  (BC_1,  TCLKI1  ,  input  ,      X),"&
"  146  (BC_1,  TCLK1  ,  input  ,      X),"&
"  147  (BC_1,  TNEGI1  ,  input  ,      X),"&
"  148  (BC_1,  TPOSI1  ,  input  ,      X),"&
"  149  (BC_1,  TCLKO1  ,  output2  ,      X),"&
"  150  (BC_1,  TPOSO1  ,  output2  ,      X),"&
"  151  (BC_1,  TNEGO1  ,  output2  ,      X),"&
"  152  (BC_1,  RCLKO1  ,  output2  ,      X),"&
"  153  (BC_1,  RLINK1  ,  output2  ,      X),"&
"  154  (BC_7,  TSYNC1  ,  bidir  , 0,  155  , 0,  Z),"&
"  155  (BC_2,  *  ,  control  ,      0),"&
"  156  (BC_1,  TSSYNC1  ,  input  ,      X),"&
"  157  (BC_1,  TLCLK1  ,  output2  ,      X),"&
"  158  (BC_1,  TCHCLK1  ,  output2  ,      X),"&
"  159  (BC_1,  TCHBLK1  ,  output2  ,      X),"&
"  160  (BC_7,  RSYNC1  ,  bidir  , 0,  161  , 0,  Z),"&
"  161  (BC_2,  *  ,  control  ,      0),"&
"  162  (BC_1,  RSIGF1  ,  output2  ,      X),"&
"  163  (BC_1,  RMSYNC1  ,  output2  ,      X),"&
"  164  (BC_1,  RLOS_LOTC1  ,  output2  ,      X),"&
"  165  (BC_1,  RLCLK1  ,  output2  ,      X),"&
"  166  (BC_1,  RFSYNC1  ,  output2  ,      X),"&
"  167  (BC_1,  RCHCLK1  ,  output2  ,      X),"&
"  168  (BC_1,  RCHBLK1  ,  output2   ,      X),"&
"  169  (BC_7,  ESIBS1_1  ,  bidir  , 0,  170  , 0,  Z),"&
"  170  (BC_2,  *  ,  control  ,      0),"&
"  171  (BC_7,  ESIBS0_1  ,  bidir  , 0,  172  , 0,  Z),"&
"  172  (BC_2,  *  ,  control  ,      0),"&
"  173  (BC_7,  ESIBRD1  ,  bidir  , 0,  174  , 0,  Z),"&
"  174  (BC_2,  *  ,  control  ,      0),"&
"  175  (BC_1,  RSIG1  ,  output2  ,      X),"&
"  176  (BC_1,  RNEGI1  ,  input  ,      X),"&
"  177  (BC_1,  RPOSI1  ,  input  ,      X),"&
"  178  (BC_1,  RNEGO1  ,  output2  ,      X),"&
"  179  (BC_1,  RPOSO1  ,  output2  ,      X),"&
"  180  (BC_1,  BPCLK1  ,  output2  ,      X),"&
"  181  (BC_1,  RSER1  ,  output2  ,      X),"&
"  182  (BC_1,  RSYSCLK1  ,  input  ,      X),"&
"  183  (BC_1,  TSYSCLK1  ,  input  ,      X),"&
"  184  (BC_1,  CS1  ,  input  ,      X),"&
"  185  (BC_1,  INT  ,  output2  ,      X),"&
"  186  (BC_1,  A2  ,  input  ,      X),"&
"  187  (BC_1,  A0  ,  input  ,      X),"&
"  188  (BC_1,  A3  ,  input  ,      X),"&
"  189  (BC_7,  D7_AD7  ,  bidir  , 0,  133  , 0,  Z),"&
"  190  (BC_7,  D6_AD6  ,  bidir  , 0,  133  , 0,  Z),"&
"  191  (BC_1,  A7_ALE_AS  ,  input  ,      X),"&
"  192  (BC_1,  RCLKI3  ,  input  ,      X),"&
"  193  (BC_1,  RCLK3  ,  output2  ,      X),"&
"  194  (BC_1,  TSIG3  ,  input  ,      X),"&
"  195  (BC_1,  TSER3  ,  input  ,      X),"&
"  196  (BC_1,  TLINK3  ,  input  ,      X),"&
"  197  (BC_1,  TCLKI3  ,  input  ,      X),"&
"  198  (BC_1,  TCLK3  ,  input  ,      X),"&
"  199  (BC_1,  TNEGI3  ,  input  ,      X),"&
"  200  (BC_1,  TPOSI3  ,  input  ,      X),"&
"  201  (BC_1,  TCLKO3  ,  output2  ,      X),"&
"  202  (BC_1,  TPOSO3  ,  output2  ,      X),"&
"  203  (BC_1,  TNEGO3  ,  output2  ,      X)";
end DS21455CSBGA;

This library contains 8972 BSDL files (for 7016 distinct entities) from 68 vendors
Last BSDL model (sam4s16b) was added on Dec 7, 2017 14:26
info@bsdl.info