-- M O T O R O L A S S D T J T A G S O F T W A R E
-- BSDL File Generated: Mon Apr 16 16:07:13 2001
--
-- Revision History:
--
entity DSP56F827 is
generic (PHYSICAL_PIN_MAP : string := "P128LQFP");
port (POWER_IO10: linkage bit;
GROUND_IO10: linkage bit;
D7: inout bit;
D8: inout bit;
D9: inout bit;
D10: inout bit;
D11: inout bit;
D12: inout bit;
D13: inout bit;
D14: inout bit;
D15: inout bit;
RD_B: inout bit;
WR_B: inout bit;
DS_B: inout bit;
PS_B: inout bit;
POWER_CORE3: linkage bit;
GROUND_CORE3: linkage bit;
A0: inout bit;
A1: inout bit;
A2: inout bit;
A3: inout bit;
A4: inout bit;
A5: inout bit;
A6: inout bit;
A7: inout bit;
POWER_IO7: linkage bit;
GROUND_IO7: linkage bit;
A8: inout bit;
A9: inout bit;
A10: inout bit;
A11: inout bit;
A12: inout bit;
A13: inout bit;
A14: inout bit;
A15: inout bit;
XBOOT: in bit;
IREQA_B: in bit;
DE_B: out bit;
RESET_B: in bit;
TCS: linkage bit;
TCK: in bit;
TRST_B: in bit;
TMS: in bit;
TDO: out bit;
TDI: in bit;
IREQB_B: in bit;
STCK: inout bit;
STFS: inout bit;
STD: inout bit;
SRCK: inout bit;
SRFS: inout bit;
SRD: inout bit;
POWER_IO5: linkage bit;
CLKO: out bit;
GROUND_IO5: linkage bit;
EXTAL: linkage bit;
XTAL: linkage bit;
VSSA_PLL: linkage bit;
VDDA_PLL: linkage bit;
VSSA_ADC: linkage bit;
VREFLO: linkage bit;
VREFP: linkage bit;
VREFN: linkage bit;
VREFHI: linkage bit;
VREFMID: linkage bit;
VDDA_ADC: linkage bit;
ANA0: linkage bit;
ANA1: linkage bit;
ANA2: linkage bit;
ANA3: linkage bit;
ANA4: linkage bit;
ANA5: linkage bit;
ANA6: linkage bit;
ANA7: linkage bit;
ANA8: linkage bit;
ANA9: linkage bit;
GROUND_CORE2: linkage bit;
POWER_CORE2: linkage bit;
POWER_IO3: linkage bit;
GROUND_IO3: linkage bit;
PCS2: out bit;
PCS3: out bit;
PCS4: out bit;
PCS5: out bit;
PCS6: out bit;
PCS7: out bit;
VPP: linkage bit;
MPIOD7: inout bit;
MPIOD6: inout bit;
MPIOD5: inout bit;
MPIOD4: inout bit;
MPIOD3: inout bit;
MPIOD2: inout bit;
MPIOD1: inout bit;
MPIOD0: inout bit;
SS_B: inout bit;
MISO: inout bit;
MOSI: inout bit;
SCLK: inout bit;
RXD2: inout bit;
TXD2: inout bit;
RXD1: in bit;
TXD1: inout bit;
RXD0: inout bit;
TXD0: inout bit;
TA3: inout bit;
TA2: inout bit;
TA1: inout bit;
TA0: inout bit;
POWER_IO1: linkage bit;
GROUND_IO1: linkage bit;
GROUND_CORE1: linkage bit;
POWER_CORE1: linkage bit;
MPIOB7: inout bit;
MPIOB6: inout bit;
MPIOB5: inout bit;
MPIOB4: inout bit;
MPIOB3: inout bit;
MPIOB2: inout bit;
MPIOB1: inout bit;
MPIOB0: inout bit;
D0: inout bit;
D1: inout bit;
D2: inout bit;
D3: inout bit;
D4: inout bit;
D5: inout bit;
D6: inout bit);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of DSP56F827 : entity is "STD_1149_1_1993";
attribute PIN_MAP of DSP56F827 : entity is PHYSICAL_PIN_MAP;
constant P128LQFP : PIN_MAP_STRING :=
"POWER_IO10: 1, " &
"GROUND_IO10: 2, " &
"D7: 3, " &
"D8: 4, " &
"D9: 5, " &
"D10: 6, " &
"D11: 7, " &
"D12: 8, " &
"D13: 9, " &
"D14: 10, " &
"D15: 11, " &
"RD_B: 12, " &
"WR_B: 13, " &
"DS_B: 14, " &
"PS_B: 15, " &
"POWER_CORE3: 16, " &
"GROUND_CORE3: 17, " &
"A0: 18, " &
"A1: 19, " &
"A2: 20, " &
"A3: 21, " &
"A4: 22, " &
"A5: 23, " &
"A6: 24, " &
"A7: 25, " &
"POWER_IO7: 26, " &
"GROUND_IO7: 27, " &
"A8: 28, " &
"A9: 29, " &
"A10: 30, " &
"A11: 31, " &
"A12: 32, " &
"A13: 33, " &
"A14: 34, " &
"A15: 35, " &
"XBOOT: 36, " &
"IREQA_B: 37, " &
"DE_B: 38, " &
"RESET_B: 39, " &
"TCS: 40, " &
"TCK: 41, " &
"TRST_B: 42, " &
"TMS: 43, " &
"TDO: 44, " &
"TDI: 45, " &
"IREQB_B: 46, " &
"STCK: 47, " &
"STFS: 48, " &
"STD: 49, " &
"SRCK: 50, " &
"SRFS: 51, " &
"SRD: 52, " &
"POWER_IO5: 53, " &
"CLKO: 54, " &
"GROUND_IO5: 55, " &
"EXTAL: 56, " &
"XTAL: 57, " &
"VSSA_PLL: 58, " &
"VDDA_PLL: 59, " &
"VSSA_ADC: 60, " &
"VREFLO: 61, " &
"VREFP: 62, " &
"VREFN: 63, " &
"VREFHI: 64, " &
"VREFMID: 65, " &
"VDDA_ADC: 66, " &
"ANA0: 67, " &
"ANA1: 68, " &
"ANA2: 69, " &
"ANA3: 70, " &
"ANA4: 71, " &
"ANA5: 72, " &
"ANA6: 73, " &
"ANA7: 74, " &
"ANA8: 75, " &
"ANA9: 76, " &
"GROUND_CORE2: 77, " &
"POWER_CORE2: 78, " &
"POWER_IO3: 79, " &
"GROUND_IO3: 80, " &
"PCS2: 81, " &
"PCS3: 82, " &
"PCS4: 83, " &
"PCS5: 84, " &
"PCS6: 85, " &
"PCS7: 86, " &
"VPP: 87, " &
"MPIOD7: 88, " &
"MPIOD6: 89, " &
"MPIOD5: 90, " &
"MPIOD4: 91, " &
"MPIOD3: 92, " &
"MPIOD2: 93, " &
"MPIOD1: 94, " &
"MPIOD0: 95, " &
"SS_B: 96, " &
"MISO: 97, " &
"MOSI: 98, " &
"SCLK: 99, " &
"RXD2: 100, " &
"TXD2: 101, " &
"RXD1: 102, " &
"TXD1: 103, " &
"RXD0: 104, " &
"TXD0: 105, " &
"TA3: 106, " &
"TA2: 107, " &
"TA1: 108, " &
"TA0: 109, " &
"POWER_IO1: 110, " &
"GROUND_IO1: 111, " &
"GROUND_CORE1: 112, " &
"POWER_CORE1: 113, " &
"MPIOB7: 114, " &
"MPIOB6: 115, " &
"MPIOB5: 116, " &
"MPIOB4: 117, " &
"MPIOB3: 118, " &
"MPIOB2: 119, " &
"MPIOB1: 120, " &
"MPIOB0: 121, " &
"D0: 122, " &
"D1: 123, " &
"D2: 124, " &
"D3: 125, " &
"D4: 126, " &
"D5: 127, " &
"D6: 128 ";
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_RESET of TRST_B : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);
attribute INSTRUCTION_LENGTH of DSP56F827 : entity is 4;
attribute INSTRUCTION_OPCODE of DSP56F827 : entity is
"EXTEST (0000)," &
"SAMPLE (0001)," &
"IDCODE (0010)," &
"CLAMP (0101)," &
"HIGHZ (0100)," &
"EXTEST_PULLUP (0011)," &
"ENABLE_ONCE (0110)," &
"DEBUG_REQUEST (0111)," &
"BYPASS (1111)";
attribute INSTRUCTION_CAPTURE of DSP56F827 : entity is "0001";
attribute INSTRUCTION_PRIVATE of DSP56F827 : entity is
"ENABLE_ONCE, DEBUG_REQUEST ";
attribute IDCODE_REGISTER of DSP56F827 : entity is
"00000001111100111011000000011101";
attribute REGISTER_ACCESS of DSP56F827 : entity is
"BOUNDARY (EXTEST_PULLUP)," &
"BYPASS (ENABLE_ONCE, DEBUG_REQUEST)" ;
attribute BOUNDARY_LENGTH of DSP56F827 : entity is 305;
attribute BOUNDARY_REGISTER of DSP56F827 : entity is
-- num cell port func safe [ccell dis rslt]
"0 (BC_1, D7, input, X)," &
"1 (BC_1, D7, output3, X, 2, 1, Z)," &
"2 (BC_1, *, control, 1)," &
"3 (BC_1, *, internal, 1)," &
"4 (BC_1, D8, input, X)," &
"5 (BC_1, D8, output3, X, 6, 1, Z)," &
"6 (BC_1, *, control, 1)," &
"7 (BC_1, *, internal, 1)," &
"8 (BC_1, D9, input, X)," &
"9 (BC_1, D9, output3, X, 10, 1, Z)," &
"10 (BC_1, *, control, 1)," &
"11 (BC_1, *, internal, 1)," &
"12 (BC_1, D10, input, X)," &
"13 (BC_1, D10, output3, X, 14, 1, Z)," &
"14 (BC_1, *, control, 1)," &
"15 (BC_1, *, internal, 1)," &
"16 (BC_1, D11, input, X)," &
"17 (BC_1, D11, output3, X, 18, 1, Z)," &
"18 (BC_1, *, control, 1)," &
"19 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"20 (BC_1, D12, input, X)," &
"21 (BC_1, D12, output3, X, 22, 1, Z)," &
"22 (BC_1, *, control, 1)," &
"23 (BC_1, *, internal, 1)," &
"24 (BC_1, D13, input, X)," &
"25 (BC_1, D13, output3, X, 26, 1, Z)," &
"26 (BC_1, *, control, 1)," &
"27 (BC_1, *, internal, 1)," &
"28 (BC_1, D14, input, X)," &
"29 (BC_1, D14, output3, X, 30, 1, Z)," &
"30 (BC_1, *, control, 1)," &
"31 (BC_1, *, internal, 1)," &
"32 (BC_1, D15, input, X)," &
"33 (BC_1, D15, output3, X, 34, 1, Z)," &
"34 (BC_1, *, control, 1)," &
"35 (BC_1, *, internal, 1)," &
"36 (BC_1, RD_B, input, X)," &
"37 (BC_1, RD_B, output3, X, 38, 1, Z)," &
"38 (BC_1, *, control, 1)," &
"39 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"40 (BC_1, WR_B, input, X)," &
"41 (BC_1, WR_B, output3, X, 42, 1, Z)," &
"42 (BC_1, *, control, 1)," &
"43 (BC_1, *, internal, 1)," &
"44 (BC_1, DS_B, input, X)," &
"45 (BC_1, DS_B, output3, X, 46, 1, Z)," &
"46 (BC_1, *, control, 1)," &
"47 (BC_1, *, internal, 1)," &
"48 (BC_1, PS_B, input, X)," &
"49 (BC_1, PS_B, output3, X, 50, 1, Z)," &
"50 (BC_1, *, control, 1)," &
"51 (BC_1, *, internal, 1)," &
"52 (BC_1, A0, input, X)," &
"53 (BC_1, A0, output3, X, 54, 1, Z)," &
"54 (BC_1, *, control, 1)," &
"55 (BC_1, *, internal, 1)," &
"56 (BC_1, A1, input, X)," &
"57 (BC_1, A1, output3, X, 58, 1, Z)," &
"58 (BC_1, *, control, 1)," &
"59 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"60 (BC_1, A2, input, X)," &
"61 (BC_1, A2, output3, X, 62, 1, Z)," &
"62 (BC_1, *, control, 1)," &
"63 (BC_1, *, internal, 1)," &
"64 (BC_1, A3, input, X)," &
"65 (BC_1, A3, output3, X, 66, 1, Z)," &
"66 (BC_1, *, control, 1)," &
"67 (BC_1, *, internal, 1)," &
"68 (BC_1, A4, input, X)," &
"69 (BC_1, A4, output3, X, 70, 1, Z)," &
"70 (BC_1, *, control, 1)," &
"71 (BC_1, *, internal, 1)," &
"72 (BC_1, A5, input, X)," &
"73 (BC_1, A5, output3, X, 74, 1, Z)," &
"74 (BC_1, *, control, 1)," &
"75 (BC_1, *, internal, 1)," &
"76 (BC_1, A6, input, X)," &
"77 (BC_1, A6, output3, X, 78, 1, Z)," &
"78 (BC_1, *, control, 1)," &
"79 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"80 (BC_1, A7, input, X)," &
"81 (BC_1, A7, output3, X, 82, 1, Z)," &
"82 (BC_1, *, control, 1)," &
"83 (BC_1, *, internal, 1)," &
"84 (BC_1, A8, input, X)," &
"85 (BC_1, A8, output3, X, 86, 1, Z)," &
"86 (BC_1, *, control, 1)," &
"87 (BC_1, *, internal, 1)," &
"88 (BC_1, A9, input, X)," &
"89 (BC_1, A9, output3, X, 90, 1, Z)," &
"90 (BC_1, *, control, 1)," &
"91 (BC_1, *, internal, 1)," &
"92 (BC_1, A10, input, X)," &
"93 (BC_1, A10, output3, X, 94, 1, Z)," &
"94 (BC_1, *, control, 1)," &
"95 (BC_1, *, internal, 1)," &
"96 (BC_1, A11, input, X)," &
"97 (BC_1, A11, output3, X, 98, 1, Z)," &
"98 (BC_1, *, control, 1)," &
"99 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"100 (BC_1, A12, input, X)," &
"101 (BC_1, A12, output3, X, 102, 1, Z)," &
"102 (BC_1, *, control, 1)," &
"103 (BC_1, *, internal, 1)," &
"104 (BC_1, A13, input, X)," &
"105 (BC_1, A13, output3, X, 106, 1, Z)," &
"106 (BC_1, *, control, 1)," &
"107 (BC_1, *, internal, 1)," &
"108 (BC_1, A14, input, X)," &
"109 (BC_1, A14, output3, X, 110, 1, Z)," &
"110 (BC_1, *, control, 1)," &
"111 (BC_1, *, internal, 1)," &
"112 (BC_1, A15, input, X)," &
"113 (BC_1, A15, output3, X, 114, 1, Z)," &
"114 (BC_1, *, control, 1)," &
"115 (BC_1, *, internal, 1)," &
"116 (BC_1, XBOOT, input, X)," &
"117 (BC_1, IREQA_B, input, X)," &
"118 (BC_1, DE_B, output3, X, 119, 1, Z)," &
"119 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"120 (BC_1, RESET_B, input, X)," &
"121 (BC_1, IREQB_B, input, X)," &
"122 (BC_1, STCK, input, X)," &
"123 (BC_1, STCK, output3, X, 124, 1, Z)," &
"124 (BC_1, *, control, 1)," &
"125 (BC_1, *, internal, 1)," &
"126 (BC_1, STFS, input, X)," &
"127 (BC_1, STFS, output3, X, 128, 1, Z)," &
"128 (BC_1, *, control, 1)," &
"129 (BC_1, *, internal, 1)," &
"130 (BC_1, STD, input, X)," &
"131 (BC_1, STD, output3, X, 132, 1, Z)," &
"132 (BC_1, *, control, 1)," &
"133 (BC_1, *, internal, 1)," &
"134 (BC_1, SRCK, input, X)," &
"135 (BC_1, SRCK, output3, X, 136, 1, Z)," &
"136 (BC_1, *, control, 1)," &
"137 (BC_1, *, internal, 1)," &
"138 (BC_1, SRFS, input, X)," &
"139 (BC_1, SRFS, output3, X, 140, 1, Z)," &
-- num cell port func safe [ccell dis rslt]
"140 (BC_1, *, control, 1)," &
"141 (BC_1, *, internal, 1)," &
"142 (BC_1, SRD, input, X)," &
"143 (BC_1, SRD, output3, X, 144, 1, Z)," &
"144 (BC_1, *, control, 1)," &
"145 (BC_1, *, internal, 1)," &
"146 (BC_1, CLKO, output3, X, 147, 1, Z)," &
"147 (BC_1, *, control, 1)," &
"148 (BC_1, PCS2, output3, X, 149, 1, Z)," &
"149 (BC_1, *, control, 1)," &
"150 (BC_1, PCS3, output3, X, 151, 1, Z)," &
"151 (BC_1, *, control, 1)," &
"152 (BC_1, PCS4, output3, X, 153, 1, Z)," &
"153 (BC_1, *, control, 1)," &
"154 (BC_1, PCS5, output3, X, 155, 1, Z)," &
"155 (BC_1, *, control, 1)," &
"156 (BC_1, PCS6, output3, X, 157, 1, Z)," &
"157 (BC_1, *, control, 1)," &
"158 (BC_1, PCS7, output3, X, 159, 1, Z)," &
"159 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"160 (BC_1, MPIOD7, input, X)," &
"161 (BC_1, MPIOD7, output3, X, 162, 1, Z)," &
"162 (BC_1, *, control, 1)," &
"163 (BC_1, *, internal, 1)," &
"164 (BC_1, MPIOD6, input, X)," &
"165 (BC_1, MPIOD6, output3, X, 166, 1, Z)," &
"166 (BC_1, *, control, 1)," &
"167 (BC_1, *, internal, 1)," &
"168 (BC_1, MPIOD5, input, X)," &
"169 (BC_1, MPIOD5, output3, X, 170, 1, Z)," &
"170 (BC_1, *, control, 1)," &
"171 (BC_1, *, internal, 1)," &
"172 (BC_1, MPIOD4, input, X)," &
"173 (BC_1, MPIOD4, output3, X, 174, 1, Z)," &
"174 (BC_1, *, control, 1)," &
"175 (BC_1, *, internal, 1)," &
"176 (BC_1, MPIOD3, input, X)," &
"177 (BC_1, MPIOD3, output3, X, 178, 1, Z)," &
"178 (BC_1, *, control, 1)," &
"179 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"180 (BC_1, MPIOD2, input, X)," &
"181 (BC_1, MPIOD2, output3, X, 182, 1, Z)," &
"182 (BC_1, *, control, 1)," &
"183 (BC_1, *, internal, 1)," &
"184 (BC_1, MPIOD1, input, X)," &
"185 (BC_1, MPIOD1, output3, X, 186, 1, Z)," &
"186 (BC_1, *, control, 1)," &
"187 (BC_1, *, internal, 1)," &
"188 (BC_1, MPIOD0, input, X)," &
"189 (BC_1, MPIOD0, output3, X, 190, 1, Z)," &
"190 (BC_1, *, control, 1)," &
"191 (BC_1, *, internal, 1)," &
"192 (BC_1, SS_B, input, X)," &
"193 (BC_1, SS_B, output3, X, 194, 1, Z)," &
"194 (BC_1, *, control, 1)," &
"195 (BC_1, *, internal, 1)," &
"196 (BC_1, MISO, input, X)," &
"197 (BC_1, MISO, output3, X, 198, 1, Z)," &
"198 (BC_1, *, control, 1)," &
"199 (BC_1, *, internal, 1)," &
-- num cell port func safe [ccell dis rslt]
"200 (BC_1, MOSI, input, X)," &
"201 (BC_1, MOSI, output3, X, 202, 1, Z)," &
"202 (BC_1, *, control, 1)," &
"203 (BC_1, *, internal, 1)," &
"204 (BC_1, SCLK, input, X)," &
"205 (BC_1, SCLK, output3, X, 206, 1, Z)," &
"206 (BC_1, *, control, 1)," &
"207 (BC_1, *, internal, 1)," &
"208 (BC_1, RXD2, input, X)," &
"209 (BC_1, RXD2, output3, X, 210, 1, Z)," &
"210 (BC_1, *, control, 1)," &
"211 (BC_1, *, internal, 1)," &
"212 (BC_1, TXD2, input, X)," &
"213 (BC_1, TXD2, output3, X, 214, 1, Z)," &
"214 (BC_1, *, control, 1)," &
"215 (BC_1, *, internal, 1)," &
"216 (BC_1, RXD1, input, X)," &
"217 (BC_1, TXD1, input, X)," &
"218 (BC_1, TXD1, output3, X, 219, 1, Z)," &
"219 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"220 (BC_1, *, internal, 1)," &
"221 (BC_1, RXD0, input, X)," &
"222 (BC_1, RXD0, output3, X, 223, 1, Z)," &
"223 (BC_1, *, control, 1)," &
"224 (BC_1, *, internal, 1)," &
"225 (BC_1, TXD0, input, X)," &
"226 (BC_1, TXD0, output3, X, 227, 1, Z)," &
"227 (BC_1, *, control, 1)," &
"228 (BC_1, *, internal, 1)," &
"229 (BC_1, TA3, input, X)," &
"230 (BC_1, TA3, output3, X, 231, 1, Z)," &
"231 (BC_1, *, control, 1)," &
"232 (BC_1, *, internal, 1)," &
"233 (BC_1, TA2, input, X)," &
"234 (BC_1, TA2, output3, X, 235, 1, Z)," &
"235 (BC_1, *, control, 1)," &
"236 (BC_1, *, internal, 1)," &
"237 (BC_1, TA1, input, X)," &
"238 (BC_1, TA1, output3, X, 239, 1, Z)," &
"239 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"240 (BC_1, *, internal, 1)," &
"241 (BC_1, TA0, input, X)," &
"242 (BC_1, TA0, output3, X, 243, 1, Z)," &
"243 (BC_1, *, control, 1)," &
"244 (BC_1, *, internal, 1)," &
"245 (BC_1, MPIOB7, input, X)," &
"246 (BC_1, MPIOB7, output3, X, 247, 1, Z)," &
"247 (BC_1, *, control, 1)," &
"248 (BC_1, *, internal, 1)," &
"249 (BC_1, MPIOB6, input, X)," &
"250 (BC_1, MPIOB6, output3, X, 251, 1, Z)," &
"251 (BC_1, *, control, 1)," &
"252 (BC_1, *, internal, 1)," &
"253 (BC_1, MPIOB5, input, X)," &
"254 (BC_1, MPIOB5, output3, X, 255, 1, Z)," &
"255 (BC_1, *, control, 1)," &
"256 (BC_1, *, internal, 1)," &
"257 (BC_1, MPIOB4, input, X)," &
"258 (BC_1, MPIOB4, output3, X, 259, 1, Z)," &
"259 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"260 (BC_1, *, internal, 0)," &
"261 (BC_1, MPIOB3, input, X)," &
"262 (BC_1, MPIOB3, output3, X, 263, 1, Z)," &
"263 (BC_1, *, control, 1)," &
"264 (BC_1, *, internal, 1)," &
"265 (BC_1, MPIOB2, input, X)," &
"266 (BC_1, MPIOB2, output3, X, 267, 1, Z)," &
"267 (BC_1, *, control, 1)," &
"268 (BC_1, *, internal, 1)," &
"269 (BC_1, MPIOB1, input, X)," &
"270 (BC_1, MPIOB1, output3, X, 271, 1, Z)," &
"271 (BC_1, *, control, 1)," &
"272 (BC_1, *, internal, 1)," &
"273 (BC_1, MPIOB0, input, X)," &
"274 (BC_1, MPIOB0, output3, X, 275, 1, Z)," &
"275 (BC_1, *, control, 1)," &
"276 (BC_1, *, internal, 1)," &
"277 (BC_1, D0, input, X)," &
"278 (BC_1, D0, output3, X, 279, 1, Z)," &
"279 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"280 (BC_1, *, internal, 1)," &
"281 (BC_1, D1, input, X)," &
"282 (BC_1, D1, output3, X, 283, 1, Z)," &
"283 (BC_1, *, control, 1)," &
"284 (BC_1, *, internal, 1)," &
"285 (BC_1, D2, input, X)," &
"286 (BC_1, D2, output3, X, 287, 1, Z)," &
"287 (BC_1, *, control, 1)," &
"288 (BC_1, *, internal, 1)," &
"289 (BC_1, D3, input, X)," &
"290 (BC_1, D3, output3, X, 291, 1, Z)," &
"291 (BC_1, *, control, 1)," &
"292 (BC_1, *, internal, 1)," &
"293 (BC_1, D4, input, X)," &
"294 (BC_1, D4, output3, X, 295, 1, Z)," &
"295 (BC_1, *, control, 1)," &
"296 (BC_1, *, internal, 1)," &
"297 (BC_1, D5, input, X)," &
"298 (BC_1, D5, output3, X, 299, 1, Z)," &
"299 (BC_1, *, control, 1)," &
-- num cell port func safe [ccell dis rslt]
"300 (BC_1, *, internal, 1)," &
"301 (BC_1, D6, input, X)," &
"302 (BC_1, D6, output3, X, 303, 1, Z)," &
"303 (BC_1, *, control, 1)," &
"304 (BC_1, *, internal, 1)";
end DSP56F827;