--********************************************************************
--** Copyright (c) 2001 Cypress Semiconductor
--** All rights reserved.
--**
--** File Name: cyp15g0201-DXA.bsdl
--** Release: 1.0
--** Last Updated: July 17, 2002
--**
--** Function: Quad HOTLink-II Tranceiver, BSDL file for JTAG
--** Part #: CYP15G0201DXA-BGC
--**
--** Notes:
--** IMPORTANT NOTE: Please be aware that the CYP15G0201DXA-BGC Quad
--** HOTLink-II Tranceiver device is not 1149.1 compliant. Therefore,
--** the BSDL simulation file given below is intended as an example.
--** Ref CYP15G0201DXA-BGC Datasheet at www.cypress.com
--**
--** The incompatibility of the BSDL file is due to the fact that the
--** the chip reset and the JTAG reset (TRSTZn) are the same signals.
--**
--** The CYP15G0201DXA-BGC has 12 tri-level select control signals.
--** These signals are SDASEL, SPDSEL, PARCTL, RFMODE etc.
--** The tri state is implemented in the BSDL file as follows:
--** Input vector : 11 => HIGH
--** Input vector : 10 => MID, where 1 is the MSB and 0 is the LSB.
--** Input vector : 00 => LOW.
--** MSB is the higher register no. and LSB is the lower register no.
--**
--** Analog Input Assoc. Cells Analog Input Voltage, Capture Value
--** (MSB, LSB)
--** ------------ ------------ ------------------------------------
--** SDASEL 170, 169 (HIGH, 11), (MID/OPEN, 10), (LOW, 00)
--** SPDSEL 168, 167 (HIGH, 11), (MID/OPEN, 10), (LOW, 00)
--** PARCTL 166, 165 (HIGH, 11), (MID/OPEN, 10), (LOW, 00)
--** RFMODE 164, 163 (HIGH, 11), (MID/OPEN, 10), (LOW, 00)
--** RXCKSEL 155, 154 (HIGH, 11), (MID/OPEN, 10), (LOW, 00)
--** TXCKSEL 150, 149 (HIGH, 11), (MID/OPEN, 10), (LOW, 00)
--** DECMODE 23, 22 (HIGH, 11), (MID/OPEN, 10), (LOW, 00)
--** FRAMCHAR 20, 19 (HIGH, 11), (MID/OPEN, 10), (LOW, 00)
--** TXMODE(0) 14, 13 (HIGH, 11), (MID/OPEN, 10), (LOW, 00)
--** TXMODE(1) 12, 11 (HIGH, 11), (MID/OPEN, 10), (LOW, 00)
--** RXMODE(0) 10, 9 (HIGH, 11), (MID/OPEN, 10), (LOW, 00)
--** RXMODE(1) 8, 7 (HIGH, 11), (MID/OPEN, 10), (LOW, 00)
--**
--** The CYP15G0201DXB-BGC revision of this device will be 1149.1
--** compliant. In this case, the TRSTZn will function as the chip
--** reset only. The JTAG will have a power-on-reset. The changes
--** needed to be made to the BSDL file is to comment out the
--** following line.
--** -- attribute TAP_SCAN_RESET of TRSTZn: signal is true;
--**
--** Queries ?: Contact DCD Applications at 408-943-2891
--********************************************************************
entity cyp15g0201 is
-- This section identifies the device package selected.
generic (PHYSICAL_PIN_MAP: string:= "BGC_196");
-- This section declares all the ports of the device.
port (
BISTLE : in bit;
DECMODE : in bit;
FRAMCHAR : in bit;
INA1p : linkage bit;
INA1n : linkage bit;
INA2p : linkage bit;
INA2n : linkage bit;
INB1p : linkage bit;
INB1n : linkage bit;
INB2p : linkage bit;
INB2n : linkage bit;
INSELA : in bit;
INSELB : in bit;
LPEN : in bit;
OELE : in bit;
PARCTL : in bit;
REFCLKn : in bit;
REFCLKp : in bit;
RFEN : in bit;
RFMODE : in bit;
RXCKSEL : in bit;
RXLE : in bit;
RXRATE : in bit;
SCSEL : in bit;
SDASEL : in bit;
SPDSEL : in bit;
TCLK : in bit;
TDI : in bit;
TMS : in bit;
TRSTZn : in bit;
TXCKSEL : in bit;
TXCLKA : in bit;
TXCLKB : in bit;
TXOPA : in bit;
TXOPB : in bit;
TXRATE : in bit;
TXRSTn : in bit;
VCC : linkage bit_vector (0 to 31);
GND : linkage bit_vector (0 to 39);
BOE : in bit_vector (0 to 3);
RXMODE : in bit_vector (0 to 1);
TXCTA : in bit_vector (0 to 1);
TXCTB : in bit_vector (0 to 1);
TXDA : in bit_vector (0 to 7);
TXDB : in bit_vector (0 to 7);
TXMODE : in bit_vector (0 to 1);
RXCLKAp : inout bit;
RXCLKBp : inout bit;
OUTA1n : linkage bit;
OUTA1p : linkage bit;
OUTA2n : linkage bit;
OUTA2p : linkage bit;
OUTB1n : linkage bit;
OUTB1p : linkage bit;
OUTB2n : linkage bit;
OUTB2p : linkage bit;
RXCLKAn : out bit;
RXCLKBn : out bit;
RXOPA : out bit;
RXOPB : out bit;
TDO : out bit;
TXCLKOn : out bit;
TXCLKOp : out bit;
LFIAn : out bit;
LFIBn : out bit;
TXPERA : out bit;
TXPERB : out bit;
RXDA : out bit_vector (0 to 7);
RXDB : out bit_vector (0 to 7);
RXSTA : out bit_vector (0 to 2);
RXSTB : out bit_vector (0 to 2)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of cyp15g0201: entity is "STD_1149_1_1993";
attribute PIN_MAP of cyp15g0201: entity is PHYSICAL_PIN_MAP;
-- This section specifies the pin map for each port. This information
-- is extracted from the port-to-pin map file that was read in using
-- the "read_pin_map" command.
constant BGC_196: PIN_MAP_STRING :=
"BISTLE : E1," &
"DECMODE : F1," &
"FRAMCHAR : E2," &
"INA1p : A5," &
"INA1n : B5," &
"INA2p : A2," &
"INA2n : B2," &
"INB1p : A12," &
"INB1n : B12," &
"INB2p : A9," &
"INB2n : B9," &
"INSELA : D12," &
"INSELB : D11," &
"LPEN : C4," &
"OELE : F2," &
"PARCTL : C10," &
"REFCLKn : N9," &
"REFCLKp : P9," &
"RFEN : C2," &
"RFMODE : C11," &
"RXCKSEL : E12," &
"RXLE : D18," &
"RXRATE : C5," &
"SCSEL : L9," &
"SDASEL : C13," &
"SPDSEL : C9," &
"TCLK : D9," &
"TDI : D10," &
"TMS : E14," &
"TRSTZn : E13," &
"TXCKSEL : E11," &
"TXCLKA : K6," &
"TXCLKB : K14," &
"TXOPA : L6," &
"TXOPB : E9," &
"TXRATE : D4," &
"TXRSTn : M9," &
"VCC : (A1, A4, A7, A8, A11, A14, B4, B11, " &
" C3, C12, D1, D2, D13, D14, G1, G14, " &
" H1, H14, L1, L2, L13, L14, M3, M12, " &
" N4, N11, P1, P4, P7, P8, P11, P14)," &
"GND : (C7, C8, D7, D8, E7, E8, F6, F7, " &
" F8, F9, G3, G4, G5, G6, G7, G8, " &
" G9, G10, G11, G12, H3, H4, H5, H6, " &
" H7, H8, H9, H10, H11, H12, J6, J7, " &
" J8, J9, K7, K8, L7, L8, M7, M8)," &
"BOE : (E5, E6, C14, B14)," &
"RXMODE : (D6, D5)," &
"TXCTA : (N2, M2)," &
"TXCTB : (J10, J11)," &
"TXDA : (P5, N5, M5, L5, K5, P3, N3, P2)," &
"TXDB : (F14, F13, F12, F11, F10, J14, J13, J12)," &
"TXMODE : (E4, E3)," &
"OUTA1n : A6," &
"OUTA1p : B6," &
"OUTA2n : A3," &
"OUTA2p : B3," &
"OUTB1n : A13," &
"OUTB1p : B13," &
"OUTB2n : A10," &
"OUTB2p : B10," &
"RXCLKAn : M1," &
"RXCLKAp : N1," &
"RXCLKBn : K12," &
"RXCLKBp : K11," &
"RXOPA : J2," &
"RXOPB : K10," &
"TDO : B1," &
"TXCLKOn : P10," &
"TXCLKOp : N10," &
"LFIAn : L4," &
"LFIBn : K13," &
"TXPERA : M6," &
"TXPERB : E10," &
"RXDA : (J3, J4, J5, K1, K2, K3, K4, L3)," &
"RXDB : (P13, P12, N12, N13, N14, M13, M14, L12)," &
"RXSTA : (J1, F5, F4)," &
"RXSTB : (M11, L11, L10)";
-- This section specifies the TAP ports.
-- For the TAP TCK port, the parameters in the brackets are:
-- First Field : Maximum TCK frequency.
-- Second Field: Allowable states TCK may be stopped in.
attribute TAP_SCAN_CLOCK of TCLK : signal is (10.0e6, BOTH);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_RESET of TRSTZn: signal is true;
-- Specifies the number of bits in the instruction register.
attribute INSTRUCTION_LENGTH of cyp15g0201: entity is 3;
-- Specifies the boundary-scan instructions implemented in the
-- design and their opcodes.
attribute INSTRUCTION_OPCODE of cyp15g0201: entity is
"BYPASS (111)," &
"EXTEST (000)," &
"SAMPLE (001)," &
"IDCODE (010)," &
"USER1 (011)";
-- Specifies the bit pattern that is loaded into the instruction
-- register when the TAP controller passes through the Capture-IR
-- state. The standard mandates that the two LSBs must be "01".
-- The remaining bits are design specific.
attribute INSTRUCTION_CAPTURE of cyp15g0201: entity is "001";
-- Specifies the instruction opcode that is reserved for component
-- test during manufacture.
attribute INSTRUCTION_PRIVATE of cyp15g0201 : entity is
" USER1";
-- Specifies the bit pattern that is loaded into the DEVICE_ID
-- register during the IDCODE instruction when the TAP controller
-- passes through the Capture-DR state.
attribute IDCODE_REGISTER of cyp15g0201: entity is
"0000" & -- 4-bit version number
"1100100000001100" & -- 16-bit part number
"00000110100" & -- 11-bit identity of the manufacturer
"1"; -- Required by IEEE Std 1149.1
-- This section specifies the test data register placed between TDI
-- and TDO for each implemented instruction.
attribute REGISTER_ACCESS of cyp15g0201: entity is
"BYPASS (BYPASS)," &
"BOUNDARY (EXTEST, SAMPLE)," &
"DEVICE_ID (IDCODE)," &
"UTDR1[24] (USER1)";
-- Specifies the length of the boundary scan register.
attribute BOUNDARY_LENGTH of cyp15g0201: entity is 175;
-- The following list specifies the characteristics of each cell
-- in the boundary scan register from TDI to TDO.
-- The following is a description of the label fields:
-- num : Is the cell number.
-- cell : Is the cell type as defined by the standard.
-- port : Is the design port name. Control cells do not
-- have a port name.
-- function: Is the function of the cell as defined by the
-- standard. Is one of input, output2, output3,
-- bidir, control or controlr.
-- safe : Specifies the value that the BSR cell should be
-- loaded with for safe operation when the software
-- might otherwise choose a random value.
-- ccell : The control cell number. Specifies the control
-- cell that drives the output enable for this port.
-- disval : Specifies the value that is loaded into the
-- control cell to disable the output enable for
-- the corresponding port.
-- rslt : Resulting state. Shows the state of the driver
-- when it is disabled.
attribute BOUNDARY_REGISTER of cyp15g0201: entity is
--
-- num cell port function safe [ccell disval rslt]
--
"174 (BC_4, *, internal, X), " &
"173 (BC_4, *, internal, X), " &
"172 (BC_4, *, internal, X), " &
"171 (BC_4, *, internal, X), " &
"170 (BC_4, SDASEL, observe_only, X), " &
"169 (BC_4, SDASEL, observe_only, X), " &
"168 (BC_4, SPDSEL, observe_only, X), " &
"167 (BC_4, SPDSEL, observe_only, X), " &
"166 (BC_4, PARCTL, observe_only, X), " &
"165 (BC_4, PARCTL, observe_only, X), " &
"164 (BC_4, RFMODE, observe_only, X), " &
"163 (BC_4, RFMODE, observe_only, X), " &
"162 (BC_4, INSELB, observe_only, X), " &
"161 (BC_4, INSELA, observe_only, X), " &
"160 (BC_4, *, internal, X), " &
"159 (BC_4, *, internal, X), " &
"158 (BC_1, *, internal, X), " &
"157 (BC_4, *, internal, X), " &
"156 (BC_4, *, internal, X), " &
"155 (BC_4, RXCKSEL, observe_only, X), " &
"154 (BC_4, RXCKSEL, observe_only, X), " &
"153 (BC_4, *, internal, X), " &
"152 (BC_4, *, internal, X), " &
"151 (BC_4, *, internal, X), " &
"150 (BC_4, TXCKSEL, observe_only, X), " &
"149 (BC_4, TXCKSEL, observe_only, X), " &
"148 (BC_4, *, internal, X), " &
"147 (BC_4, *, internal, X), " &
"146 (BC_4, *, internal, X), " &
"145 (BC_4, *, internal, X), " &
"144 (BC_1, *, internal, X), " &
"143 (BC_4, *, internal, X), " &
"142 (BC_4, *, internal, X), " &
"141 (BC_4, *, internal, X), " &
"140 (BC_4, *, internal, X), " &
"139 (BC_1, *, internal, X), " &
"138 (BC_4, *, internal, X), " &
"137 (BC_1, *, controlr, 0), " &
"136 (BC_1, *, internal, X), " &
"135 (BC_1, *, internal, X), " &
"134 (BC_1, *, internal, X), " &
"133 (BC_1, *, internal, X), " &
"132 (BC_1, *, internal, X), " &
"131 (BC_1, *, internal, X), " &
"130 (BC_1, *, internal, X), " &
"129 (BC_1, *, internal, X), " &
"128 (BC_1, *, internal, X), " &
"127 (BC_1, *, internal, X), " &
"126 (BC_1, *, internal, X), " &
"125 (BC_1, *, internal, X), " &
"124 (BC_1, *, controlr, 0), " &
"123 (BC_1, *, internal, X), " &
"122 (BC_4, *, internal, X), " &
"121 (BC_4, *, internal, X), " &
"120 (BC_4, *, internal, X), " &
"119 (BC_4, *, internal, X), " &
"118 (BC_4, *, internal, X), " &
"117 (BC_4, *, internal, X), " &
"116 (BC_4, *, internal, X), " &
"115 (BC_4, *, internal, X), " &
"114 (BC_4, *, internal, X), " &
"113 (BC_4, *, internal, X), " &
"112 (BC_4, *, internal, X), " &
"111 (BC_4, *, internal, X), " &
"110 (BC_1, *, internal, X), " &
"109 (BC_1, *, internal, X), " &
"108 (BC_1, *, internal, X), " &
"107 (BC_1, *, internal, X), " &
"106 (BC_4, *, internal, X), " &
"105 (BC_1, *, controlr, 0), " &
"104 (BC_1, *, internal, X), " &
"103 (BC_1, *, internal, X), " &
"102 (BC_1, *, internal, X), " &
"101 (BC_1, *, internal, X), " &
"100 (BC_1, *, internal, X), " &
"99 (BC_1, *, internal, X), " &
"98 (BC_1, *, internal, X), " &
"97 (BC_1, *, internal, X), " &
"96 (BC_1, *, internal, X), " &
"95 (BC_1, *, internal, X), " &
"94 (BC_1, TXCLKOp, output2, X), " &
"93 (BC_1, *, internal, X), " &
"92 (BC_4, *, internal, X), " &
"91 (BC_1, *, controlr, 0), " &
"90 (BC_4, TXRSTn, observe_only, X), " &
"89 (BC_4, REFCLKp, observe_only, X), " &
"88 (BC_4, SCSEL, observe_only, X), " &
"87 (BC_4, *, internal, X), " &
"86 (BC_1, *, internal, X), " &
"85 (BC_4, *, internal, X), " &
"84 (BC_1, *, internal, X), " &
"83 (BC_4, *, internal, X), " &
"82 (BC_1, TXPERA, output2, X), " &
"81 (BC_4, TXOPA, observe_only, X), " &
"80 (BC_4, TXCLKA, observe_only, X), " &
"79 (BC_4, TXDA(0), observe_only, X), " &
"78 (BC_4, TXDA(1), observe_only, X), " &
"77 (BC_4, TXDA(2), observe_only, X), " &
"76 (BC_4, TXDA(3), observe_only, X), " &
"75 (BC_4, TXDA(4), observe_only, X), " &
"74 (BC_4, TXDA(5), observe_only, X), " &
"73 (BC_4, TXDA(6), observe_only, X), " &
"72 (BC_4, TXDA(7), observe_only, X), " &
"71 (BC_4, TXCTA(0), observe_only, X), " &
"70 (BC_4, TXCTA(1), observe_only, X), " &
"69 (BC_1, RXCLKAp, output3, X, 67, 0, Z), " &
"68 (BC_4, RXCLKAp, observe_only, X), " &
"67 (BC_1, *, controlr, 0), " &
"66 (BC_1, LFIAn, output2, X), " &
"65 (BC_1, RXDA(7), output2, X), " &
"64 (BC_1, RXDA(6), output2, X), " &
"63 (BC_1, RXDA(5), output2, X), " &
"62 (BC_1, RXDA(4), output2, X), " &
"61 (BC_1, RXDA(3), output2, X), " &
"60 (BC_1, RXDA(2), output2, X), " &
"59 (BC_1, RXDA(1), output2, X), " &
"58 (BC_1, RXDA(0), output2, X), " &
"57 (BC_1, RXOPA, output3, X, 124, 0, Z), " &
"56 (BC_1, RXSTA(0), output2, X), " &
"55 (BC_1, RXSTA(1), output2, X), " &
"54 (BC_1, RXSTA(2), output2, X), " &
"53 (BC_1, TXPERB, output2, X), " &
"52 (BC_4, TXOPB, observe_only, X), " &
"51 (BC_4, TXCLKB, observe_only, X), " &
"50 (BC_4, TXDB(0), observe_only, X), " &
"49 (BC_4, TXDB(1), observe_only, X), " &
"48 (BC_4, TXDB(2), observe_only, X), " &
"47 (BC_4, TXDB(3), observe_only, X), " &
"46 (BC_4, TXDB(4), observe_only, X), " &
"45 (BC_4, TXDB(5), observe_only, X), " &
"44 (BC_4, TXDB(6), observe_only, X), " &
"43 (BC_4, TXDB(7), observe_only, X), " &
"42 (BC_4, TXCTB(0), observe_only, X), " &
"41 (BC_4, TXCTB(1), observe_only, X), " &
"40 (BC_1, RXCLKBp, output3, X, 38, 0, Z), " &
"39 (BC_4, RXCLKBp, observe_only, X), " &
"38 (BC_1, *, controlr, 0), " &
"37 (BC_1, LFIBn, output2, X), " &
"36 (BC_1, RXDB(7), output2, X), " &
"35 (BC_1, RXDB(6), output2, X), " &
"34 (BC_1, RXDB(5), output2, X), " &
"33 (BC_1, RXDB(4), output2, X), " &
"32 (BC_1, RXDB(3), output2, X), " &
"31 (BC_1, RXDB(2), output2, X), " &
"30 (BC_1, RXDB(1), output2, X), " &
"29 (BC_1, RXDB(0), output2, X), " &
"28 (BC_1, RXSTB(0), output2, X), " &
"27 (BC_1, RXSTB(1), output2, X), " &
"26 (BC_1, RXSTB(2), output2, X), " &
"25 (BC_1, RXOPB, output3, X, 124, 0, Z), " &
"24 (BC_4, OELE, observe_only, X), " &
"23 (BC_4, DECMODE, observe_only, X), " &
"22 (BC_4, DECMODE, observe_only, X), " &
"21 (BC_4, BISTLE, observe_only, X), " &
"20 (BC_4, FRAMCHAR, observe_only, X), " &
"19 (BC_4, FRAMCHAR, observe_only, X), " &
"18 (BC_4, BOE(3), observe_only, X), " &
"17 (BC_4, BOE(2), observe_only, X), " &
"16 (BC_4, BOE(1), observe_only, X), " &
"15 (BC_4, BOE(0), observe_only, X), " &
"14 (BC_4, TXMODE(0), observe_only, X), " &
"13 (BC_4, TXMODE(0), observe_only, X), " &
"12 (BC_4, TXMODE(1), observe_only, X), " &
"11 (BC_4, TXMODE(1), observe_only, X), " &
"10 (BC_4, RXMODE(0), observe_only, X), " &
"9 (BC_4, RXMODE(0), observe_only, X), " &
"8 (BC_4, RXMODE(1), observe_only, X), " &
"7 (BC_4, RXMODE(1), observe_only, X), " &
"6 (BC_4, TXRATE, observe_only, X), " &
"5 (BC_4, *, internal, X), " &
"4 (BC_4, RXRATE, observe_only, X), " &
"3 (BC_4, RXLE, observe_only, X), " &
"2 (BC_4, LPEN, observe_only, X), " &
"1 (BC_4, RFEN, observe_only, X), " &
"0 (BC_4, *, internal, X) ";
end cyp15g0201;